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/drivers/staging/iio/meter/ade7854.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C Header | 176 lines | 159 code | 9 blank | 8 comment | 0 complexity | 5ae320d247f10557a926efdcfe775cb9 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1#ifndef _ADE7854_H
  2#define _ADE7854_H
  3
  4#define ADE7854_AIGAIN    0x4380
  5#define ADE7854_AVGAIN    0x4381
  6#define ADE7854_BIGAIN    0x4382
  7#define ADE7854_BVGAIN    0x4383
  8#define ADE7854_CIGAIN    0x4384
  9#define ADE7854_CVGAIN    0x4385
 10#define ADE7854_NIGAIN    0x4386
 11#define ADE7854_AIRMSOS   0x4387
 12#define ADE7854_AVRMSOS   0x4388
 13#define ADE7854_BIRMSOS   0x4389
 14#define ADE7854_BVRMSOS   0x438A
 15#define ADE7854_CIRMSOS   0x438B
 16#define ADE7854_CVRMSOS   0x438C
 17#define ADE7854_NIRMSOS   0x438D
 18#define ADE7854_AVAGAIN   0x438E
 19#define ADE7854_BVAGAIN   0x438F
 20#define ADE7854_CVAGAIN   0x4390
 21#define ADE7854_AWGAIN    0x4391
 22#define ADE7854_AWATTOS   0x4392
 23#define ADE7854_BWGAIN    0x4393
 24#define ADE7854_BWATTOS   0x4394
 25#define ADE7854_CWGAIN    0x4395
 26#define ADE7854_CWATTOS   0x4396
 27#define ADE7854_AVARGAIN  0x4397
 28#define ADE7854_AVAROS    0x4398
 29#define ADE7854_BVARGAIN  0x4399
 30#define ADE7854_BVAROS    0x439A
 31#define ADE7854_CVARGAIN  0x439B
 32#define ADE7854_CVAROS    0x439C
 33#define ADE7854_AFWGAIN   0x439D
 34#define ADE7854_AFWATTOS  0x439E
 35#define ADE7854_BFWGAIN   0x439F
 36#define ADE7854_BFWATTOS  0x43A0
 37#define ADE7854_CFWGAIN   0x43A1
 38#define ADE7854_CFWATTOS  0x43A2
 39#define ADE7854_AFVARGAIN 0x43A3
 40#define ADE7854_AFVAROS   0x43A4
 41#define ADE7854_BFVARGAIN 0x43A5
 42#define ADE7854_BFVAROS   0x43A6
 43#define ADE7854_CFVARGAIN 0x43A7
 44#define ADE7854_CFVAROS   0x43A8
 45#define ADE7854_VATHR1    0x43A9
 46#define ADE7854_VATHR0    0x43AA
 47#define ADE7854_WTHR1     0x43AB
 48#define ADE7854_WTHR0     0x43AC
 49#define ADE7854_VARTHR1   0x43AD
 50#define ADE7854_VARTHR0   0x43AE
 51#define ADE7854_RSV       0x43AF
 52#define ADE7854_VANOLOAD  0x43B0
 53#define ADE7854_APNOLOAD  0x43B1
 54#define ADE7854_VARNOLOAD 0x43B2
 55#define ADE7854_VLEVEL    0x43B3
 56#define ADE7854_DICOEFF   0x43B5
 57#define ADE7854_HPFDIS    0x43B6
 58#define ADE7854_ISUMLVL   0x43B8
 59#define ADE7854_ISUM      0x43BF
 60#define ADE7854_AIRMS     0x43C0
 61#define ADE7854_AVRMS     0x43C1
 62#define ADE7854_BIRMS     0x43C2
 63#define ADE7854_BVRMS     0x43C3
 64#define ADE7854_CIRMS     0x43C4
 65#define ADE7854_CVRMS     0x43C5
 66#define ADE7854_NIRMS     0x43C6
 67#define ADE7854_RUN       0xE228
 68#define ADE7854_AWATTHR   0xE400
 69#define ADE7854_BWATTHR   0xE401
 70#define ADE7854_CWATTHR   0xE402
 71#define ADE7854_AFWATTHR  0xE403
 72#define ADE7854_BFWATTHR  0xE404
 73#define ADE7854_CFWATTHR  0xE405
 74#define ADE7854_AVARHR    0xE406
 75#define ADE7854_BVARHR    0xE407
 76#define ADE7854_CVARHR    0xE408
 77#define ADE7854_AFVARHR   0xE409
 78#define ADE7854_BFVARHR   0xE40A
 79#define ADE7854_CFVARHR   0xE40B
 80#define ADE7854_AVAHR     0xE40C
 81#define ADE7854_BVAHR     0xE40D
 82#define ADE7854_CVAHR     0xE40E
 83#define ADE7854_IPEAK     0xE500
 84#define ADE7854_VPEAK     0xE501
 85#define ADE7854_STATUS0   0xE502
 86#define ADE7854_STATUS1   0xE503
 87#define ADE7854_OILVL     0xE507
 88#define ADE7854_OVLVL     0xE508
 89#define ADE7854_SAGLVL    0xE509
 90#define ADE7854_MASK0     0xE50A
 91#define ADE7854_MASK1     0xE50B
 92#define ADE7854_IAWV      0xE50C
 93#define ADE7854_IBWV      0xE50D
 94#define ADE7854_ICWV      0xE50E
 95#define ADE7854_VAWV      0xE510
 96#define ADE7854_VBWV      0xE511
 97#define ADE7854_VCWV      0xE512
 98#define ADE7854_AWATT     0xE513
 99#define ADE7854_BWATT     0xE514
100#define ADE7854_CWATT     0xE515
101#define ADE7854_AVA       0xE519
102#define ADE7854_BVA       0xE51A
103#define ADE7854_CVA       0xE51B
104#define ADE7854_CHECKSUM  0xE51F
105#define ADE7854_VNOM      0xE520
106#define ADE7854_PHSTATUS  0xE600
107#define ADE7854_ANGLE0    0xE601
108#define ADE7854_ANGLE1    0xE602
109#define ADE7854_ANGLE2    0xE603
110#define ADE7854_PERIOD    0xE607
111#define ADE7854_PHNOLOAD  0xE608
112#define ADE7854_LINECYC   0xE60C
113#define ADE7854_ZXTOUT    0xE60D
114#define ADE7854_COMPMODE  0xE60E
115#define ADE7854_GAIN      0xE60F
116#define ADE7854_CFMODE    0xE610
117#define ADE7854_CF1DEN    0xE611
118#define ADE7854_CF2DEN    0xE612
119#define ADE7854_CF3DEN    0xE613
120#define ADE7854_APHCAL    0xE614
121#define ADE7854_BPHCAL    0xE615
122#define ADE7854_CPHCAL    0xE616
123#define ADE7854_PHSIGN    0xE617
124#define ADE7854_CONFIG    0xE618
125#define ADE7854_MMODE     0xE700
126#define ADE7854_ACCMODE   0xE701
127#define ADE7854_LCYCMODE  0xE702
128#define ADE7854_PEAKCYC   0xE703
129#define ADE7854_SAGCYC    0xE704
130#define ADE7854_CFCYC     0xE705
131#define ADE7854_HSDC_CFG  0xE706
132#define ADE7854_CONFIG2   0xEC01
133
134#define ADE7854_READ_REG   0x1
135#define ADE7854_WRITE_REG  0x0
136
137#define ADE7854_MAX_TX    7
138#define ADE7854_MAX_RX    7
139#define ADE7854_STARTUP_DELAY 1
140
141#define ADE7854_SPI_SLOW	(u32)(300 * 1000)
142#define ADE7854_SPI_BURST	(u32)(1000 * 1000)
143#define ADE7854_SPI_FAST	(u32)(2000 * 1000)
144
145#define DRIVER_NAME		"ade7854"
146
147/**
148 * struct ade7854_state - device instance specific data
149 * @spi:			actual spi_device
150 * @indio_dev:		industrial I/O device structure
151 * @buf_lock:		mutex to protect tx and rx
152 * @tx:			transmit buffer
153 * @rx:			receive buffer
154 **/
155struct ade7854_state {
156	struct spi_device	*spi;
157	struct i2c_client	*i2c;
158	int			(*read_reg_8) (struct device *, u16, u8 *);
159	int			(*read_reg_16) (struct device *, u16, u16 *);
160	int			(*read_reg_24) (struct device *, u16, u32 *);
161	int			(*read_reg_32) (struct device *, u16, u32 *);
162	int			(*write_reg_8) (struct device *, u16, u8);
163	int			(*write_reg_16) (struct device *, u16, u16);
164	int			(*write_reg_24) (struct device *, u16, u32);
165	int			(*write_reg_32) (struct device *, u16, u32);
166	int			irq;
167	struct mutex		buf_lock;
168	u8			tx[ADE7854_MAX_TX] ____cacheline_aligned;
169	u8			rx[ADE7854_MAX_RX];
170
171};
172
173extern int ade7854_probe(struct iio_dev *indio_dev, struct device *dev);
174extern int ade7854_remove(struct iio_dev *indio_dev);
175
176#endif