/drivers/staging/gma500/psb_intel_sdvo_regs.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t · C Header · 338 lines · 198 code · 39 blank · 101 comment · 0 complexity · 56859db72d46eb8b0d9560d3f28b3466 MD5 · raw file

  1. /*
  2. * SDVO command definitions and structures.
  3. *
  4. * Copyright (c) 2008, Intel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program; if not, write to the Free Software Foundation, Inc.,
  17. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18. *
  19. * Authors:
  20. * Eric Anholt <eric@anholt.net>
  21. */
  22. #define SDVO_OUTPUT_FIRST (0)
  23. #define SDVO_OUTPUT_TMDS0 (1 << 0)
  24. #define SDVO_OUTPUT_RGB0 (1 << 1)
  25. #define SDVO_OUTPUT_CVBS0 (1 << 2)
  26. #define SDVO_OUTPUT_SVID0 (1 << 3)
  27. #define SDVO_OUTPUT_YPRPB0 (1 << 4)
  28. #define SDVO_OUTPUT_SCART0 (1 << 5)
  29. #define SDVO_OUTPUT_LVDS0 (1 << 6)
  30. #define SDVO_OUTPUT_TMDS1 (1 << 8)
  31. #define SDVO_OUTPUT_RGB1 (1 << 9)
  32. #define SDVO_OUTPUT_CVBS1 (1 << 10)
  33. #define SDVO_OUTPUT_SVID1 (1 << 11)
  34. #define SDVO_OUTPUT_YPRPB1 (1 << 12)
  35. #define SDVO_OUTPUT_SCART1 (1 << 13)
  36. #define SDVO_OUTPUT_LVDS1 (1 << 14)
  37. #define SDVO_OUTPUT_LAST (14)
  38. struct psb_intel_sdvo_caps {
  39. u8 vendor_id;
  40. u8 device_id;
  41. u8 device_rev_id;
  42. u8 sdvo_version_major;
  43. u8 sdvo_version_minor;
  44. unsigned int sdvo_inputs_mask:2;
  45. unsigned int smooth_scaling:1;
  46. unsigned int sharp_scaling:1;
  47. unsigned int up_scaling:1;
  48. unsigned int down_scaling:1;
  49. unsigned int stall_support:1;
  50. unsigned int pad:1;
  51. u16 output_flags;
  52. } __packed;
  53. /** This matches the EDID DTD structure, more or less */
  54. struct psb_intel_sdvo_dtd {
  55. struct {
  56. u16 clock; /**< pixel clock, in 10kHz units */
  57. u8 h_active; /**< lower 8 bits (pixels) */
  58. u8 h_blank; /**< lower 8 bits (pixels) */
  59. u8 h_high; /**< upper 4 bits each h_active, h_blank */
  60. u8 v_active; /**< lower 8 bits (lines) */
  61. u8 v_blank; /**< lower 8 bits (lines) */
  62. u8 v_high; /**< upper 4 bits each v_active, v_blank */
  63. } part1;
  64. struct {
  65. u8 h_sync_off;
  66. /**< lower 8 bits, from hblank start */
  67. u8 h_sync_width;/**< lower 8 bits (pixels) */
  68. /** lower 4 bits each vsync offset, vsync width */
  69. u8 v_sync_off_width;
  70. /**
  71. * 2 high bits of hsync offset, 2 high bits of hsync width,
  72. * bits 4-5 of vsync offset, and 2 high bits of vsync width.
  73. */
  74. u8 sync_off_width_high;
  75. u8 dtd_flags;
  76. u8 sdvo_flags;
  77. /** bits 6-7 of vsync offset at bits 6-7 */
  78. u8 v_sync_off_high;
  79. u8 reserved;
  80. } part2;
  81. } __packed;
  82. struct psb_intel_sdvo_pixel_clock_range {
  83. u16 min; /**< pixel clock, in 10kHz units */
  84. u16 max; /**< pixel clock, in 10kHz units */
  85. } __packed;
  86. struct psb_intel_sdvo_preferred_input_timing_args {
  87. u16 clock;
  88. u16 width;
  89. u16 height;
  90. } __packed;
  91. /* I2C registers for SDVO */
  92. #define SDVO_I2C_ARG_0 0x07
  93. #define SDVO_I2C_ARG_1 0x06
  94. #define SDVO_I2C_ARG_2 0x05
  95. #define SDVO_I2C_ARG_3 0x04
  96. #define SDVO_I2C_ARG_4 0x03
  97. #define SDVO_I2C_ARG_5 0x02
  98. #define SDVO_I2C_ARG_6 0x01
  99. #define SDVO_I2C_ARG_7 0x00
  100. #define SDVO_I2C_OPCODE 0x08
  101. #define SDVO_I2C_CMD_STATUS 0x09
  102. #define SDVO_I2C_RETURN_0 0x0a
  103. #define SDVO_I2C_RETURN_1 0x0b
  104. #define SDVO_I2C_RETURN_2 0x0c
  105. #define SDVO_I2C_RETURN_3 0x0d
  106. #define SDVO_I2C_RETURN_4 0x0e
  107. #define SDVO_I2C_RETURN_5 0x0f
  108. #define SDVO_I2C_RETURN_6 0x10
  109. #define SDVO_I2C_RETURN_7 0x11
  110. #define SDVO_I2C_VENDOR_BEGIN 0x20
  111. /* Status results */
  112. #define SDVO_CMD_STATUS_POWER_ON 0x0
  113. #define SDVO_CMD_STATUS_SUCCESS 0x1
  114. #define SDVO_CMD_STATUS_NOTSUPP 0x2
  115. #define SDVO_CMD_STATUS_INVALID_ARG 0x3
  116. #define SDVO_CMD_STATUS_PENDING 0x4
  117. #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5
  118. #define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6
  119. /* SDVO commands, argument/result registers */
  120. #define SDVO_CMD_RESET 0x01
  121. /** Returns a struct psb_intel_sdvo_caps */
  122. #define SDVO_CMD_GET_DEVICE_CAPS 0x02
  123. #define SDVO_CMD_GET_FIRMWARE_REV 0x86
  124. # define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0
  125. # define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1
  126. # define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2
  127. /**
  128. * Reports which inputs are trained (managed to sync).
  129. *
  130. * Devices must have trained within 2 vsyncs of a mode change.
  131. */
  132. #define SDVO_CMD_GET_TRAINED_INPUTS 0x03
  133. struct psb_intel_sdvo_get_trained_inputs_response {
  134. unsigned int input0_trained:1;
  135. unsigned int input1_trained:1;
  136. unsigned int pad:6;
  137. } __packed;
  138. /** Returns a struct psb_intel_sdvo_output_flags of active outputs. */
  139. #define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04
  140. /**
  141. * Sets the current set of active outputs.
  142. *
  143. * Takes a struct psb_intel_sdvo_output_flags.
  144. * Must be preceded by a SET_IN_OUT_MAP
  145. * on multi-output devices.
  146. */
  147. #define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05
  148. /**
  149. * Returns the current mapping of SDVO inputs to outputs on the device.
  150. *
  151. * Returns two struct psb_intel_sdvo_output_flags structures.
  152. */
  153. #define SDVO_CMD_GET_IN_OUT_MAP 0x06
  154. /**
  155. * Sets the current mapping of SDVO inputs to outputs on the device.
  156. *
  157. * Takes two struct i380_sdvo_output_flags structures.
  158. */
  159. #define SDVO_CMD_SET_IN_OUT_MAP 0x07
  160. /**
  161. * Returns a struct psb_intel_sdvo_output_flags of attached displays.
  162. */
  163. #define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b
  164. /**
  165. * Returns a struct psb_intel_sdvo_ouptut_flags of displays supporting hot plugging.
  166. */
  167. #define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c
  168. /**
  169. * Takes a struct psb_intel_sdvo_output_flags.
  170. */
  171. #define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d
  172. /**
  173. * Returns a struct psb_intel_sdvo_output_flags of displays with hot plug
  174. * interrupts enabled.
  175. */
  176. #define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e
  177. #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f
  178. struct psb_intel_sdvo_get_interrupt_event_source_response {
  179. u16 interrupt_status;
  180. unsigned int ambient_light_interrupt:1;
  181. unsigned int pad:7;
  182. } __packed;
  183. /**
  184. * Selects which input is affected by future input commands.
  185. *
  186. * Commands affected include SET_INPUT_TIMINGS_PART[12],
  187. * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12],
  188. * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS.
  189. */
  190. #define SDVO_CMD_SET_TARGET_INPUT 0x10
  191. struct psb_intel_sdvo_set_target_input_args {
  192. unsigned int target_1:1;
  193. unsigned int pad:7;
  194. } __packed;
  195. /**
  196. * Takes a struct psb_intel_sdvo_output_flags of which outputs are targeted by
  197. * future output commands.
  198. *
  199. * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
  200. * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE.
  201. */
  202. #define SDVO_CMD_SET_TARGET_OUTPUT 0x11
  203. #define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12
  204. #define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13
  205. #define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14
  206. #define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15
  207. #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16
  208. #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17
  209. #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18
  210. #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19
  211. /* Part 1 */
  212. # define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0
  213. # define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1
  214. # define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2
  215. # define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3
  216. # define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4
  217. # define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5
  218. # define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6
  219. # define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7
  220. /* Part 2 */
  221. # define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0
  222. # define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1
  223. # define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2
  224. # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3
  225. # define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4
  226. # define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7)
  227. # define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5)
  228. # define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3)
  229. # define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1)
  230. # define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5
  231. # define SDVO_DTD_SDVO_FLAG_STALL (1 << 7)
  232. # define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6)
  233. # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6)
  234. # define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4)
  235. # define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4)
  236. # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4)
  237. # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4)
  238. # define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6
  239. /**
  240. * Generates a DTD based on the given width, height, and flags.
  241. *
  242. * This will be supported by any device supporting scaling or interlaced
  243. * modes.
  244. */
  245. #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a
  246. # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0
  247. # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1
  248. # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2
  249. # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3
  250. # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4
  251. # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5
  252. # define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6
  253. # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0)
  254. # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1)
  255. #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b
  256. #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c
  257. /** Returns a struct psb_intel_sdvo_pixel_clock_range */
  258. #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d
  259. /** Returns a struct psb_intel_sdvo_pixel_clock_range */
  260. #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e
  261. /** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */
  262. #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f
  263. /** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
  264. #define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20
  265. /** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
  266. #define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21
  267. # define SDVO_CLOCK_RATE_MULT_1X (1 << 0)
  268. # define SDVO_CLOCK_RATE_MULT_2X (1 << 1)
  269. # define SDVO_CLOCK_RATE_MULT_4X (1 << 3)
  270. #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27
  271. #define SDVO_CMD_GET_TV_FORMAT 0x28
  272. #define SDVO_CMD_SET_TV_FORMAT 0x29
  273. #define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
  274. #define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
  275. #define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
  276. # define SDVO_ENCODER_STATE_ON (1 << 0)
  277. # define SDVO_ENCODER_STATE_STANDBY (1 << 1)
  278. # define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
  279. # define SDVO_ENCODER_STATE_OFF (1 << 3)
  280. #define SDVO_CMD_SET_TV_RESOLUTION_SUPPORT 0x93
  281. #define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a
  282. # define SDVO_CONTROL_BUS_PROM 0x0
  283. # define SDVO_CONTROL_BUS_DDC1 0x1
  284. # define SDVO_CONTROL_BUS_DDC2 0x2
  285. # define SDVO_CONTROL_BUS_DDC3 0x3
  286. /* SDVO Bus & SDVO Inputs wiring details*/
  287. /* Bit 0: Is SDVOB connected to In0 (1 = yes, 0 = no*/
  288. /* Bit 1: Is SDVOB connected to In1 (1 = yes, 0 = no*/
  289. /* Bit 2: Is SDVOC connected to In0 (1 = yes, 0 = no*/
  290. /* Bit 3: Is SDVOC connected to In1 (1 = yes, 0 = no*/
  291. #define SDVOB_IN0 0x01
  292. #define SDVOB_IN1 0x02
  293. #define SDVOC_IN0 0x04
  294. #define SDVOC_IN1 0x08
  295. #define SDVO_DEVICE_NONE 0x00
  296. #define SDVO_DEVICE_CRT 0x01
  297. #define SDVO_DEVICE_TV 0x02
  298. #define SDVO_DEVICE_LVDS 0x04
  299. #define SDVO_DEVICE_TMDS 0x08