/drivers/staging/gma500/mrst_hdmi_i2c.c

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t · C · 327 lines · 228 code · 57 blank · 42 comment · 16 complexity · 93aa94fe1f320eee4eeb60ded54f2ec7 MD5 · raw file

  1. /*
  2. * Copyright © 2010 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Li Peng <peng.li@intel.com>
  25. */
  26. #include <linux/mutex.h>
  27. #include <linux/pci.h>
  28. #include <linux/i2c.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/delay.h>
  31. #include "psb_drv.h"
  32. #define HDMI_READ(reg) readl(hdmi_dev->regs + (reg))
  33. #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
  34. #define HDMI_HCR 0x1000
  35. #define HCR_DETECT_HDP (1 << 6)
  36. #define HCR_ENABLE_HDCP (1 << 5)
  37. #define HCR_ENABLE_AUDIO (1 << 2)
  38. #define HCR_ENABLE_PIXEL (1 << 1)
  39. #define HCR_ENABLE_TMDS (1 << 0)
  40. #define HDMI_HICR 0x1004
  41. #define HDMI_INTR_I2C_ERROR (1 << 4)
  42. #define HDMI_INTR_I2C_FULL (1 << 3)
  43. #define HDMI_INTR_I2C_DONE (1 << 2)
  44. #define HDMI_INTR_HPD (1 << 0)
  45. #define HDMI_HSR 0x1008
  46. #define HDMI_HISR 0x100C
  47. #define HDMI_HI2CRDB0 0x1200
  48. #define HDMI_HI2CHCR 0x1240
  49. #define HI2C_HDCP_WRITE (0 << 2)
  50. #define HI2C_HDCP_RI_READ (1 << 2)
  51. #define HI2C_HDCP_READ (2 << 2)
  52. #define HI2C_EDID_READ (3 << 2)
  53. #define HI2C_READ_CONTINUE (1 << 1)
  54. #define HI2C_ENABLE_TRANSACTION (1 << 0)
  55. #define HDMI_ICRH 0x1100
  56. #define HDMI_HI2CTDR0 0x1244
  57. #define HDMI_HI2CTDR1 0x1248
  58. #define I2C_STAT_INIT 0
  59. #define I2C_READ_DONE 1
  60. #define I2C_TRANSACTION_DONE 2
  61. struct hdmi_i2c_dev {
  62. struct i2c_adapter *adap;
  63. struct mutex i2c_lock;
  64. struct completion complete;
  65. int status;
  66. struct i2c_msg *msg;
  67. int buf_offset;
  68. };
  69. static void hdmi_i2c_irq_enable(struct mrst_hdmi_dev *hdmi_dev)
  70. {
  71. u32 temp;
  72. temp = HDMI_READ(HDMI_HICR);
  73. temp |= (HDMI_INTR_I2C_ERROR | HDMI_INTR_I2C_FULL | HDMI_INTR_I2C_DONE);
  74. HDMI_WRITE(HDMI_HICR, temp);
  75. HDMI_READ(HDMI_HICR);
  76. }
  77. static void hdmi_i2c_irq_disable(struct mrst_hdmi_dev *hdmi_dev)
  78. {
  79. HDMI_WRITE(HDMI_HICR, 0x0);
  80. HDMI_READ(HDMI_HICR);
  81. }
  82. static int xfer_read(struct i2c_adapter *adap, struct i2c_msg *pmsg)
  83. {
  84. struct mrst_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap);
  85. struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
  86. u32 temp;
  87. i2c_dev->status = I2C_STAT_INIT;
  88. i2c_dev->msg = pmsg;
  89. i2c_dev->buf_offset = 0;
  90. INIT_COMPLETION(i2c_dev->complete);
  91. /* Enable I2C transaction */
  92. temp = ((pmsg->len) << 20) | HI2C_EDID_READ | HI2C_ENABLE_TRANSACTION;
  93. HDMI_WRITE(HDMI_HI2CHCR, temp);
  94. HDMI_READ(HDMI_HI2CHCR);
  95. while (i2c_dev->status != I2C_TRANSACTION_DONE)
  96. wait_for_completion_interruptible_timeout(&i2c_dev->complete,
  97. 10 * HZ);
  98. return 0;
  99. }
  100. static int xfer_write(struct i2c_adapter *adap, struct i2c_msg *pmsg)
  101. {
  102. /*
  103. * XXX: i2c write seems isn't useful for EDID probe, don't do anything
  104. */
  105. return 0;
  106. }
  107. static int mrst_hdmi_i2c_access(struct i2c_adapter *adap,
  108. struct i2c_msg *pmsg,
  109. int num)
  110. {
  111. struct mrst_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap);
  112. struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
  113. int i, err = 0;
  114. mutex_lock(&i2c_dev->i2c_lock);
  115. /* Enable i2c unit */
  116. HDMI_WRITE(HDMI_ICRH, 0x00008760);
  117. /* Enable irq */
  118. hdmi_i2c_irq_enable(hdmi_dev);
  119. for (i = 0; i < num; i++) {
  120. if (pmsg->len && pmsg->buf) {
  121. if (pmsg->flags & I2C_M_RD)
  122. err = xfer_read(adap, pmsg);
  123. else
  124. err = xfer_write(adap, pmsg);
  125. }
  126. pmsg++; /* next message */
  127. }
  128. /* Disable irq */
  129. hdmi_i2c_irq_disable(hdmi_dev);
  130. mutex_unlock(&i2c_dev->i2c_lock);
  131. return i;
  132. }
  133. static u32 mrst_hdmi_i2c_func(struct i2c_adapter *adapter)
  134. {
  135. return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
  136. }
  137. static const struct i2c_algorithm mrst_hdmi_i2c_algorithm = {
  138. .master_xfer = mrst_hdmi_i2c_access,
  139. .functionality = mrst_hdmi_i2c_func,
  140. };
  141. static struct i2c_adapter mrst_hdmi_i2c_adapter = {
  142. .name = "mrst_hdmi_i2c",
  143. .nr = 3,
  144. .owner = THIS_MODULE,
  145. .class = I2C_CLASS_DDC,
  146. .algo = &mrst_hdmi_i2c_algorithm,
  147. };
  148. static void hdmi_i2c_read(struct mrst_hdmi_dev *hdmi_dev)
  149. {
  150. struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
  151. struct i2c_msg *msg = i2c_dev->msg;
  152. u8 *buf = msg->buf;
  153. u32 temp;
  154. int i, offset;
  155. offset = i2c_dev->buf_offset;
  156. for (i = 0; i < 0x10; i++) {
  157. temp = HDMI_READ(HDMI_HI2CRDB0 + (i * 4));
  158. memcpy(buf + (offset + i * 4), &temp, 4);
  159. }
  160. i2c_dev->buf_offset += (0x10 * 4);
  161. /* clearing read buffer full intr */
  162. temp = HDMI_READ(HDMI_HISR);
  163. HDMI_WRITE(HDMI_HISR, temp | HDMI_INTR_I2C_FULL);
  164. HDMI_READ(HDMI_HISR);
  165. /* continue read transaction */
  166. temp = HDMI_READ(HDMI_HI2CHCR);
  167. HDMI_WRITE(HDMI_HI2CHCR, temp | HI2C_READ_CONTINUE);
  168. HDMI_READ(HDMI_HI2CHCR);
  169. i2c_dev->status = I2C_READ_DONE;
  170. return;
  171. }
  172. static void hdmi_i2c_transaction_done(struct mrst_hdmi_dev *hdmi_dev)
  173. {
  174. struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
  175. u32 temp;
  176. /* clear transaction done intr */
  177. temp = HDMI_READ(HDMI_HISR);
  178. HDMI_WRITE(HDMI_HISR, temp | HDMI_INTR_I2C_DONE);
  179. HDMI_READ(HDMI_HISR);
  180. temp = HDMI_READ(HDMI_HI2CHCR);
  181. HDMI_WRITE(HDMI_HI2CHCR, temp & ~HI2C_ENABLE_TRANSACTION);
  182. HDMI_READ(HDMI_HI2CHCR);
  183. i2c_dev->status = I2C_TRANSACTION_DONE;
  184. return;
  185. }
  186. static irqreturn_t mrst_hdmi_i2c_handler(int this_irq, void *dev)
  187. {
  188. struct mrst_hdmi_dev *hdmi_dev = dev;
  189. struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
  190. u32 stat;
  191. stat = HDMI_READ(HDMI_HISR);
  192. if (stat & HDMI_INTR_HPD) {
  193. HDMI_WRITE(HDMI_HISR, stat | HDMI_INTR_HPD);
  194. HDMI_READ(HDMI_HISR);
  195. }
  196. if (stat & HDMI_INTR_I2C_FULL)
  197. hdmi_i2c_read(hdmi_dev);
  198. if (stat & HDMI_INTR_I2C_DONE)
  199. hdmi_i2c_transaction_done(hdmi_dev);
  200. complete(&i2c_dev->complete);
  201. return IRQ_HANDLED;
  202. }
  203. /*
  204. * choose alternate function 2 of GPIO pin 52, 53,
  205. * which is used by HDMI I2C logic
  206. */
  207. static void mrst_hdmi_i2c_gpio_fix(void)
  208. {
  209. void *base;
  210. unsigned int gpio_base = 0xff12c000;
  211. int gpio_len = 0x1000;
  212. u32 temp;
  213. base = ioremap((resource_size_t)gpio_base, gpio_len);
  214. if (base == NULL) {
  215. DRM_ERROR("gpio ioremap fail\n");
  216. return;
  217. }
  218. temp = readl(base + 0x44);
  219. DRM_DEBUG_DRIVER("old gpio val %x\n", temp);
  220. writel((temp | 0x00000a00), (base + 0x44));
  221. temp = readl(base + 0x44);
  222. DRM_DEBUG_DRIVER("new gpio val %x\n", temp);
  223. iounmap(base);
  224. }
  225. int mrst_hdmi_i2c_init(struct pci_dev *dev)
  226. {
  227. struct mrst_hdmi_dev *hdmi_dev;
  228. struct hdmi_i2c_dev *i2c_dev;
  229. int ret;
  230. hdmi_dev = pci_get_drvdata(dev);
  231. i2c_dev = kzalloc(sizeof(struct hdmi_i2c_dev), GFP_KERNEL);
  232. if (i2c_dev == NULL) {
  233. DRM_ERROR("Can't allocate interface\n");
  234. ret = -ENOMEM;
  235. goto exit;
  236. }
  237. i2c_dev->adap = &mrst_hdmi_i2c_adapter;
  238. i2c_dev->status = I2C_STAT_INIT;
  239. init_completion(&i2c_dev->complete);
  240. mutex_init(&i2c_dev->i2c_lock);
  241. i2c_set_adapdata(&mrst_hdmi_i2c_adapter, hdmi_dev);
  242. hdmi_dev->i2c_dev = i2c_dev;
  243. /* Enable HDMI I2C function on gpio */
  244. mrst_hdmi_i2c_gpio_fix();
  245. /* request irq */
  246. ret = request_irq(dev->irq, mrst_hdmi_i2c_handler, IRQF_SHARED,
  247. mrst_hdmi_i2c_adapter.name, hdmi_dev);
  248. if (ret) {
  249. DRM_ERROR("Failed to request IRQ for I2C controller\n");
  250. goto err;
  251. }
  252. /* Adapter registration */
  253. ret = i2c_add_numbered_adapter(&mrst_hdmi_i2c_adapter);
  254. return ret;
  255. err:
  256. kfree(i2c_dev);
  257. exit:
  258. return ret;
  259. }
  260. void mrst_hdmi_i2c_exit(struct pci_dev *dev)
  261. {
  262. struct mrst_hdmi_dev *hdmi_dev;
  263. struct hdmi_i2c_dev *i2c_dev;
  264. hdmi_dev = pci_get_drvdata(dev);
  265. if (i2c_del_adapter(&mrst_hdmi_i2c_adapter))
  266. DRM_DEBUG_DRIVER("Failed to delete hdmi-i2c adapter\n");
  267. i2c_dev = hdmi_dev->i2c_dev;
  268. kfree(i2c_dev);
  269. free_irq(dev->irq, hdmi_dev);
  270. }