/drivers/staging/gma500/mid_bios.c

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t · C · 269 lines · 199 code · 31 blank · 39 comment · 18 complexity · a716e8153caff23fb57a00fc740ab0e6 MD5 · raw file

  1. /**************************************************************************
  2. * Copyright (c) 2011, Intel Corporation.
  3. * All Rights Reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. **************************************************************************/
  19. /* TODO
  20. * - Split functions by vbt type
  21. * - Make them all take drm_device
  22. * - Check ioremap failures
  23. */
  24. #include <drm/drmP.h>
  25. #include <drm/drm.h>
  26. #include "psb_drm.h"
  27. #include "psb_drv.h"
  28. #include "mid_bios.h"
  29. #include "mdfld_output.h"
  30. static int panel_id = GCT_DETECT;
  31. module_param_named(panel_id, panel_id, int, 0600);
  32. MODULE_PARM_DESC(panel_id, "Panel Identifier");
  33. static void mid_get_fuse_settings(struct drm_device *dev)
  34. {
  35. struct drm_psb_private *dev_priv = dev->dev_private;
  36. struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
  37. uint32_t fuse_value = 0;
  38. uint32_t fuse_value_tmp = 0;
  39. #define FB_REG06 0xD0810600
  40. #define FB_MIPI_DISABLE (1 << 11)
  41. #define FB_REG09 0xD0810900
  42. #define FB_REG09 0xD0810900
  43. #define FB_SKU_MASK 0x7000
  44. #define FB_SKU_SHIFT 12
  45. #define FB_SKU_100 0
  46. #define FB_SKU_100L 1
  47. #define FB_SKU_83 2
  48. pci_write_config_dword(pci_root, 0xD0, FB_REG06);
  49. pci_read_config_dword(pci_root, 0xD4, &fuse_value);
  50. /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
  51. if (IS_MRST(dev))
  52. dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
  53. DRM_INFO("internal display is %s\n",
  54. dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
  55. /* Prevent runtime suspend at start*/
  56. if (dev_priv->iLVDS_enable) {
  57. dev_priv->is_lvds_on = true;
  58. dev_priv->is_mipi_on = false;
  59. } else {
  60. dev_priv->is_mipi_on = true;
  61. dev_priv->is_lvds_on = false;
  62. }
  63. dev_priv->video_device_fuse = fuse_value;
  64. pci_write_config_dword(pci_root, 0xD0, FB_REG09);
  65. pci_read_config_dword(pci_root, 0xD4, &fuse_value);
  66. dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
  67. fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
  68. dev_priv->fuse_reg_value = fuse_value;
  69. switch (fuse_value_tmp) {
  70. case FB_SKU_100:
  71. dev_priv->core_freq = 200;
  72. break;
  73. case FB_SKU_100L:
  74. dev_priv->core_freq = 100;
  75. break;
  76. case FB_SKU_83:
  77. dev_priv->core_freq = 166;
  78. break;
  79. default:
  80. dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
  81. fuse_value_tmp);
  82. dev_priv->core_freq = 0;
  83. }
  84. dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
  85. pci_dev_put(pci_root);
  86. }
  87. /*
  88. * Get the revison ID, B0:D2:F0;0x08
  89. */
  90. static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
  91. {
  92. uint32_t platform_rev_id = 0;
  93. struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
  94. pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
  95. dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
  96. pci_dev_put(pci_gfx_root);
  97. dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n",
  98. dev_priv->platform_rev_id);
  99. }
  100. static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
  101. {
  102. struct drm_device *dev = dev_priv->dev;
  103. struct mrst_vbt *vbt = &dev_priv->vbt_data;
  104. u32 addr;
  105. u16 new_size;
  106. u8 *vbt_virtual;
  107. u8 bpi;
  108. u8 number_desc = 0;
  109. struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
  110. struct gct_r10_timing_info ti;
  111. void *pGCT;
  112. struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
  113. /* Get the address of the platform config vbt, B0:D2:F0;0xFC */
  114. pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
  115. pci_dev_put(pci_gfx_root);
  116. dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
  117. /* check for platform config address == 0. */
  118. /* this means fw doesn't support vbt */
  119. if (addr == 0) {
  120. vbt->size = 0;
  121. return;
  122. }
  123. /* get the virtual address of the vbt */
  124. vbt_virtual = ioremap(addr, sizeof(*vbt));
  125. memcpy(vbt, vbt_virtual, sizeof(*vbt));
  126. iounmap(vbt_virtual); /* Free virtual address space */
  127. dev_dbg(dev->dev, "GCT revision is %x\n", vbt->revision);
  128. switch (vbt->revision) {
  129. case 0:
  130. vbt->mrst_gct = ioremap(addr + sizeof(*vbt) - 4,
  131. vbt->size - sizeof(*vbt) + 4);
  132. pGCT = vbt->mrst_gct;
  133. bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
  134. dev_priv->gct_data.bpi = bpi;
  135. dev_priv->gct_data.pt =
  136. ((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
  137. memcpy(&dev_priv->gct_data.DTD,
  138. &((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
  139. sizeof(struct mrst_timing_info));
  140. dev_priv->gct_data.Panel_Port_Control =
  141. ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
  142. dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
  143. ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
  144. break;
  145. case 1:
  146. vbt->mrst_gct = ioremap(addr + sizeof(*vbt) - 4,
  147. vbt->size - sizeof(*vbt) + 4);
  148. pGCT = vbt->mrst_gct;
  149. bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
  150. dev_priv->gct_data.bpi = bpi;
  151. dev_priv->gct_data.pt =
  152. ((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
  153. memcpy(&dev_priv->gct_data.DTD,
  154. &((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
  155. sizeof(struct mrst_timing_info));
  156. dev_priv->gct_data.Panel_Port_Control =
  157. ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
  158. dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
  159. ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
  160. break;
  161. case 0x10:
  162. /*header definition changed from rev 01 (v2) to rev 10h. */
  163. /*so, some values have changed location*/
  164. new_size = vbt->checksum; /*checksum contains lo size byte*/
  165. /*LSB of mrst_gct contains hi size byte*/
  166. new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
  167. vbt->checksum = vbt->size; /*size contains the checksum*/
  168. if (new_size > 0xff)
  169. vbt->size = 0xff; /*restrict size to 255*/
  170. else
  171. vbt->size = new_size;
  172. /* number of descriptors defined in the GCT */
  173. number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
  174. bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
  175. vbt->mrst_gct = ioremap(addr + GCT_R10_HEADER_SIZE,
  176. GCT_R10_DISPLAY_DESC_SIZE * number_desc);
  177. pGCT = vbt->mrst_gct;
  178. pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
  179. dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
  180. /*copy the GCT display timings into a temp structure*/
  181. memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
  182. /*now copy the temp struct into the dev_priv->gct_data*/
  183. dp_ti->pixel_clock = ti.pixel_clock;
  184. dp_ti->hactive_hi = ti.hactive_hi;
  185. dp_ti->hactive_lo = ti.hactive_lo;
  186. dp_ti->hblank_hi = ti.hblank_hi;
  187. dp_ti->hblank_lo = ti.hblank_lo;
  188. dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
  189. dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
  190. dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
  191. dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
  192. dp_ti->vactive_hi = ti.vactive_hi;
  193. dp_ti->vactive_lo = ti.vactive_lo;
  194. dp_ti->vblank_hi = ti.vblank_hi;
  195. dp_ti->vblank_lo = ti.vblank_lo;
  196. dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
  197. dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
  198. dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
  199. dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
  200. /* Move the MIPI_Display_Descriptor data from GCT to dev priv */
  201. dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
  202. *((u8 *)pGCT + 0x0d);
  203. dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
  204. (*((u8 *)pGCT + 0x0e)) << 8;
  205. break;
  206. default:
  207. dev_err(dev->dev, "Unknown revision of GCT!\n");
  208. vbt->size = 0;
  209. }
  210. if (IS_MFLD(dev_priv->dev)) {
  211. if (panel_id == GCT_DETECT) {
  212. if (dev_priv->gct_data.bpi == 2) {
  213. dev_info(dev->dev, "[GFX] PYR Panel Detected\n");
  214. dev_priv->panel_id = PYR_CMD;
  215. panel_id = PYR_CMD;
  216. } else if (dev_priv->gct_data.bpi == 0) {
  217. dev_info(dev->dev, "[GFX] TMD Panel Detected.\n");
  218. dev_priv->panel_id = TMD_VID;
  219. panel_id = TMD_VID;
  220. } else {
  221. dev_info(dev->dev, "[GFX] Default Panel (TPO)\n");
  222. dev_priv->panel_id = TPO_CMD;
  223. panel_id = TPO_CMD;
  224. }
  225. } else {
  226. dev_info(dev->dev, "[GFX] Panel Parameter Passed in through cmd line\n");
  227. dev_priv->panel_id = panel_id;
  228. }
  229. }
  230. }
  231. int mid_chip_setup(struct drm_device *dev)
  232. {
  233. struct drm_psb_private *dev_priv = dev->dev_private;
  234. mid_get_fuse_settings(dev);
  235. mid_get_vbt_data(dev_priv);
  236. mid_get_pci_revID(dev_priv);
  237. return 0;
  238. }