/drivers/staging/comedi/drivers/plx9080.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t · C Header · 429 lines · 273 code · 62 blank · 94 comment · 12 complexity · cf51f68bbb72bbc67d2c905c832b1cbc MD5 · raw file

  1. /* plx9080.h
  2. *
  3. * Copyright (C) 2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net>
  4. *
  5. * I modified this file from the plx9060.h header for the
  6. * wanXL device driver in the linux kernel,
  7. * for the register offsets and bit definitions. Made minor modifications,
  8. * added plx9080 registers and
  9. * stripped out stuff that was specifically for the wanXL driver.
  10. * Note: I've only made sure the definitions are correct as far
  11. * as I make use of them. There are still various plx9060-isms
  12. * left in this header file.
  13. *
  14. ********************************************************************
  15. *
  16. * Copyright (C) 1999 RG Studio s.c.
  17. * Written by Krzysztof Halasa <khc@rgstudio.com.pl>
  18. *
  19. * Portions (C) SBE Inc., used by permission.
  20. *
  21. * This program is free software; you can redistribute it and/or
  22. * modify it under the terms of the GNU General Public License
  23. * as published by the Free Software Foundation; either version
  24. * 2 of the License, or (at your option) any later version.
  25. */
  26. #ifndef __COMEDI_PLX9080_H
  27. #define __COMEDI_PLX9080_H
  28. /* descriptor block used for chained dma transfers */
  29. struct plx_dma_desc {
  30. volatile uint32_t pci_start_addr;
  31. volatile uint32_t local_start_addr;
  32. /* transfer_size is in bytes, only first 23 bits of register are used */
  33. volatile uint32_t transfer_size;
  34. /* address of next descriptor (quad word aligned), plus some
  35. * additional bits (see PLX_DMA0_DESCRIPTOR_REG) */
  36. volatile uint32_t next;
  37. };
  38. /**********************************************************************
  39. ** Register Offsets and Bit Definitions
  40. **
  41. ** Note: All offsets zero relative. IE. Some standard base address
  42. ** must be added to the Register Number to properly access the register.
  43. **
  44. **********************************************************************/
  45. #define PLX_LAS0RNG_REG 0x0000 /* L, Local Addr Space 0 Range Register */
  46. #define PLX_LAS1RNG_REG 0x00f0 /* L, Local Addr Space 1 Range Register */
  47. #define LRNG_IO 0x00000001 /* Map to: 1=I/O, 0=Mem */
  48. #define LRNG_ANY32 0x00000000 /* Locate anywhere in 32 bit */
  49. #define LRNG_LT1MB 0x00000002 /* Locate in 1st meg */
  50. #define LRNG_ANY64 0x00000004 /* Locate anywhere in 64 bit */
  51. #define LRNG_MEM_MASK 0xfffffff0 /* bits that specify range for memory io */
  52. #define LRNG_IO_MASK 0xfffffffa /* bits that specify range for normal io */
  53. #define PLX_LAS0MAP_REG 0x0004 /* L, Local Addr Space 0 Remap Register */
  54. #define PLX_LAS1MAP_REG 0x00f4 /* L, Local Addr Space 1 Remap Register */
  55. #define LMAP_EN 0x00000001 /* Enable slave decode */
  56. #define LMAP_MEM_MASK 0xfffffff0 /* bits that specify decode for memory io */
  57. #define LMAP_IO_MASK 0xfffffffa /* bits that specify decode bits for normal io */
  58. /* Mode/Arbitration Register.
  59. */
  60. #define PLX_MARB_REG 0x8 /* L, Local Arbitration Register */
  61. #define PLX_DMAARB_REG 0xac
  62. enum marb_bits {
  63. MARB_LLT_MASK = 0x000000ff, /* Local Bus Latency Timer */
  64. MARB_LPT_MASK = 0x0000ff00, /* Local Bus Pause Timer */
  65. MARB_LTEN = 0x00010000, /* Latency Timer Enable */
  66. MARB_LPEN = 0x00020000, /* Pause Timer Enable */
  67. MARB_BREQ = 0x00040000, /* Local Bus BREQ Enable */
  68. MARB_DMA_PRIORITY_MASK = 0x00180000,
  69. MARB_LBDS_GIVE_UP_BUS_MODE = 0x00200000, /* local bus direct slave give up bus mode */
  70. MARB_DS_LLOCK_ENABLE = 0x00400000, /* direct slave LLOCKo# enable */
  71. MARB_PCI_REQUEST_MODE = 0x00800000,
  72. MARB_PCIv21_MODE = 0x01000000, /* pci specification v2.1 mode */
  73. MARB_PCI_READ_NO_WRITE_MODE = 0x02000000,
  74. MARB_PCI_READ_WITH_WRITE_FLUSH_MODE = 0x04000000,
  75. MARB_GATE_TIMER_WITH_BREQ = 0x08000000, /* gate local bus latency timer with BREQ */
  76. MARB_PCI_READ_NO_FLUSH_MODE = 0x10000000,
  77. MARB_USE_SUBSYSTEM_IDS = 0x20000000,
  78. };
  79. #define PLX_BIGEND_REG 0xc
  80. enum bigend_bits {
  81. BIGEND_CONFIG = 0x1, /* use big endian ordering for configuration register accesses */
  82. BIGEND_DIRECT_MASTER = 0x2,
  83. BIGEND_DIRECT_SLAVE_LOCAL0 = 0x4,
  84. BIGEND_ROM = 0x8,
  85. BIGEND_BYTE_LANE = 0x10, /* use byte lane consisting of most significant bits instead of least significant */
  86. BIGEND_DIRECT_SLAVE_LOCAL1 = 0x20,
  87. BIGEND_DMA1 = 0x40,
  88. BIGEND_DMA0 = 0x80,
  89. };
  90. /* Note: The Expansion ROM stuff is only relevant to the PC environment.
  91. ** This expansion ROM code is executed by the host CPU at boot time.
  92. ** For this reason no bit definitions are provided here.
  93. */
  94. #define PLX_ROMRNG_REG 0x0010 /* L, Expn ROM Space Range Register */
  95. #define PLX_ROMMAP_REG 0x0014 /* L, Local Addr Space Range Register */
  96. #define PLX_REGION0_REG 0x0018 /* L, Local Bus Region 0 Descriptor */
  97. #define RGN_WIDTH 0x00000002 /* Local bus width bits */
  98. #define RGN_8BITS 0x00000000 /* 08 bit Local Bus */
  99. #define RGN_16BITS 0x00000001 /* 16 bit Local Bus */
  100. #define RGN_32BITS 0x00000002 /* 32 bit Local Bus */
  101. #define RGN_MWS 0x0000003C /* Memory Access Wait States */
  102. #define RGN_0MWS 0x00000000
  103. #define RGN_1MWS 0x00000004
  104. #define RGN_2MWS 0x00000008
  105. #define RGN_3MWS 0x0000000C
  106. #define RGN_4MWS 0x00000010
  107. #define RGN_6MWS 0x00000018
  108. #define RGN_8MWS 0x00000020
  109. #define RGN_MRE 0x00000040 /* Memory Space Ready Input Enable */
  110. #define RGN_MBE 0x00000080 /* Memory Space Bterm Input Enable */
  111. #define RGN_READ_PREFETCH_DISABLE 0x00000100
  112. #define RGN_ROM_PREFETCH_DISABLE 0x00000200
  113. #define RGN_READ_PREFETCH_COUNT_ENABLE 0x00000400
  114. #define RGN_RWS 0x003C0000 /* Expn ROM Wait States */
  115. #define RGN_RRE 0x00400000 /* ROM Space Ready Input Enable */
  116. #define RGN_RBE 0x00800000 /* ROM Space Bterm Input Enable */
  117. #define RGN_MBEN 0x01000000 /* Memory Space Burst Enable */
  118. #define RGN_RBEN 0x04000000 /* ROM Space Burst Enable */
  119. #define RGN_THROT 0x08000000 /* De-assert TRDY when FIFO full */
  120. #define RGN_TRD 0xF0000000 /* Target Ready Delay /8 */
  121. #define PLX_REGION1_REG 0x00f8 /* L, Local Bus Region 1 Descriptor */
  122. #define PLX_DMRNG_REG 0x001C /* L, Direct Master Range Register */
  123. #define PLX_LBAPMEM_REG 0x0020 /* L, Lcl Base Addr for PCI mem space */
  124. #define PLX_LBAPIO_REG 0x0024 /* L, Lcl Base Addr for PCI I/O space */
  125. #define PLX_DMMAP_REG 0x0028 /* L, Direct Master Remap Register */
  126. #define DMM_MAE 0x00000001 /* Direct Mstr Memory Acc Enable */
  127. #define DMM_IAE 0x00000002 /* Direct Mstr I/O Acc Enable */
  128. #define DMM_LCK 0x00000004 /* LOCK Input Enable */
  129. #define DMM_PF4 0x00000008 /* Prefetch 4 Mode Enable */
  130. #define DMM_THROT 0x00000010 /* Assert IRDY when read FIFO full */
  131. #define DMM_PAF0 0x00000000 /* Programmable Almost fill level */
  132. #define DMM_PAF1 0x00000020 /* Programmable Almost fill level */
  133. #define DMM_PAF2 0x00000040 /* Programmable Almost fill level */
  134. #define DMM_PAF3 0x00000060 /* Programmable Almost fill level */
  135. #define DMM_PAF4 0x00000080 /* Programmable Almost fill level */
  136. #define DMM_PAF5 0x000000A0 /* Programmable Almost fill level */
  137. #define DMM_PAF6 0x000000C0 /* Programmable Almost fill level */
  138. #define DMM_PAF7 0x000000D0 /* Programmable Almost fill level */
  139. #define DMM_MAP 0xFFFF0000 /* Remap Address Bits */
  140. #define PLX_CAR_REG 0x002C /* L, Configuration Address Register */
  141. #define CAR_CT0 0x00000000 /* Config Type 0 */
  142. #define CAR_CT1 0x00000001 /* Config Type 1 */
  143. #define CAR_REG 0x000000FC /* Register Number Bits */
  144. #define CAR_FUN 0x00000700 /* Function Number Bits */
  145. #define CAR_DEV 0x0000F800 /* Device Number Bits */
  146. #define CAR_BUS 0x00FF0000 /* Bus Number Bits */
  147. #define CAR_CFG 0x80000000 /* Config Spc Access Enable */
  148. #define PLX_DBR_IN_REG 0x0060 /* L, PCI to Local Doorbell Register */
  149. #define PLX_DBR_OUT_REG 0x0064 /* L, Local to PCI Doorbell Register */
  150. #define PLX_INTRCS_REG 0x0068 /* L, Interrupt Control/Status Reg */
  151. #define ICS_AERR 0x00000001 /* Assert LSERR on ABORT */
  152. #define ICS_PERR 0x00000002 /* Assert LSERR on Parity Error */
  153. #define ICS_SERR 0x00000004 /* Generate PCI SERR# */
  154. #define ICS_MBIE 0x00000008 /* mailbox interrupt enable */
  155. #define ICS_PIE 0x00000100 /* PCI Interrupt Enable */
  156. #define ICS_PDIE 0x00000200 /* PCI Doorbell Interrupt Enable */
  157. #define ICS_PAIE 0x00000400 /* PCI Abort Interrupt Enable */
  158. #define ICS_PLIE 0x00000800 /* PCI Local Int Enable */
  159. #define ICS_RAE 0x00001000 /* Retry Abort Enable */
  160. #define ICS_PDIA 0x00002000 /* PCI Doorbell Interrupt Active */
  161. #define ICS_PAIA 0x00004000 /* PCI Abort Interrupt Active */
  162. #define ICS_LIA 0x00008000 /* Local Interrupt Active */
  163. #define ICS_LIE 0x00010000 /* Local Interrupt Enable */
  164. #define ICS_LDIE 0x00020000 /* Local Doorbell Int Enable */
  165. #define ICS_DMA0_E 0x00040000 /* DMA #0 Interrupt Enable */
  166. #define ICS_DMA1_E 0x00080000 /* DMA #1 Interrupt Enable */
  167. #define ICS_LDIA 0x00100000 /* Local Doorbell Int Active */
  168. #define ICS_DMA0_A 0x00200000 /* DMA #0 Interrupt Active */
  169. #define ICS_DMA1_A 0x00400000 /* DMA #1 Interrupt Active */
  170. #define ICS_BIA 0x00800000 /* BIST Interrupt Active */
  171. #define ICS_TA_DM 0x01000000 /* Target Abort - Direct Master */
  172. #define ICS_TA_DMA0 0x02000000 /* Target Abort - DMA #0 */
  173. #define ICS_TA_DMA1 0x04000000 /* Target Abort - DMA #1 */
  174. #define ICS_TA_RA 0x08000000 /* Target Abort - Retry Timeout */
  175. #define ICS_MBIA(x) (0x10000000 << ((x) & 0x3)) /* mailbox x is active */
  176. #define PLX_CONTROL_REG 0x006C /* L, EEPROM Cntl & PCI Cmd Codes */
  177. #define CTL_RDMA 0x0000000E /* DMA Read Command */
  178. #define CTL_WDMA 0x00000070 /* DMA Write Command */
  179. #define CTL_RMEM 0x00000600 /* Memory Read Command */
  180. #define CTL_WMEM 0x00007000 /* Memory Write Command */
  181. #define CTL_USERO 0x00010000 /* USERO output pin control bit */
  182. #define CTL_USERI 0x00020000 /* USERI input pin bit */
  183. #define CTL_EE_CLK 0x01000000 /* EEPROM Clock line */
  184. #define CTL_EE_CS 0x02000000 /* EEPROM Chip Select */
  185. #define CTL_EE_W 0x04000000 /* EEPROM Write bit */
  186. #define CTL_EE_R 0x08000000 /* EEPROM Read bit */
  187. #define CTL_EECHK 0x10000000 /* EEPROM Present bit */
  188. #define CTL_EERLD 0x20000000 /* EEPROM Reload Register */
  189. #define CTL_RESET 0x40000000 /* !! Adapter Reset !! */
  190. #define CTL_READY 0x80000000 /* Local Init Done */
  191. #define PLX_ID_REG 0x70 /* hard-coded plx vendor and device ids */
  192. #define PLX_REVISION_REG 0x74 /* silicon revision */
  193. #define PLX_DMA0_MODE_REG 0x80 /* dma channel 0 mode register */
  194. #define PLX_DMA1_MODE_REG 0x94 /* dma channel 0 mode register */
  195. #define PLX_LOCAL_BUS_16_WIDE_BITS 0x1
  196. #define PLX_LOCAL_BUS_32_WIDE_BITS 0x3
  197. #define PLX_LOCAL_BUS_WIDTH_MASK 0x3
  198. #define PLX_DMA_EN_READYIN_BIT 0x40 /* enable ready in input */
  199. #define PLX_EN_BTERM_BIT 0x80 /* enable BTERM# input */
  200. #define PLX_DMA_LOCAL_BURST_EN_BIT 0x100 /* enable local burst mode */
  201. #define PLX_EN_CHAIN_BIT 0x200 /* enables chaining */
  202. #define PLX_EN_DMA_DONE_INTR_BIT 0x400 /* enables interrupt on dma done */
  203. #define PLX_LOCAL_ADDR_CONST_BIT 0x800 /* hold local address constant (don't increment) */
  204. #define PLX_DEMAND_MODE_BIT 0x1000 /* enables demand-mode for dma transfer */
  205. #define PLX_EOT_ENABLE_BIT 0x4000
  206. #define PLX_STOP_MODE_BIT 0x8000
  207. #define PLX_DMA_INTR_PCI_BIT 0x20000 /* routes dma interrupt to pci bus (instead of local bus) */
  208. #define PLX_DMA0_PCI_ADDRESS_REG 0x84 /* pci address that dma transfers start at */
  209. #define PLX_DMA1_PCI_ADDRESS_REG 0x98
  210. #define PLX_DMA0_LOCAL_ADDRESS_REG 0x88 /* local address that dma transfers start at */
  211. #define PLX_DMA1_LOCAL_ADDRESS_REG 0x9c
  212. #define PLX_DMA0_TRANSFER_SIZE_REG 0x8c /* number of bytes to transfer (first 23 bits) */
  213. #define PLX_DMA1_TRANSFER_SIZE_REG 0xa0
  214. #define PLX_DMA0_DESCRIPTOR_REG 0x90 /* descriptor pointer register */
  215. #define PLX_DMA1_DESCRIPTOR_REG 0xa4
  216. #define PLX_DESC_IN_PCI_BIT 0x1 /* descriptor is located in pci space (not local space) */
  217. #define PLX_END_OF_CHAIN_BIT 0x2 /* end of chain bit */
  218. #define PLX_INTR_TERM_COUNT 0x4 /* interrupt when this descriptor's transfer is finished */
  219. #define PLX_XFER_LOCAL_TO_PCI 0x8 /* transfer from local to pci bus (not pci to local) */
  220. #define PLX_DMA0_CS_REG 0xa8 /* command status register */
  221. #define PLX_DMA1_CS_REG 0xa9
  222. #define PLX_DMA_EN_BIT 0x1 /* enable dma channel */
  223. #define PLX_DMA_START_BIT 0x2 /* start dma transfer */
  224. #define PLX_DMA_ABORT_BIT 0x4 /* abort dma transfer */
  225. #define PLX_CLEAR_DMA_INTR_BIT 0x8 /* clear dma interrupt */
  226. #define PLX_DMA_DONE_BIT 0x10 /* transfer done status bit */
  227. #define PLX_DMA0_THRESHOLD_REG 0xb0 /* command status register */
  228. /*
  229. * Accesses near the end of memory can cause the PLX chip
  230. * to pre-fetch data off of end-of-ram. Limit the size of
  231. * memory so host-side accesses cannot occur.
  232. */
  233. #define PLX_PREFETCH 32
  234. /*
  235. * The PCI Interface, via the PCI-9060 Chip, has up to eight (8) Mailbox
  236. * Registers. The PUTS (Power-Up Test Suite) handles the board-side
  237. * interface/interaction using the first 4 registers. Specifications for
  238. * the use of the full PUTS' command and status interface is contained
  239. * within a separate SBE PUTS Manual. The Host-Side Device Driver only
  240. * uses a subset of the full PUTS interface.
  241. */
  242. /*****************************************/
  243. /*** MAILBOX #(-1) - MEM ACCESS STS ***/
  244. /*****************************************/
  245. #define MBX_STS_VALID 0x57584744 /* 'WXGD' */
  246. #define MBX_STS_DILAV 0x44475857 /* swapped = 'DGXW' */
  247. /*****************************************/
  248. /*** MAILBOX #0 - PUTS STATUS ***/
  249. /*****************************************/
  250. #define MBX_STS_MASK 0x000000ff /* PUTS Status Register bits */
  251. #define MBX_STS_TMASK 0x0000000f /* register bits for TEST number */
  252. #define MBX_STS_PCIRESET 0x00000100 /* Host issued PCI reset request */
  253. #define MBX_STS_BUSY 0x00000080 /* PUTS is in progress */
  254. #define MBX_STS_ERROR 0x00000040 /* PUTS has failed */
  255. #define MBX_STS_RESERVED 0x000000c0 /* Undefined -> status in transition.
  256. We are in process of changing
  257. bits; we SET Error bit before
  258. RESET of Busy bit */
  259. #define MBX_RESERVED_5 0x00000020 /* FYI: reserved/unused bit */
  260. #define MBX_RESERVED_4 0x00000010 /* FYI: reserved/unused bit */
  261. /******************************************/
  262. /*** MAILBOX #1 - PUTS COMMANDS ***/
  263. /******************************************/
  264. /*
  265. * Any attempt to execute an unimplement command results in the PUTS
  266. * interface executing a NOOP and continuing as if the offending command
  267. * completed normally. Note: this supplies a simple method to interrogate
  268. * mailbox command processing functionality.
  269. */
  270. #define MBX_CMD_MASK 0xffff0000 /* PUTS Command Register bits */
  271. #define MBX_CMD_ABORTJ 0x85000000 /* abort and jump */
  272. #define MBX_CMD_RESETP 0x86000000 /* reset and pause at start */
  273. #define MBX_CMD_PAUSE 0x87000000 /* pause immediately */
  274. #define MBX_CMD_PAUSEC 0x88000000 /* pause on completion */
  275. #define MBX_CMD_RESUME 0x89000000 /* resume operation */
  276. #define MBX_CMD_STEP 0x8a000000 /* single step tests */
  277. #define MBX_CMD_BSWAP 0x8c000000 /* identify byte swap scheme */
  278. #define MBX_CMD_BSWAP_0 0x8c000000 /* use scheme 0 */
  279. #define MBX_CMD_BSWAP_1 0x8c000001 /* use scheme 1 */
  280. #define MBX_CMD_SETHMS 0x8d000000 /* setup host memory access window
  281. size */
  282. #define MBX_CMD_SETHBA 0x8e000000 /* setup host memory access base
  283. address */
  284. #define MBX_CMD_MGO 0x8f000000 /* perform memory setup and continue
  285. (IE. Done) */
  286. #define MBX_CMD_NOOP 0xFF000000 /* dummy, illegal command */
  287. /*****************************************/
  288. /*** MAILBOX #2 - MEMORY SIZE ***/
  289. /*****************************************/
  290. #define MBX_MEMSZ_MASK 0xffff0000 /* PUTS Memory Size Register bits */
  291. #define MBX_MEMSZ_128KB 0x00020000 /* 128 kilobyte board */
  292. #define MBX_MEMSZ_256KB 0x00040000 /* 256 kilobyte board */
  293. #define MBX_MEMSZ_512KB 0x00080000 /* 512 kilobyte board */
  294. #define MBX_MEMSZ_1MB 0x00100000 /* 1 megabyte board */
  295. #define MBX_MEMSZ_2MB 0x00200000 /* 2 megabyte board */
  296. #define MBX_MEMSZ_4MB 0x00400000 /* 4 megabyte board */
  297. #define MBX_MEMSZ_8MB 0x00800000 /* 8 megabyte board */
  298. #define MBX_MEMSZ_16MB 0x01000000 /* 16 megabyte board */
  299. /***************************************/
  300. /*** MAILBOX #2 - BOARD TYPE ***/
  301. /***************************************/
  302. #define MBX_BTYPE_MASK 0x0000ffff /* PUTS Board Type Register */
  303. #define MBX_BTYPE_FAMILY_MASK 0x0000ff00 /* PUTS Board Family Register */
  304. #define MBX_BTYPE_SUBTYPE_MASK 0x000000ff /* PUTS Board Subtype */
  305. #define MBX_BTYPE_PLX9060 0x00000100 /* PLX family type */
  306. #define MBX_BTYPE_PLX9080 0x00000300 /* PLX wanXL100s family type */
  307. #define MBX_BTYPE_WANXL_4 0x00000104 /* wanXL400, 4-port */
  308. #define MBX_BTYPE_WANXL_2 0x00000102 /* wanXL200, 2-port */
  309. #define MBX_BTYPE_WANXL_1s 0x00000301 /* wanXL100s, 1-port */
  310. #define MBX_BTYPE_WANXL_1t 0x00000401 /* wanXL100T1, 1-port */
  311. /*****************************************/
  312. /*** MAILBOX #3 - SHMQ MAILBOX ***/
  313. /*****************************************/
  314. #define MBX_SMBX_MASK 0x000000ff /* PUTS SHMQ Mailbox bits */
  315. /***************************************/
  316. /*** GENERIC HOST-SIDE DRIVER ***/
  317. /***************************************/
  318. #define MBX_ERR 0
  319. #define MBX_OK 1
  320. /* mailbox check routine - type of testing */
  321. #define MBXCHK_STS 0x00 /* check for PUTS status */
  322. #define MBXCHK_NOWAIT 0x01 /* dont care about PUTS status */
  323. /* system allocates this many bytes for address mapping mailbox space */
  324. #define MBX_ADDR_SPACE_360 0x80 /* wanXL100s/200/400 */
  325. #define MBX_ADDR_MASK_360 (MBX_ADDR_SPACE_360-1)
  326. static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
  327. {
  328. void __iomem *dma_cs_addr;
  329. uint8_t dma_status;
  330. const int timeout = 10000;
  331. unsigned int i;
  332. if (channel)
  333. dma_cs_addr = iobase + PLX_DMA1_CS_REG;
  334. else
  335. dma_cs_addr = iobase + PLX_DMA0_CS_REG;
  336. /* abort dma transfer if necessary */
  337. dma_status = readb(dma_cs_addr);
  338. if ((dma_status & PLX_DMA_EN_BIT) == 0)
  339. return 0;
  340. /* wait to make sure done bit is zero */
  341. for (i = 0; (dma_status & PLX_DMA_DONE_BIT) && i < timeout; i++) {
  342. udelay(1);
  343. dma_status = readb(dma_cs_addr);
  344. }
  345. if (i == timeout) {
  346. printk
  347. ("plx9080: cancel() timed out waiting for dma %i done clear\n",
  348. channel);
  349. return -ETIMEDOUT;
  350. }
  351. /* disable and abort channel */
  352. writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);
  353. /* wait for dma done bit */
  354. dma_status = readb(dma_cs_addr);
  355. for (i = 0; (dma_status & PLX_DMA_DONE_BIT) == 0 && i < timeout; i++) {
  356. udelay(1);
  357. dma_status = readb(dma_cs_addr);
  358. }
  359. if (i == timeout) {
  360. printk
  361. ("plx9080: cancel() timed out waiting for dma %i done set\n",
  362. channel);
  363. return -ETIMEDOUT;
  364. }
  365. return 0;
  366. }
  367. #endif /* __COMEDI_PLX9080_H */