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/drivers/staging/comedi/drivers/plx9080.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C Header | 429 lines | 273 code | 62 blank | 94 comment | 12 complexity | cf51f68bbb72bbc67d2c905c832b1cbc MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1/* plx9080.h
  2 *
  3 * Copyright (C) 2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net>
  4 *
  5 * I modified this file from the plx9060.h header for the
  6 * wanXL device driver in the linux kernel,
  7 * for the register offsets and bit definitions.  Made minor modifications,
  8 * added plx9080 registers and
  9 * stripped out stuff that was specifically for the wanXL driver.
 10 * Note: I've only made sure the definitions are correct as far
 11 * as I make use of them.  There are still various plx9060-isms
 12 * left in this header file.
 13 *
 14 ********************************************************************
 15 *
 16 * Copyright (C) 1999 RG Studio s.c.
 17 * Written by Krzysztof Halasa <khc@rgstudio.com.pl>
 18 *
 19 * Portions (C) SBE Inc., used by permission.
 20 *
 21 * This program is free software; you can redistribute it and/or
 22 * modify it under the terms of the GNU General Public License
 23 * as published by the Free Software Foundation; either version
 24 * 2 of the License, or (at your option) any later version.
 25 */
 26
 27#ifndef __COMEDI_PLX9080_H
 28#define __COMEDI_PLX9080_H
 29
 30/*  descriptor block used for chained dma transfers */
 31struct plx_dma_desc {
 32	volatile uint32_t pci_start_addr;
 33	volatile uint32_t local_start_addr;
 34	/* transfer_size is in bytes, only first 23 bits of register are used */
 35	volatile uint32_t transfer_size;
 36	/* address of next descriptor (quad word aligned), plus some
 37	 * additional bits (see PLX_DMA0_DESCRIPTOR_REG) */
 38	volatile uint32_t next;
 39};
 40
 41/**********************************************************************
 42**            Register Offsets and Bit Definitions
 43**
 44** Note: All offsets zero relative.  IE. Some standard base address
 45** must be added to the Register Number to properly access the register.
 46**
 47**********************************************************************/
 48
 49#define PLX_LAS0RNG_REG         0x0000	/* L, Local Addr Space 0 Range Register */
 50#define PLX_LAS1RNG_REG         0x00f0	/* L, Local Addr Space 1 Range Register */
 51#define  LRNG_IO           0x00000001	/* Map to: 1=I/O, 0=Mem */
 52#define  LRNG_ANY32        0x00000000	/* Locate anywhere in 32 bit */
 53#define  LRNG_LT1MB        0x00000002	/* Locate in 1st meg */
 54#define  LRNG_ANY64        0x00000004	/* Locate anywhere in 64 bit */
 55#define  LRNG_MEM_MASK     0xfffffff0	/*  bits that specify range for memory io */
 56#define  LRNG_IO_MASK     0xfffffffa	/*  bits that specify range for normal io */
 57
 58#define PLX_LAS0MAP_REG         0x0004	/* L, Local Addr Space 0 Remap Register */
 59#define PLX_LAS1MAP_REG         0x00f4	/* L, Local Addr Space 1 Remap Register */
 60#define  LMAP_EN           0x00000001	/* Enable slave decode */
 61#define  LMAP_MEM_MASK     0xfffffff0	/*  bits that specify decode for memory io */
 62#define  LMAP_IO_MASK     0xfffffffa	/*  bits that specify decode bits for normal io */
 63
 64/* Mode/Arbitration Register.
 65*/
 66#define PLX_MARB_REG         0x8	/* L, Local Arbitration Register */
 67#define PLX_DMAARB_REG      0xac
 68enum marb_bits {
 69	MARB_LLT_MASK = 0x000000ff,	/* Local Bus Latency Timer */
 70	MARB_LPT_MASK = 0x0000ff00,	/* Local Bus Pause Timer */
 71	MARB_LTEN = 0x00010000,	/* Latency Timer Enable */
 72	MARB_LPEN = 0x00020000,	/* Pause Timer Enable */
 73	MARB_BREQ = 0x00040000,	/* Local Bus BREQ Enable */
 74	MARB_DMA_PRIORITY_MASK = 0x00180000,
 75	MARB_LBDS_GIVE_UP_BUS_MODE = 0x00200000,	/* local bus direct slave give up bus mode */
 76	MARB_DS_LLOCK_ENABLE = 0x00400000,	/* direct slave LLOCKo# enable */
 77	MARB_PCI_REQUEST_MODE = 0x00800000,
 78	MARB_PCIv21_MODE = 0x01000000,	/* pci specification v2.1 mode */
 79	MARB_PCI_READ_NO_WRITE_MODE = 0x02000000,
 80	MARB_PCI_READ_WITH_WRITE_FLUSH_MODE = 0x04000000,
 81	MARB_GATE_TIMER_WITH_BREQ = 0x08000000,	/* gate local bus latency timer with BREQ */
 82	MARB_PCI_READ_NO_FLUSH_MODE = 0x10000000,
 83	MARB_USE_SUBSYSTEM_IDS = 0x20000000,
 84};
 85
 86#define PLX_BIGEND_REG 0xc
 87enum bigend_bits {
 88	BIGEND_CONFIG = 0x1,	/* use big endian ordering for configuration register accesses */
 89	BIGEND_DIRECT_MASTER = 0x2,
 90	BIGEND_DIRECT_SLAVE_LOCAL0 = 0x4,
 91	BIGEND_ROM = 0x8,
 92	BIGEND_BYTE_LANE = 0x10,	/* use byte lane consisting of most significant bits instead of least significant */
 93	BIGEND_DIRECT_SLAVE_LOCAL1 = 0x20,
 94	BIGEND_DMA1 = 0x40,
 95	BIGEND_DMA0 = 0x80,
 96};
 97
 98/* Note: The Expansion ROM  stuff is only relevant to the PC environment.
 99**       This expansion ROM code is executed by the host CPU at boot time.
100**       For this reason no bit definitions are provided here.
101*/
102#define PLX_ROMRNG_REG         0x0010	/* L, Expn ROM Space Range Register */
103#define PLX_ROMMAP_REG         0x0014	/* L, Local Addr Space Range Register */
104
105#define PLX_REGION0_REG         0x0018	/* L, Local Bus Region 0 Descriptor */
106#define  RGN_WIDTH         0x00000002	/* Local bus width bits */
107#define  RGN_8BITS         0x00000000	/* 08 bit Local Bus */
108#define  RGN_16BITS        0x00000001	/* 16 bit Local Bus */
109#define  RGN_32BITS        0x00000002	/* 32 bit Local Bus */
110#define  RGN_MWS           0x0000003C	/* Memory Access Wait States */
111#define  RGN_0MWS          0x00000000
112#define  RGN_1MWS          0x00000004
113#define  RGN_2MWS          0x00000008
114#define  RGN_3MWS          0x0000000C
115#define  RGN_4MWS          0x00000010
116#define  RGN_6MWS          0x00000018
117#define  RGN_8MWS          0x00000020
118#define  RGN_MRE           0x00000040	/* Memory Space Ready Input Enable */
119#define  RGN_MBE           0x00000080	/* Memory Space Bterm Input Enable */
120#define  RGN_READ_PREFETCH_DISABLE 0x00000100
121#define  RGN_ROM_PREFETCH_DISABLE 0x00000200
122#define  RGN_READ_PREFETCH_COUNT_ENABLE 0x00000400
123#define  RGN_RWS           0x003C0000	/* Expn ROM Wait States */
124#define  RGN_RRE           0x00400000	/* ROM Space Ready Input Enable */
125#define  RGN_RBE           0x00800000	/* ROM Space Bterm Input Enable */
126#define  RGN_MBEN          0x01000000	/* Memory Space Burst Enable */
127#define  RGN_RBEN          0x04000000	/* ROM Space Burst Enable */
128#define  RGN_THROT         0x08000000	/* De-assert TRDY when FIFO full */
129#define  RGN_TRD           0xF0000000	/* Target Ready Delay /8 */
130
131#define PLX_REGION1_REG         0x00f8	/* L, Local Bus Region 1 Descriptor */
132
133#define PLX_DMRNG_REG          0x001C	/* L, Direct Master Range Register */
134
135#define PLX_LBAPMEM_REG        0x0020	/* L, Lcl Base Addr for PCI mem space */
136
137#define PLX_LBAPIO_REG         0x0024	/* L, Lcl Base Addr for PCI I/O space */
138
139#define PLX_DMMAP_REG          0x0028	/* L, Direct Master Remap Register */
140#define  DMM_MAE           0x00000001	/* Direct Mstr Memory Acc Enable */
141#define  DMM_IAE           0x00000002	/* Direct Mstr I/O Acc Enable */
142#define  DMM_LCK           0x00000004	/* LOCK Input Enable */
143#define  DMM_PF4           0x00000008	/* Prefetch 4 Mode Enable */
144#define  DMM_THROT         0x00000010	/* Assert IRDY when read FIFO full */
145#define  DMM_PAF0          0x00000000	/* Programmable Almost fill level */
146#define  DMM_PAF1          0x00000020	/* Programmable Almost fill level */
147#define  DMM_PAF2          0x00000040	/* Programmable Almost fill level */
148#define  DMM_PAF3          0x00000060	/* Programmable Almost fill level */
149#define  DMM_PAF4          0x00000080	/* Programmable Almost fill level */
150#define  DMM_PAF5          0x000000A0	/* Programmable Almost fill level */
151#define  DMM_PAF6          0x000000C0	/* Programmable Almost fill level */
152#define  DMM_PAF7          0x000000D0	/* Programmable Almost fill level */
153#define  DMM_MAP           0xFFFF0000	/* Remap Address Bits */
154
155#define PLX_CAR_REG            0x002C	/* L, Configuration Address Register */
156#define  CAR_CT0           0x00000000	/* Config Type 0 */
157#define  CAR_CT1           0x00000001	/* Config Type 1 */
158#define  CAR_REG           0x000000FC	/* Register Number Bits */
159#define  CAR_FUN           0x00000700	/* Function Number Bits */
160#define  CAR_DEV           0x0000F800	/* Device Number Bits */
161#define  CAR_BUS           0x00FF0000	/* Bus Number Bits */
162#define  CAR_CFG           0x80000000	/* Config Spc Access Enable */
163
164#define PLX_DBR_IN_REG         0x0060	/* L, PCI to Local Doorbell Register */
165
166#define PLX_DBR_OUT_REG        0x0064	/* L, Local to PCI Doorbell Register */
167
168#define PLX_INTRCS_REG         0x0068	/* L, Interrupt Control/Status Reg */
169#define  ICS_AERR          0x00000001	/* Assert LSERR on ABORT */
170#define  ICS_PERR          0x00000002	/* Assert LSERR on Parity Error */
171#define  ICS_SERR          0x00000004	/* Generate PCI SERR# */
172#define  ICS_MBIE          0x00000008	/*  mailbox interrupt enable */
173#define  ICS_PIE           0x00000100	/* PCI Interrupt Enable */
174#define  ICS_PDIE          0x00000200	/* PCI Doorbell Interrupt Enable */
175#define  ICS_PAIE          0x00000400	/* PCI Abort Interrupt Enable */
176#define  ICS_PLIE          0x00000800	/* PCI Local Int Enable */
177#define  ICS_RAE           0x00001000	/* Retry Abort Enable */
178#define  ICS_PDIA          0x00002000	/* PCI Doorbell Interrupt Active */
179#define  ICS_PAIA          0x00004000	/* PCI Abort Interrupt Active */
180#define  ICS_LIA           0x00008000	/* Local Interrupt Active */
181#define  ICS_LIE           0x00010000	/* Local Interrupt Enable */
182#define  ICS_LDIE          0x00020000	/* Local Doorbell Int Enable */
183#define  ICS_DMA0_E        0x00040000	/* DMA #0 Interrupt Enable */
184#define  ICS_DMA1_E        0x00080000	/* DMA #1 Interrupt Enable */
185#define  ICS_LDIA          0x00100000	/* Local Doorbell Int Active */
186#define  ICS_DMA0_A        0x00200000	/* DMA #0 Interrupt Active */
187#define  ICS_DMA1_A        0x00400000	/* DMA #1 Interrupt Active */
188#define  ICS_BIA           0x00800000	/* BIST Interrupt Active */
189#define  ICS_TA_DM         0x01000000	/* Target Abort - Direct Master */
190#define  ICS_TA_DMA0       0x02000000	/* Target Abort - DMA #0 */
191#define  ICS_TA_DMA1       0x04000000	/* Target Abort - DMA #1 */
192#define  ICS_TA_RA         0x08000000	/* Target Abort - Retry Timeout */
193#define  ICS_MBIA(x)       (0x10000000 << ((x) & 0x3))	/*  mailbox x is active */
194
195#define PLX_CONTROL_REG        0x006C	/* L, EEPROM Cntl & PCI Cmd Codes */
196#define  CTL_RDMA          0x0000000E	/* DMA Read Command */
197#define  CTL_WDMA          0x00000070	/* DMA Write Command */
198#define  CTL_RMEM          0x00000600	/* Memory Read Command */
199#define  CTL_WMEM          0x00007000	/* Memory Write Command */
200#define  CTL_USERO         0x00010000	/* USERO output pin control bit */
201#define  CTL_USERI         0x00020000	/* USERI input pin bit */
202#define  CTL_EE_CLK        0x01000000	/* EEPROM Clock line */
203#define  CTL_EE_CS         0x02000000	/* EEPROM Chip Select */
204#define  CTL_EE_W          0x04000000	/* EEPROM Write bit */
205#define  CTL_EE_R          0x08000000	/* EEPROM Read bit */
206#define  CTL_EECHK         0x10000000	/* EEPROM Present bit */
207#define  CTL_EERLD         0x20000000	/* EEPROM Reload Register */
208#define  CTL_RESET         0x40000000	/* !! Adapter Reset !! */
209#define  CTL_READY         0x80000000	/* Local Init Done */
210
211#define PLX_ID_REG	0x70	/*  hard-coded plx vendor and device ids */
212
213#define PLX_REVISION_REG	0x74	/*  silicon revision */
214
215#define PLX_DMA0_MODE_REG	0x80	/*  dma channel 0 mode register */
216#define PLX_DMA1_MODE_REG	0x94	/*  dma channel 0 mode register */
217#define  PLX_LOCAL_BUS_16_WIDE_BITS	0x1
218#define  PLX_LOCAL_BUS_32_WIDE_BITS	0x3
219#define  PLX_LOCAL_BUS_WIDTH_MASK	0x3
220#define  PLX_DMA_EN_READYIN_BIT	0x40	/*  enable ready in input */
221#define  PLX_EN_BTERM_BIT	0x80	/*  enable BTERM# input */
222#define  PLX_DMA_LOCAL_BURST_EN_BIT	0x100	/*  enable local burst mode */
223#define  PLX_EN_CHAIN_BIT	0x200	/*  enables chaining */
224#define  PLX_EN_DMA_DONE_INTR_BIT	0x400	/*  enables interrupt on dma done */
225#define  PLX_LOCAL_ADDR_CONST_BIT	0x800	/*  hold local address constant (don't increment) */
226#define  PLX_DEMAND_MODE_BIT	0x1000	/*  enables demand-mode for dma transfer */
227#define  PLX_EOT_ENABLE_BIT	0x4000
228#define  PLX_STOP_MODE_BIT 0x8000
229#define  PLX_DMA_INTR_PCI_BIT	0x20000	/*  routes dma interrupt to pci bus (instead of local bus) */
230
231#define PLX_DMA0_PCI_ADDRESS_REG	0x84	/*  pci address that dma transfers start at */
232#define PLX_DMA1_PCI_ADDRESS_REG	0x98
233
234#define PLX_DMA0_LOCAL_ADDRESS_REG	0x88	/*  local address that dma transfers start at */
235#define PLX_DMA1_LOCAL_ADDRESS_REG	0x9c
236
237#define PLX_DMA0_TRANSFER_SIZE_REG	0x8c	/*  number of bytes to transfer (first 23 bits) */
238#define PLX_DMA1_TRANSFER_SIZE_REG	0xa0
239
240#define PLX_DMA0_DESCRIPTOR_REG	0x90	/*  descriptor pointer register */
241#define PLX_DMA1_DESCRIPTOR_REG	0xa4
242#define  PLX_DESC_IN_PCI_BIT	0x1	/*  descriptor is located in pci space (not local space) */
243#define  PLX_END_OF_CHAIN_BIT	0x2	/*  end of chain bit */
244#define  PLX_INTR_TERM_COUNT	0x4	/*  interrupt when this descriptor's transfer is finished */
245#define  PLX_XFER_LOCAL_TO_PCI 0x8	/*  transfer from local to pci bus (not pci to local) */
246
247#define PLX_DMA0_CS_REG	0xa8	/*  command status register */
248#define PLX_DMA1_CS_REG	0xa9
249#define  PLX_DMA_EN_BIT	0x1	/*  enable dma channel */
250#define  PLX_DMA_START_BIT	0x2	/*  start dma transfer */
251#define  PLX_DMA_ABORT_BIT	0x4	/*  abort dma transfer */
252#define  PLX_CLEAR_DMA_INTR_BIT	0x8	/*  clear dma interrupt */
253#define  PLX_DMA_DONE_BIT	0x10	/*  transfer done status bit */
254
255#define PLX_DMA0_THRESHOLD_REG	0xb0	/*  command status register */
256
257/*
258 * Accesses near the end of memory can cause the PLX chip
259 * to pre-fetch data off of end-of-ram.  Limit the size of
260 * memory so host-side accesses cannot occur.
261 */
262
263#define PLX_PREFETCH   32
264
265/*
266 * The PCI Interface, via the PCI-9060 Chip, has up to eight (8) Mailbox
267 * Registers.  The PUTS (Power-Up Test Suite) handles the board-side
268 * interface/interaction using the first 4 registers.  Specifications for
269 * the use of the full PUTS' command and status interface is contained
270 * within a separate SBE PUTS Manual.  The Host-Side Device Driver only
271 * uses a subset of the full PUTS interface.
272 */
273
274/*****************************************/
275/***    MAILBOX #(-1) - MEM ACCESS STS ***/
276/*****************************************/
277
278#define MBX_STS_VALID      0x57584744	/* 'WXGD' */
279#define MBX_STS_DILAV      0x44475857	/* swapped = 'DGXW' */
280
281/*****************************************/
282/***    MAILBOX #0  -  PUTS STATUS     ***/
283/*****************************************/
284
285#define MBX_STS_MASK       0x000000ff	/* PUTS Status Register bits */
286#define MBX_STS_TMASK      0x0000000f	/* register bits for TEST number */
287
288#define MBX_STS_PCIRESET   0x00000100	/* Host issued PCI reset request */
289#define MBX_STS_BUSY       0x00000080	/* PUTS is in progress */
290#define MBX_STS_ERROR      0x00000040	/* PUTS has failed */
291#define MBX_STS_RESERVED   0x000000c0	/* Undefined -> status in transition.
292					   We are in process of changing
293					   bits; we SET Error bit before
294					   RESET of Busy bit */
295
296#define MBX_RESERVED_5     0x00000020	/* FYI: reserved/unused bit */
297#define MBX_RESERVED_4     0x00000010	/* FYI: reserved/unused bit */
298
299/******************************************/
300/***    MAILBOX #1  -  PUTS COMMANDS    ***/
301/******************************************/
302
303/*
304 * Any attempt to execute an unimplement command results in the PUTS
305 * interface executing a NOOP and continuing as if the offending command
306 * completed normally.  Note: this supplies a simple method to interrogate
307 * mailbox command processing functionality.
308 */
309
310#define MBX_CMD_MASK       0xffff0000	/* PUTS Command Register bits */
311
312#define MBX_CMD_ABORTJ     0x85000000	/* abort and jump */
313#define MBX_CMD_RESETP     0x86000000	/* reset and pause at start */
314#define MBX_CMD_PAUSE      0x87000000	/* pause immediately */
315#define MBX_CMD_PAUSEC     0x88000000	/* pause on completion */
316#define MBX_CMD_RESUME     0x89000000	/* resume operation */
317#define MBX_CMD_STEP       0x8a000000	/* single step tests */
318
319#define MBX_CMD_BSWAP      0x8c000000	/* identify byte swap scheme */
320#define MBX_CMD_BSWAP_0    0x8c000000	/* use scheme 0 */
321#define MBX_CMD_BSWAP_1    0x8c000001	/* use scheme 1 */
322
323#define MBX_CMD_SETHMS     0x8d000000	/* setup host memory access window
324					   size */
325#define MBX_CMD_SETHBA     0x8e000000	/* setup host memory access base
326					   address */
327#define MBX_CMD_MGO        0x8f000000	/* perform memory setup and continue
328					   (IE. Done) */
329#define MBX_CMD_NOOP       0xFF000000	/* dummy, illegal command */
330
331/*****************************************/
332/***    MAILBOX #2  -  MEMORY SIZE     ***/
333/*****************************************/
334
335#define MBX_MEMSZ_MASK     0xffff0000	/* PUTS Memory Size Register bits */
336
337#define MBX_MEMSZ_128KB    0x00020000	/* 128 kilobyte board */
338#define MBX_MEMSZ_256KB    0x00040000	/* 256 kilobyte board */
339#define MBX_MEMSZ_512KB    0x00080000	/* 512 kilobyte board */
340#define MBX_MEMSZ_1MB      0x00100000	/* 1 megabyte board */
341#define MBX_MEMSZ_2MB      0x00200000	/* 2 megabyte board */
342#define MBX_MEMSZ_4MB      0x00400000	/* 4 megabyte board */
343#define MBX_MEMSZ_8MB      0x00800000	/* 8 megabyte board */
344#define MBX_MEMSZ_16MB     0x01000000	/* 16 megabyte board */
345
346/***************************************/
347/***    MAILBOX #2  -  BOARD TYPE    ***/
348/***************************************/
349
350#define MBX_BTYPE_MASK          0x0000ffff	/* PUTS Board Type Register */
351#define MBX_BTYPE_FAMILY_MASK   0x0000ff00	/* PUTS Board Family Register */
352#define MBX_BTYPE_SUBTYPE_MASK  0x000000ff	/* PUTS Board Subtype */
353
354#define MBX_BTYPE_PLX9060       0x00000100	/* PLX family type */
355#define MBX_BTYPE_PLX9080       0x00000300	/* PLX wanXL100s family type */
356
357#define MBX_BTYPE_WANXL_4       0x00000104	/* wanXL400, 4-port */
358#define MBX_BTYPE_WANXL_2       0x00000102	/* wanXL200, 2-port */
359#define MBX_BTYPE_WANXL_1s      0x00000301	/* wanXL100s, 1-port */
360#define MBX_BTYPE_WANXL_1t      0x00000401	/* wanXL100T1, 1-port */
361
362/*****************************************/
363/***    MAILBOX #3  -  SHMQ MAILBOX    ***/
364/*****************************************/
365
366#define MBX_SMBX_MASK           0x000000ff	/* PUTS SHMQ Mailbox bits */
367
368/***************************************/
369/***    GENERIC HOST-SIDE DRIVER     ***/
370/***************************************/
371
372#define MBX_ERR    0
373#define MBX_OK     1
374
375/* mailbox check routine - type of testing */
376#define MBXCHK_STS      0x00	/* check for PUTS status */
377#define MBXCHK_NOWAIT   0x01	/* dont care about PUTS status */
378
379/* system allocates this many bytes for address mapping mailbox space */
380#define MBX_ADDR_SPACE_360 0x80	/* wanXL100s/200/400 */
381#define MBX_ADDR_MASK_360 (MBX_ADDR_SPACE_360-1)
382
383static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
384{
385	void __iomem *dma_cs_addr;
386	uint8_t dma_status;
387	const int timeout = 10000;
388	unsigned int i;
389
390	if (channel)
391		dma_cs_addr = iobase + PLX_DMA1_CS_REG;
392	else
393		dma_cs_addr = iobase + PLX_DMA0_CS_REG;
394
395	/*  abort dma transfer if necessary */
396	dma_status = readb(dma_cs_addr);
397	if ((dma_status & PLX_DMA_EN_BIT) == 0)
398		return 0;
399
400	/*  wait to make sure done bit is zero */
401	for (i = 0; (dma_status & PLX_DMA_DONE_BIT) && i < timeout; i++) {
402		udelay(1);
403		dma_status = readb(dma_cs_addr);
404	}
405	if (i == timeout) {
406		printk
407		    ("plx9080: cancel() timed out waiting for dma %i done clear\n",
408		     channel);
409		return -ETIMEDOUT;
410	}
411	/*  disable and abort channel */
412	writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);
413	/*  wait for dma done bit */
414	dma_status = readb(dma_cs_addr);
415	for (i = 0; (dma_status & PLX_DMA_DONE_BIT) == 0 && i < timeout; i++) {
416		udelay(1);
417		dma_status = readb(dma_cs_addr);
418	}
419	if (i == timeout) {
420		printk
421		    ("plx9080: cancel() timed out waiting for dma %i done set\n",
422		     channel);
423		return -ETIMEDOUT;
424	}
425
426	return 0;
427}
428
429#endif /* __COMEDI_PLX9080_H */