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/drivers/staging/comedi/drivers/ni_mio_common.c

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C | 6005 lines | 4968 code | 604 blank | 433 comment | 869 complexity | c44039260f42b06fffd172846b247bbb MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0

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   1/*
   2    comedi/drivers/ni_mio_common.c
   3    Hardware driver for DAQ-STC based boards
   4
   5    COMEDI - Linux Control and Measurement Device Interface
   6    Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7    Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23*/
  24
  25/*
  26	This file is meant to be included by another file, e.g.,
  27	ni_atmio.c or ni_pcimio.c.
  28
  29	Interrupt support originally added by Truxton Fulton
  30	<trux@truxton.com>
  31
  32	References (from ftp://ftp.natinst.com/support/manuals):
  33
  34	   340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35	   341079b.pdf  PCI E Series RLPM
  36	   340934b.pdf  DAQ-STC reference manual
  37	67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  38	release_ni611x.pdf
  39	release_ni67xx.pdf
  40	Other possibly relevant info:
  41
  42	   320517c.pdf  User manual (obsolete)
  43	   320517f.pdf  User manual (new)
  44	   320889a.pdf  delete
  45	   320906c.pdf  maximum signal ratings
  46	   321066a.pdf  about 16x
  47	   321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48	   321808a.pdf  about at-mio-16e-10 rev P
  49	   321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50	   321838a.pdf  about at-mio-16de-10 rev N
  51
  52	ISSUES:
  53
  54	 - the interrupt routine needs to be cleaned up
  55
  56	2006-02-07: S-Series PCI-6143: Support has been added but is not
  57		fully tested as yet. Terry Barnaby, BEAM Ltd.
  58*/
  59
  60/* #define DEBUG_INTERRUPT */
  61/* #define DEBUG_STATUS_A */
  62/* #define DEBUG_STATUS_B */
  63
  64#include <linux/interrupt.h>
  65#include <linux/sched.h>
  66#include "8255.h"
  67#include "mite.h"
  68#include "comedi_fc.h"
  69
  70#ifndef MDPRINTK
  71#define MDPRINTK(format, args...)
  72#endif
  73
  74/* A timeout count */
  75#define NI_TIMEOUT 1000
  76static const unsigned old_RTSI_clock_channel = 7;
  77
  78/* Note: this table must match the ai_gain_* definitions */
  79static const short ni_gainlkup[][16] = {
  80	[ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  81			0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  82	[ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  83	[ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  84			0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  85	[ai_gain_4] = {0, 1, 4, 7},
  86	[ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  87			  0x003, 0x004, 0x005, 0x006},
  88	[ai_gain_622x] = {0, 1, 4, 5},
  89	[ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  90	[ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  91};
  92
  93static const struct comedi_lrange range_ni_E_ai = { 16, {
  94							 RANGE(-10, 10),
  95							 RANGE(-5, 5),
  96							 RANGE(-2.5, 2.5),
  97							 RANGE(-1, 1),
  98							 RANGE(-0.5, 0.5),
  99							 RANGE(-0.25, 0.25),
 100							 RANGE(-0.1, 0.1),
 101							 RANGE(-0.05, 0.05),
 102							 RANGE(0, 20),
 103							 RANGE(0, 10),
 104							 RANGE(0, 5),
 105							 RANGE(0, 2),
 106							 RANGE(0, 1),
 107							 RANGE(0, 0.5),
 108							 RANGE(0, 0.2),
 109							 RANGE(0, 0.1),
 110							 }
 111};
 112
 113static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
 114								RANGE(-10, 10),
 115								RANGE(-5, 5),
 116								RANGE(-1, 1),
 117								RANGE(-0.1,
 118								      0.1),
 119								RANGE(0, 10),
 120								RANGE(0, 5),
 121								RANGE(0, 1),
 122								RANGE(0, 0.1),
 123								}
 124};
 125
 126static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
 127								   RANGE(-10,
 128									 10),
 129								   RANGE(-5, 5),
 130								   RANGE(-2, 2),
 131								   RANGE(-1, 1),
 132								   RANGE(-0.5,
 133									 0.5),
 134								   RANGE(-0.2,
 135									 0.2),
 136								   RANGE(-0.1,
 137									 0.1),
 138								   RANGE(0, 10),
 139								   RANGE(0, 5),
 140								   RANGE(0, 2),
 141								   RANGE(0, 1),
 142								   RANGE(0,
 143									 0.5),
 144								   RANGE(0,
 145									 0.2),
 146								   RANGE(0,
 147									 0.1),
 148								   }
 149};
 150
 151static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
 152								 RANGE(-10, 10),
 153								 RANGE(-5, 5),
 154								 RANGE(-0.5,
 155								       0.5),
 156								 RANGE(-0.05,
 157								       0.05),
 158								 }
 159};
 160
 161static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
 162							     RANGE(-50, 50),
 163							     RANGE(-20, 20),
 164							     RANGE(-10, 10),
 165							     RANGE(-5, 5),
 166							     RANGE(-2, 2),
 167							     RANGE(-1, 1),
 168							     RANGE(-0.5, 0.5),
 169							     RANGE(-0.2, 0.2),
 170							     }
 171};
 172
 173static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
 174							     RANGE(-10, 10),
 175							     RANGE(-5, 5),
 176							     RANGE(-1, 1),
 177							     RANGE(-0.2, 0.2),
 178							     }
 179};
 180
 181static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
 182							     RANGE(-10, 10),
 183							     RANGE(-5, 5),
 184							     RANGE(-2, 2),
 185							     RANGE(-1, 1),
 186							     RANGE(-0.5, 0.5),
 187							     RANGE(-0.2, 0.2),
 188							     RANGE(-0.1, 0.1),
 189							     }
 190};
 191
 192static const struct comedi_lrange range_ni_S_ai_6143 = { 1, {
 193							     RANGE(-5, +5),
 194							     }
 195};
 196
 197static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
 198							    RANGE(-10, 10),
 199							    RANGE(0, 10),
 200							    RANGE_ext(-1, 1),
 201							    RANGE_ext(0, 1),
 202							    }
 203};
 204
 205static const struct comedi_lrange *const ni_range_lkup[] = {
 206	[ai_gain_16] = &range_ni_E_ai,
 207	[ai_gain_8] = &range_ni_E_ai_limited,
 208	[ai_gain_14] = &range_ni_E_ai_limited14,
 209	[ai_gain_4] = &range_ni_E_ai_bipolar4,
 210	[ai_gain_611x] = &range_ni_E_ai_611x,
 211	[ai_gain_622x] = &range_ni_M_ai_622x,
 212	[ai_gain_628x] = &range_ni_M_ai_628x,
 213	[ai_gain_6143] = &range_ni_S_ai_6143
 214};
 215
 216static int ni_dio_insn_config(struct comedi_device *dev,
 217			      struct comedi_subdevice *s,
 218			      struct comedi_insn *insn, unsigned int *data);
 219static int ni_dio_insn_bits(struct comedi_device *dev,
 220			    struct comedi_subdevice *s,
 221			    struct comedi_insn *insn, unsigned int *data);
 222static int ni_cdio_cmdtest(struct comedi_device *dev,
 223			   struct comedi_subdevice *s, struct comedi_cmd *cmd);
 224static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 225static int ni_cdio_cancel(struct comedi_device *dev,
 226			  struct comedi_subdevice *s);
 227static void handle_cdio_interrupt(struct comedi_device *dev);
 228static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 229			  unsigned int trignum);
 230
 231static int ni_serial_insn_config(struct comedi_device *dev,
 232				 struct comedi_subdevice *s,
 233				 struct comedi_insn *insn, unsigned int *data);
 234static int ni_serial_hw_readwrite8(struct comedi_device *dev,
 235				   struct comedi_subdevice *s,
 236				   unsigned char data_out,
 237				   unsigned char *data_in);
 238static int ni_serial_sw_readwrite8(struct comedi_device *dev,
 239				   struct comedi_subdevice *s,
 240				   unsigned char data_out,
 241				   unsigned char *data_in);
 242
 243static int ni_calib_insn_read(struct comedi_device *dev,
 244			      struct comedi_subdevice *s,
 245			      struct comedi_insn *insn, unsigned int *data);
 246static int ni_calib_insn_write(struct comedi_device *dev,
 247			       struct comedi_subdevice *s,
 248			       struct comedi_insn *insn, unsigned int *data);
 249
 250static int ni_eeprom_insn_read(struct comedi_device *dev,
 251			       struct comedi_subdevice *s,
 252			       struct comedi_insn *insn, unsigned int *data);
 253static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
 254					struct comedi_subdevice *s,
 255					struct comedi_insn *insn,
 256					unsigned int *data);
 257
 258static int ni_pfi_insn_bits(struct comedi_device *dev,
 259			    struct comedi_subdevice *s,
 260			    struct comedi_insn *insn, unsigned int *data);
 261static int ni_pfi_insn_config(struct comedi_device *dev,
 262			      struct comedi_subdevice *s,
 263			      struct comedi_insn *insn, unsigned int *data);
 264static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
 265				       unsigned chan);
 266
 267static void ni_rtsi_init(struct comedi_device *dev);
 268static int ni_rtsi_insn_bits(struct comedi_device *dev,
 269			     struct comedi_subdevice *s,
 270			     struct comedi_insn *insn, unsigned int *data);
 271static int ni_rtsi_insn_config(struct comedi_device *dev,
 272			       struct comedi_subdevice *s,
 273			       struct comedi_insn *insn, unsigned int *data);
 274
 275static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
 276static int ni_read_eeprom(struct comedi_device *dev, int addr);
 277
 278#ifdef DEBUG_STATUS_A
 279static void ni_mio_print_status_a(int status);
 280#else
 281#define ni_mio_print_status_a(a)
 282#endif
 283#ifdef DEBUG_STATUS_B
 284static void ni_mio_print_status_b(int status);
 285#else
 286#define ni_mio_print_status_b(a)
 287#endif
 288
 289static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 290#ifndef PCIDMA
 291static void ni_handle_fifo_half_full(struct comedi_device *dev);
 292static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 293				 struct comedi_subdevice *s);
 294#endif
 295static void ni_handle_fifo_dregs(struct comedi_device *dev);
 296static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 297			 unsigned int trignum);
 298static void ni_load_channelgain_list(struct comedi_device *dev,
 299				     unsigned int n_chan, unsigned int *list);
 300static void shutdown_ai_command(struct comedi_device *dev);
 301
 302static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 303			 unsigned int trignum);
 304
 305static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 306
 307static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
 308
 309static int ni_gpct_insn_write(struct comedi_device *dev,
 310			      struct comedi_subdevice *s,
 311			      struct comedi_insn *insn, unsigned int *data);
 312static int ni_gpct_insn_read(struct comedi_device *dev,
 313			     struct comedi_subdevice *s,
 314			     struct comedi_insn *insn, unsigned int *data);
 315static int ni_gpct_insn_config(struct comedi_device *dev,
 316			       struct comedi_subdevice *s,
 317			       struct comedi_insn *insn, unsigned int *data);
 318static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 319static int ni_gpct_cmdtest(struct comedi_device *dev,
 320			   struct comedi_subdevice *s, struct comedi_cmd *cmd);
 321static int ni_gpct_cancel(struct comedi_device *dev,
 322			  struct comedi_subdevice *s);
 323static void handle_gpct_interrupt(struct comedi_device *dev,
 324				  unsigned short counter_index);
 325
 326static int init_cs5529(struct comedi_device *dev);
 327static int cs5529_do_conversion(struct comedi_device *dev,
 328				unsigned short *data);
 329static int cs5529_ai_insn_read(struct comedi_device *dev,
 330			       struct comedi_subdevice *s,
 331			       struct comedi_insn *insn, unsigned int *data);
 332#ifdef NI_CS5529_DEBUG
 333static unsigned int cs5529_config_read(struct comedi_device *dev,
 334				       unsigned int reg_select_bits);
 335#endif
 336static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
 337				unsigned int reg_select_bits);
 338
 339static int ni_m_series_pwm_config(struct comedi_device *dev,
 340				  struct comedi_subdevice *s,
 341				  struct comedi_insn *insn, unsigned int *data);
 342static int ni_6143_pwm_config(struct comedi_device *dev,
 343			      struct comedi_subdevice *s,
 344			      struct comedi_insn *insn, unsigned int *data);
 345
 346static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
 347			       unsigned period_ns);
 348static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
 349static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
 350
 351enum aimodes {
 352	AIMODE_NONE = 0,
 353	AIMODE_HALF_FULL = 1,
 354	AIMODE_SCAN = 2,
 355	AIMODE_SAMPLE = 3,
 356};
 357
 358enum ni_common_subdevices {
 359	NI_AI_SUBDEV,
 360	NI_AO_SUBDEV,
 361	NI_DIO_SUBDEV,
 362	NI_8255_DIO_SUBDEV,
 363	NI_UNUSED_SUBDEV,
 364	NI_CALIBRATION_SUBDEV,
 365	NI_EEPROM_SUBDEV,
 366	NI_PFI_DIO_SUBDEV,
 367	NI_CS5529_CALIBRATION_SUBDEV,
 368	NI_SERIAL_SUBDEV,
 369	NI_RTSI_SUBDEV,
 370	NI_GPCT0_SUBDEV,
 371	NI_GPCT1_SUBDEV,
 372	NI_FREQ_OUT_SUBDEV,
 373	NI_NUM_SUBDEVICES
 374};
 375static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 376{
 377	switch (counter_index) {
 378	case 0:
 379		return NI_GPCT0_SUBDEV;
 380		break;
 381	case 1:
 382		return NI_GPCT1_SUBDEV;
 383		break;
 384	default:
 385		break;
 386	}
 387	BUG();
 388	return NI_GPCT0_SUBDEV;
 389}
 390
 391enum timebase_nanoseconds {
 392	TIMEBASE_1_NS = 50,
 393	TIMEBASE_2_NS = 10000
 394};
 395
 396#define SERIAL_DISABLED		0
 397#define SERIAL_600NS		600
 398#define SERIAL_1_2US		1200
 399#define SERIAL_10US			10000
 400
 401static const int num_adc_stages_611x = 3;
 402
 403static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
 404			       unsigned ai_mite_status);
 405static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
 406			       unsigned ao_mite_status);
 407static void get_last_sample_611x(struct comedi_device *dev);
 408static void get_last_sample_6143(struct comedi_device *dev);
 409
 410static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 411				   unsigned bit_mask, unsigned bit_values)
 412{
 413	unsigned long flags;
 414
 415	spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 416	switch (reg) {
 417	case Interrupt_A_Enable_Register:
 418		devpriv->int_a_enable_reg &= ~bit_mask;
 419		devpriv->int_a_enable_reg |= bit_values & bit_mask;
 420		devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
 421				    Interrupt_A_Enable_Register);
 422		break;
 423	case Interrupt_B_Enable_Register:
 424		devpriv->int_b_enable_reg &= ~bit_mask;
 425		devpriv->int_b_enable_reg |= bit_values & bit_mask;
 426		devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
 427				    Interrupt_B_Enable_Register);
 428		break;
 429	case IO_Bidirection_Pin_Register:
 430		devpriv->io_bidirection_pin_reg &= ~bit_mask;
 431		devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 432		devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
 433				    IO_Bidirection_Pin_Register);
 434		break;
 435	case AI_AO_Select:
 436		devpriv->ai_ao_select_reg &= ~bit_mask;
 437		devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 438		ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 439		break;
 440	case G0_G1_Select:
 441		devpriv->g0_g1_select_reg &= ~bit_mask;
 442		devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 443		ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 444		break;
 445	default:
 446		printk("Warning %s() called with invalid register\n", __func__);
 447		printk("reg is %d\n", reg);
 448		break;
 449	}
 450	mmiowb();
 451	spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 452}
 453
 454#ifdef PCIDMA
 455static int ni_ai_drain_dma(struct comedi_device *dev);
 456
 457/* DMA channel setup */
 458
 459/* negative channel means no channel */
 460static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 461{
 462	unsigned bitfield;
 463
 464	if (channel >= 0) {
 465		bitfield =
 466		    (ni_stc_dma_channel_select_bitfield(channel) <<
 467		     AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 468	} else {
 469		bitfield = 0;
 470	}
 471	ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 472}
 473
 474/* negative channel means no channel */
 475static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 476{
 477	unsigned bitfield;
 478
 479	if (channel >= 0) {
 480		bitfield =
 481		    (ni_stc_dma_channel_select_bitfield(channel) <<
 482		     AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 483	} else {
 484		bitfield = 0;
 485	}
 486	ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 487}
 488
 489/* negative mite_channel means no channel */
 490static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 491					   unsigned gpct_index,
 492					   int mite_channel)
 493{
 494	unsigned bitfield;
 495
 496	if (mite_channel >= 0) {
 497		bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 498	} else {
 499		bitfield = 0;
 500	}
 501	ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 502			bitfield);
 503}
 504
 505/* negative mite_channel means no channel */
 506static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 507					  int mite_channel)
 508{
 509	unsigned long flags;
 510
 511	spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 512	devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 513	if (mite_channel >= 0) {
 514		/*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 515		   under the assumption the cdio dma selection works just like ai/ao/gpct.
 516		   Definitely works for dma channels 0 and 1. */
 517		devpriv->cdio_dma_select_reg |=
 518		    (ni_stc_dma_channel_select_bitfield(mite_channel) <<
 519		     CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 520	}
 521	ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 522	mmiowb();
 523	spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 524}
 525
 526static int ni_request_ai_mite_channel(struct comedi_device *dev)
 527{
 528	unsigned long flags;
 529
 530	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 531	BUG_ON(devpriv->ai_mite_chan);
 532	devpriv->ai_mite_chan =
 533	    mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 534	if (devpriv->ai_mite_chan == NULL) {
 535		spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 536		comedi_error(dev,
 537			     "failed to reserve mite dma channel for analog input.");
 538		return -EBUSY;
 539	}
 540	devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 541	ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 542	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 543	return 0;
 544}
 545
 546static int ni_request_ao_mite_channel(struct comedi_device *dev)
 547{
 548	unsigned long flags;
 549
 550	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 551	BUG_ON(devpriv->ao_mite_chan);
 552	devpriv->ao_mite_chan =
 553	    mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 554	if (devpriv->ao_mite_chan == NULL) {
 555		spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 556		comedi_error(dev,
 557			     "failed to reserve mite dma channel for analog outut.");
 558		return -EBUSY;
 559	}
 560	devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 561	ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 562	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 563	return 0;
 564}
 565
 566static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 567					unsigned gpct_index,
 568					enum comedi_io_direction direction)
 569{
 570	unsigned long flags;
 571	struct mite_channel *mite_chan;
 572
 573	BUG_ON(gpct_index >= NUM_GPCT);
 574	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 575	BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 576	mite_chan =
 577	    mite_request_channel(devpriv->mite,
 578				 devpriv->gpct_mite_ring[gpct_index]);
 579	if (mite_chan == NULL) {
 580		spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 581		comedi_error(dev,
 582			     "failed to reserve mite dma channel for counter.");
 583		return -EBUSY;
 584	}
 585	mite_chan->dir = direction;
 586	ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 587				mite_chan);
 588	ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 589	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 590	return 0;
 591}
 592
 593#endif /*  PCIDMA */
 594
 595static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 596{
 597#ifdef PCIDMA
 598	unsigned long flags;
 599
 600	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 601	BUG_ON(devpriv->cdo_mite_chan);
 602	devpriv->cdo_mite_chan =
 603	    mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 604	if (devpriv->cdo_mite_chan == NULL) {
 605		spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 606		comedi_error(dev,
 607			     "failed to reserve mite dma channel for correlated digital outut.");
 608		return -EBUSY;
 609	}
 610	devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 611	ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 612	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 613#endif /*  PCIDMA */
 614	return 0;
 615}
 616
 617static void ni_release_ai_mite_channel(struct comedi_device *dev)
 618{
 619#ifdef PCIDMA
 620	unsigned long flags;
 621
 622	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 623	if (devpriv->ai_mite_chan) {
 624		ni_set_ai_dma_channel(dev, -1);
 625		mite_release_channel(devpriv->ai_mite_chan);
 626		devpriv->ai_mite_chan = NULL;
 627	}
 628	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 629#endif /*  PCIDMA */
 630}
 631
 632static void ni_release_ao_mite_channel(struct comedi_device *dev)
 633{
 634#ifdef PCIDMA
 635	unsigned long flags;
 636
 637	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 638	if (devpriv->ao_mite_chan) {
 639		ni_set_ao_dma_channel(dev, -1);
 640		mite_release_channel(devpriv->ao_mite_chan);
 641		devpriv->ao_mite_chan = NULL;
 642	}
 643	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 644#endif /*  PCIDMA */
 645}
 646
 647void ni_release_gpct_mite_channel(struct comedi_device *dev,
 648				  unsigned gpct_index)
 649{
 650#ifdef PCIDMA
 651	unsigned long flags;
 652
 653	BUG_ON(gpct_index >= NUM_GPCT);
 654	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 655	if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 656		struct mite_channel *mite_chan =
 657		    devpriv->counter_dev->counters[gpct_index].mite_chan;
 658
 659		ni_set_gpct_dma_channel(dev, gpct_index, -1);
 660		ni_tio_set_mite_channel(&devpriv->
 661					counter_dev->counters[gpct_index],
 662					NULL);
 663		mite_release_channel(mite_chan);
 664	}
 665	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 666#endif /*  PCIDMA */
 667}
 668
 669static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 670{
 671#ifdef PCIDMA
 672	unsigned long flags;
 673
 674	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 675	if (devpriv->cdo_mite_chan) {
 676		ni_set_cdo_dma_channel(dev, -1);
 677		mite_release_channel(devpriv->cdo_mite_chan);
 678		devpriv->cdo_mite_chan = NULL;
 679	}
 680	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 681#endif /*  PCIDMA */
 682}
 683
 684/* e-series boards use the second irq signals to generate dma requests for their counters */
 685#ifdef PCIDMA
 686static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 687					  unsigned gpct_index, short enable)
 688{
 689	if (boardtype.reg_type & ni_reg_m_series_mask)
 690		return;
 691	switch (gpct_index) {
 692	case 0:
 693		if (enable) {
 694			devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
 695					    Second_IRQ_A_Enable_Register);
 696		} else {
 697			devpriv->stc_writew(dev, 0,
 698					    Second_IRQ_A_Enable_Register);
 699		}
 700		break;
 701	case 1:
 702		if (enable) {
 703			devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
 704					    Second_IRQ_B_Enable_Register);
 705		} else {
 706			devpriv->stc_writew(dev, 0,
 707					    Second_IRQ_B_Enable_Register);
 708		}
 709		break;
 710	default:
 711		BUG();
 712		break;
 713	}
 714}
 715#endif /*  PCIDMA */
 716
 717static void ni_clear_ai_fifo(struct comedi_device *dev)
 718{
 719	if (boardtype.reg_type == ni_reg_6143) {
 720		/*  Flush the 6143 data FIFO */
 721		ni_writel(0x10, AIFIFO_Control_6143);	/*  Flush fifo */
 722		ni_writel(0x00, AIFIFO_Control_6143);	/*  Flush fifo */
 723		while (ni_readl(AIFIFO_Status_6143) & 0x10) ;	/*  Wait for complete */
 724	} else {
 725		devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
 726		if (boardtype.reg_type == ni_reg_625x) {
 727			ni_writeb(0, M_Offset_Static_AI_Control(0));
 728			ni_writeb(1, M_Offset_Static_AI_Control(0));
 729#if 0
 730			/* the NI example code does 3 convert pulses for 625x boards,
 731			   but that appears to be wrong in practice. */
 732			devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 733					    AI_Command_1_Register);
 734			devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 735					    AI_Command_1_Register);
 736			devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 737					    AI_Command_1_Register);
 738#endif
 739		}
 740	}
 741}
 742
 743static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
 744{
 745	devpriv->stc_writew(dev, data >> 16, reg);
 746	devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 747}
 748
 749static uint32_t win_in2(struct comedi_device *dev, int reg)
 750{
 751	uint32_t bits;
 752	bits = devpriv->stc_readw(dev, reg) << 16;
 753	bits |= devpriv->stc_readw(dev, reg + 1);
 754	return bits;
 755}
 756
 757#define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
 758static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 759				  int addr)
 760{
 761	unsigned long flags;
 762
 763	spin_lock_irqsave(&devpriv->window_lock, flags);
 764	ni_writew(addr, AO_Window_Address_611x);
 765	ni_writew(data, AO_Window_Data_611x);
 766	spin_unlock_irqrestore(&devpriv->window_lock, flags);
 767}
 768
 769static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 770				  int addr)
 771{
 772	unsigned long flags;
 773
 774	spin_lock_irqsave(&devpriv->window_lock, flags);
 775	ni_writew(addr, AO_Window_Address_611x);
 776	ni_writel(data, AO_Window_Data_611x);
 777	spin_unlock_irqrestore(&devpriv->window_lock, flags);
 778}
 779
 780static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 781{
 782	unsigned long flags;
 783	unsigned short data;
 784
 785	spin_lock_irqsave(&devpriv->window_lock, flags);
 786	ni_writew(addr, AO_Window_Address_611x);
 787	data = ni_readw(AO_Window_Data_611x);
 788	spin_unlock_irqrestore(&devpriv->window_lock, flags);
 789	return data;
 790}
 791
 792/* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 793* share registers (such as Interrupt_A_Register) without interfering with
 794* each other.
 795*
 796* NOTE: the switch/case statements are optimized out for a constant argument
 797* so this is actually quite fast---  If you must wrap another function around this
 798* make it inline to avoid a large speed penalty.
 799*
 800* value should only be 1 or 0.
 801*/
 802static inline void ni_set_bits(struct comedi_device *dev, int reg,
 803			       unsigned bits, unsigned value)
 804{
 805	unsigned bit_values;
 806
 807	if (value)
 808		bit_values = bits;
 809	else
 810		bit_values = 0;
 811	ni_set_bitfield(dev, reg, bits, bit_values);
 812}
 813
 814static irqreturn_t ni_E_interrupt(int irq, void *d)
 815{
 816	struct comedi_device *dev = d;
 817	unsigned short a_status;
 818	unsigned short b_status;
 819	unsigned int ai_mite_status = 0;
 820	unsigned int ao_mite_status = 0;
 821	unsigned long flags;
 822#ifdef PCIDMA
 823	struct mite_struct *mite = devpriv->mite;
 824#endif
 825
 826	if (dev->attached == 0)
 827		return IRQ_NONE;
 828	smp_mb();		/*  make sure dev->attached is checked before handler does anything else. */
 829
 830	/*  lock to avoid race with comedi_poll */
 831	spin_lock_irqsave(&dev->spinlock, flags);
 832	a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 833	b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 834#ifdef PCIDMA
 835	if (mite) {
 836		unsigned long flags_too;
 837
 838		spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
 839		if (devpriv->ai_mite_chan) {
 840			ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
 841			if (ai_mite_status & CHSR_LINKC)
 842				writel(CHOR_CLRLC,
 843				       devpriv->mite->mite_io_addr +
 844				       MITE_CHOR(devpriv->
 845						 ai_mite_chan->channel));
 846		}
 847		if (devpriv->ao_mite_chan) {
 848			ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
 849			if (ao_mite_status & CHSR_LINKC)
 850				writel(CHOR_CLRLC,
 851				       mite->mite_io_addr +
 852				       MITE_CHOR(devpriv->
 853						 ao_mite_chan->channel));
 854		}
 855		spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
 856	}
 857#endif
 858	ack_a_interrupt(dev, a_status);
 859	ack_b_interrupt(dev, b_status);
 860	if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
 861		handle_a_interrupt(dev, a_status, ai_mite_status);
 862	if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
 863		handle_b_interrupt(dev, b_status, ao_mite_status);
 864	handle_gpct_interrupt(dev, 0);
 865	handle_gpct_interrupt(dev, 1);
 866	handle_cdio_interrupt(dev);
 867
 868	spin_unlock_irqrestore(&dev->spinlock, flags);
 869	return IRQ_HANDLED;
 870}
 871
 872#ifdef PCIDMA
 873static void ni_sync_ai_dma(struct comedi_device *dev)
 874{
 875	struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
 876	unsigned long flags;
 877
 878	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 879	if (devpriv->ai_mite_chan)
 880		mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 881	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 882}
 883
 884static void mite_handle_b_linkc(struct mite_struct *mite,
 885				struct comedi_device *dev)
 886{
 887	struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
 888	unsigned long flags;
 889
 890	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 891	if (devpriv->ao_mite_chan) {
 892		mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
 893	}
 894	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 895}
 896
 897static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 898{
 899	static const int timeout = 10000;
 900	int i;
 901	for (i = 0; i < timeout; i++) {
 902		unsigned short b_status;
 903
 904		b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 905		if (b_status & AO_FIFO_Half_Full_St)
 906			break;
 907		/* if we poll too often, the pci bus activity seems
 908		   to slow the dma transfer down */
 909		udelay(10);
 910	}
 911	if (i == timeout) {
 912		comedi_error(dev, "timed out waiting for dma load");
 913		return -EPIPE;
 914	}
 915	return 0;
 916}
 917
 918#endif /* PCIDMA */
 919static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
 920{
 921	if (devpriv->aimode == AIMODE_SCAN) {
 922#ifdef PCIDMA
 923		static const int timeout = 10;
 924		int i;
 925
 926		for (i = 0; i < timeout; i++) {
 927			ni_sync_ai_dma(dev);
 928			if ((s->async->events & COMEDI_CB_EOS))
 929				break;
 930			udelay(1);
 931		}
 932#else
 933		ni_handle_fifo_dregs(dev);
 934		s->async->events |= COMEDI_CB_EOS;
 935#endif
 936	}
 937	/* handle special case of single scan using AI_End_On_End_Of_Scan */
 938	if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
 939		shutdown_ai_command(dev);
 940	}
 941}
 942
 943static void shutdown_ai_command(struct comedi_device *dev)
 944{
 945	struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
 946
 947#ifdef PCIDMA
 948	ni_ai_drain_dma(dev);
 949#endif
 950	ni_handle_fifo_dregs(dev);
 951	get_last_sample_611x(dev);
 952	get_last_sample_6143(dev);
 953
 954	s->async->events |= COMEDI_CB_EOA;
 955}
 956
 957static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
 958{
 959	if (s->
 960	    async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
 961			     COMEDI_CB_EOA)) {
 962		switch (s - dev->subdevices) {
 963		case NI_AI_SUBDEV:
 964			ni_ai_reset(dev, s);
 965			break;
 966		case NI_AO_SUBDEV:
 967			ni_ao_reset(dev, s);
 968			break;
 969		case NI_GPCT0_SUBDEV:
 970		case NI_GPCT1_SUBDEV:
 971			ni_gpct_cancel(dev, s);
 972			break;
 973		case NI_DIO_SUBDEV:
 974			ni_cdio_cancel(dev, s);
 975			break;
 976		default:
 977			break;
 978		}
 979	}
 980	comedi_event(dev, s);
 981}
 982
 983static void handle_gpct_interrupt(struct comedi_device *dev,
 984				  unsigned short counter_index)
 985{
 986#ifdef PCIDMA
 987	struct comedi_subdevice *s =
 988	    dev->subdevices + NI_GPCT_SUBDEV(counter_index);
 989
 990	ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
 991				s);
 992	if (s->async->events)
 993		ni_event(dev, s);
 994#endif
 995}
 996
 997static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
 998{
 999	unsigned short ack = 0;
1000
1001	if (a_status & AI_SC_TC_St) {
1002		ack |= AI_SC_TC_Interrupt_Ack;
1003	}
1004	if (a_status & AI_START1_St) {
1005		ack |= AI_START1_Interrupt_Ack;
1006	}
1007	if (a_status & AI_START_St) {
1008		ack |= AI_START_Interrupt_Ack;
1009	}
1010	if (a_status & AI_STOP_St) {
1011		/* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1012		ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1013	}
1014	if (ack)
1015		devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1016}
1017
1018static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1019			       unsigned ai_mite_status)
1020{
1021	struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1022
1023	/* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1024	if (s->type == COMEDI_SUBD_UNUSED)
1025		return;
1026
1027#ifdef DEBUG_INTERRUPT
1028	printk
1029	    ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1030	     status, ai_mite_status);
1031	ni_mio_print_status_a(status);
1032#endif
1033#ifdef PCIDMA
1034	if (ai_mite_status & CHSR_LINKC) {
1035		ni_sync_ai_dma(dev);
1036	}
1037
1038	if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1039			       CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1040			       CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1041		printk
1042		    ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1043		     ai_mite_status);
1044		/* mite_print_chsr(ai_mite_status); */
1045		s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1046		/* disable_irq(dev->irq); */
1047	}
1048#endif
1049
1050	/* test for all uncommon interrupt events at the same time */
1051	if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1052		      AI_SC_TC_St | AI_START1_St)) {
1053		if (status == 0xffff) {
1054			printk
1055			    ("ni_mio_common: a_status=0xffff.  Card removed?\n");
1056			/* we probably aren't even running a command now,
1057			 * so it's a good idea to be careful. */
1058			if (comedi_get_subdevice_runflags(s) & SRF_RUNNING) {
1059				s->async->events |=
1060				    COMEDI_CB_ERROR | COMEDI_CB_EOA;
1061				ni_event(dev, s);
1062			}
1063			return;
1064		}
1065		if (status & (AI_Overrun_St | AI_Overflow_St |
1066			      AI_SC_TC_Error_St)) {
1067			printk("ni_mio_common: ai error a_status=%04x\n",
1068			       status);
1069			ni_mio_print_status_a(status);
1070
1071			shutdown_ai_command(dev);
1072
1073			s->async->events |= COMEDI_CB_ERROR;
1074			if (status & (AI_Overrun_St | AI_Overflow_St))
1075				s->async->events |= COMEDI_CB_OVERFLOW;
1076
1077			ni_event(dev, s);
1078
1079			return;
1080		}
1081		if (status & AI_SC_TC_St) {
1082#ifdef DEBUG_INTERRUPT
1083			printk("ni_mio_common: SC_TC interrupt\n");
1084#endif
1085			if (!devpriv->ai_continuous) {
1086				shutdown_ai_command(dev);
1087			}
1088		}
1089	}
1090#ifndef PCIDMA
1091	if (status & AI_FIFO_Half_Full_St) {
1092		int i;
1093		static const int timeout = 10;
1094		/* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1095		 *fail to get the fifo less than half full, so loop to be sure.*/
1096		for (i = 0; i < timeout; ++i) {
1097			ni_handle_fifo_half_full(dev);
1098			if ((devpriv->stc_readw(dev,
1099						AI_Status_1_Register) &
1100			     AI_FIFO_Half_Full_St) == 0)
1101				break;
1102		}
1103	}
1104#endif /*  !PCIDMA */
1105
1106	if ((status & AI_STOP_St)) {
1107		ni_handle_eos(dev, s);
1108	}
1109
1110	ni_event(dev, s);
1111
1112#ifdef DEBUG_INTERRUPT
1113	status = devpriv->stc_readw(dev, AI_Status_1_Register);
1114	if (status & Interrupt_A_St) {
1115		printk
1116		    ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1117		     status);
1118	}
1119#endif
1120}
1121
1122static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1123{
1124	unsigned short ack = 0;
1125	if (b_status & AO_BC_TC_St) {
1126		ack |= AO_BC_TC_Interrupt_Ack;
1127	}
1128	if (b_status & AO_Overrun_St) {
1129		ack |= AO_Error_Interrupt_Ack;
1130	}
1131	if (b_status & AO_START_St) {
1132		ack |= AO_START_Interrupt_Ack;
1133	}
1134	if (b_status & AO_START1_St) {
1135		ack |= AO_START1_Interrupt_Ack;
1136	}
1137	if (b_status & AO_UC_TC_St) {
1138		ack |= AO_UC_TC_Interrupt_Ack;
1139	}
1140	if (b_status & AO_UI2_TC_St) {
1141		ack |= AO_UI2_TC_Interrupt_Ack;
1142	}
1143	if (b_status & AO_UPDATE_St) {
1144		ack |= AO_UPDATE_Interrupt_Ack;
1145	}
1146	if (ack)
1147		devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1148}
1149
1150static void handle_b_interrupt(struct comedi_device *dev,
1151			       unsigned short b_status, unsigned ao_mite_status)
1152{
1153	struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1154	/* unsigned short ack=0; */
1155#ifdef DEBUG_INTERRUPT
1156	printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1157	       b_status, ao_mite_status);
1158	ni_mio_print_status_b(b_status);
1159#endif
1160
1161#ifdef PCIDMA
1162	/* Currently, mite.c requires us to handle LINKC */
1163	if (ao_mite_status & CHSR_LINKC) {
1164		mite_handle_b_linkc(devpriv->mite, dev);
1165	}
1166
1167	if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1168			       CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1169			       CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1170		printk
1171		    ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1172		     ao_mite_status);
1173		/* mite_print_chsr(ao_mite_status); */
1174		s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1175	}
1176#endif
1177
1178	if (b_status == 0xffff)
1179		return;
1180	if (b_status & AO_Overrun_St) {
1181		printk
1182		    ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1183		     b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1184		s->async->events |= COMEDI_CB_OVERFLOW;
1185	}
1186
1187	if (b_status & AO_BC_TC_St) {
1188		MDPRINTK
1189		    ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1190		     b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1191		s->async->events |= COMEDI_CB_EOA;
1192	}
1193#ifndef PCIDMA
1194	if (b_status & AO_FIFO_Request_St) {
1195		int ret;
1196
1197		ret = ni_ao_fifo_half_empty(dev, s);
1198		if (!ret) {
1199			printk("ni_mio_common: AO buffer underrun\n");
1200			ni_set_bits(dev, Interrupt_B_Enable_Register,
1201				    AO_FIFO_Interrupt_Enable |
1202				    AO_Error_Interrupt_Enable, 0);
1203			s->async->events |= COMEDI_CB_OVERFLOW;
1204		}
1205	}
1206#endif
1207
1208	ni_event(dev, s);
1209}
1210
1211#ifdef DEBUG_STATUS_A
1212static const char *const status_a_strings[] = {
1213	"passthru0", "fifo", "G0_gate", "G0_TC",
1214	"stop", "start", "sc_tc", "start1",
1215	"start2", "sc_tc_error", "overflow", "overrun",
1216	"fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1217};
1218
1219static void ni_mio_print_status_a(int status)
1220{
1221	int i;
1222
1223	printk("A status:");
1224	for (i = 15; i >= 0; i--) {
1225		if (status & (1 << i)) {
1226			printk(" %s", status_a_strings[i]);
1227		}
1228	}
1229	printk("\n");
1230}
1231#endif
1232
1233#ifdef DEBUG_STATUS_B
1234static const char *const status_b_strings[] = {
1235	"passthru1", "fifo", "G1_gate", "G1_TC",
1236	"UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1237	"start1", "overrun", "start", "bc_tc_error",
1238	"fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1239};
1240
1241static void ni_mio_print_status_b(int status)
1242{
1243	int i;
1244
1245	printk("B status:");
1246	for (i = 15; i >= 0; i--) {
1247		if (status & (1 << i)) {
1248			printk(" %s", status_b_strings[i]);
1249		}
1250	}
1251	printk("\n");
1252}
1253#endif
1254
1255#ifndef PCIDMA
1256
1257static void ni_ao_fifo_load(struct comedi_device *dev,
1258			    struct comedi_subdevice *s, int n)
1259{
1260	struct comedi_async *async = s->async;
1261	struct comedi_cmd *cmd = &async->cmd;
1262	int chan;
1263	int i;
1264	short d;
1265	u32 packed_data;
1266	int range;
1267	int err = 1;
1268
1269	chan = async->cur_chan;
1270	for (i = 0; i < n; i++) {
1271		err &= comedi_buf_get(async, &d);
1272		if (err == 0)
1273			break;
1274
1275		range = CR_RANGE(cmd->chanlist[chan]);
1276
1277		if (boardtype.reg_type & ni_reg_6xxx_mask) {
1278			packed_data = d & 0xffff;
1279			/* 6711 only has 16 bit wide ao fifo */
1280			if (boardtype.reg_type != ni_reg_6711) {
1281				err &= comedi_buf_get(async, &d);
1282				if (err == 0)
1283					break;
1284				chan++;
1285				i++;
1286				packed_data |= (d << 16) & 0xffff0000;
1287			}
1288			ni_writel(packed_data, DAC_FIFO_Data_611x);
1289		} else {
1290			ni_writew(d, DAC_FIFO_Data);
1291		}
1292		chan++;
1293		chan %= cmd->chanlist_len;
1294	}
1295	async->cur_chan = chan;
1296	if (err == 0) {
1297		async->events |= COMEDI_CB_OVERFLOW;
1298	}
1299}
1300
1301/*
1302 *  There's a small problem if the FIFO gets really low and we
1303 *  don't have the data to fill it.  Basically, if after we fill
1304 *  the FIFO with all the data available, the FIFO is _still_
1305 *  less than half full, we never clear the interrupt.  If the
1306 *  IRQ is in edge mode, we never get another interrupt, because
1307 *  this one wasn't cleared.  If in level mode, we get flooded
1308 *  with interrupts that we can't fulfill, because nothing ever
1309 *  gets put into the buffer.
1310 *
1311 *  This kind of situation is recoverable, but it is easier to
1312 *  just pretend we had a FIFO underrun, since there is a good
1313 *  chance it will happen anyway.  This is _not_ the case for
1314 *  RT code, as RT code might purposely be running close to the
1315 *  metal.  Needs to be fixed eventually.
1316 */
1317static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1318				 struct comedi_subdevice *s)
1319{
1320	int n;
1321
1322	n = comedi_buf_read_n_available(s->async);
1323	if (n == 0) {
1324		s->async->events |= COMEDI_CB_OVERFLOW;
1325		return 0;
1326	}
1327
1328	n /= sizeof(short);
1329	if (n > boardtype.ao_fifo_depth / 2)
1330		n = boardtype.ao_fifo_depth / 2;
1331
1332	ni_ao_fifo_load(dev, s, n);
1333
1334	s->async->events |= COMEDI_CB_BLOCK;
1335
1336	return 1;
1337}
1338
1339static int ni_ao_prep_fifo(struct comedi_device *dev,
1340			   struct comedi_subdevice *s)
1341{
1342	int n;
1343
1344	/* reset fifo */
1345	devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1346	if (boardtype.reg_type & ni_reg_6xxx_mask)
1347		ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1348
1349	/* load some data */
1350	n = comedi_buf_read_n_available(s->async);
1351	if (n == 0)
1352		return 0;
1353
1354	n /= sizeof(short);
1355	if (n > boardtype.ao_fifo_depth)
1356		n = boardtype.ao_fifo_depth;
1357
1358	ni_ao_fifo_load(dev, s, n);
1359
1360	return n;
1361}
1362
1363static void ni_ai_fifo_read(struct comedi_device *dev,
1364			    struct comedi_subdevice *s, int n)
1365{
1366	struct comedi_async *async = s->async;
1367	int i;
1368
1369	if (boardtype.reg_type == ni_reg_611x) {
1370		short data[2];
1371		u32 dl;
1372
1373		for (i = 0; i < n / 2; i++) {
1374			dl = ni_readl(ADC_FIFO_Data_611x);
1375			/* This may get the hi/lo data in the wrong order */
1376			data[0] = (dl >> 16) & 0xffff;
1377			data[1] = dl & 0xffff;
1378			cfc_write_array_to_buffer(s, data, sizeof(data));
1379		}
1380		/* Check if there's a single sample stuck in the FIFO */
1381		if (n % 2) {
1382			dl = ni_readl(ADC_FIFO_Data_611x);
1383			data[0] = dl & 0xffff;
1384			cfc_write_to_buffer(s, data[0]);
1385		}
1386	} else if (boardtype.reg_type == ni_reg_6143) {
1387		short data[2];
1388		u32 dl;
1389
1390		/*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1391		for (i = 0; i < n / 2; i++) {
1392			dl = ni_readl(AIFIFO_Data_6143);
1393
1394			data[0] = (dl >> 16) & 0xffff;
1395			data[1] = dl & 0xffff;
1396			cfc_write_array_to_buffer(s, data, sizeof(data));
1397		}
1398		if (n % 2) {
1399			/* Assume there is a single sample stuck in the FIFO */
1400			ni_writel(0x01, AIFIFO_Control_6143);	/*  Get stranded sample into FIFO */
1401			dl = ni_readl(AIFIFO_Data_6143);
1402			data[0] = (dl >> 16) & 0xffff;
1403			cfc_write_to_buffer(s, data[0]);
1404		}
1405	} else {
1406		if (n > sizeof(devpriv->ai_fifo_buffer) /
1407		    sizeof(devpriv->ai_fifo_buffer[0])) {
1408			comedi_error(dev, "bug! ai_fifo_buffer too small");
1409			async->events |= COMEDI_CB_ERROR;
1410			return;
1411		}
1412		for (i = 0; i < n; i++) {
1413			devpriv->ai_fifo_buffer[i] =
1414			    ni_readw(ADC_FIFO_Data_Register);
1415		}
1416		cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1417					  n *
1418					  sizeof(devpriv->ai_fifo_buffer[0]));
1419	}
1420}
1421
1422static void ni_handle_fifo_half_full(struct comedi_device *dev)
1423{
1424	int n;
1425	struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1426
1427	n = boardtype.ai_fifo_depth / 2;
1428
1429	ni_ai_fifo_read(dev, s, n);
1430}
1431#endif
1432
1433#ifdef PCIDMA
1434static int ni_ai_drain_dma(struct comedi_device *dev)
1435{
1436	int i;
1437	static const int timeout = 10000;
1438	unsigned long flags;
1439	int retval = 0;
1440
1441	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1442	if (devpriv->ai_mite_chan) {
1443		for (i = 0; i < timeout; i++) {
1444			if ((devpriv->stc_readw(dev,
1445						AI_Status_1_Register) &
1446			     AI_FIFO_Empty_St)
1447			    && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1448			    0)
1449				break;
1450			udelay(5);
1451		}
1452		if (i == timeout) {
1453			printk("ni_mio_common: wait for dma drain timed out\n");
1454			printk
1455			    ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1456			     mite_bytes_in_transit(devpriv->ai_mite_chan),
1457			     devpriv->stc_readw(dev, AI_Status_1_Register));
1458			retval = -1;
1459		}
1460	}
1461	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1462
1463	ni_sync_ai_dma(dev);
1464
1465	return retval;
1466}
1467#endif
1468/*
1469   Empties the AI fifo
1470*/
1471static void ni_handle_fifo_dregs(struct comedi_device *dev)
1472{
1473	struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1474	short data[2];
1475	u32 dl;
1476	short fifo_empty;
1477	int i;
1478
1479	if (boardtype.reg_type == ni_reg_611x) {
1480		while ((devpriv->stc_readw(dev,
1481					   AI_Status_1_Register) &
1482			AI_FIFO_Empty_St) == 0) {
1483			dl = ni_readl(ADC_FIFO_Data_611x);
1484
1485			/* This may get the hi/lo data in the wrong order */
1486			data[0] = (dl >> 16);
1487			data[1] = (dl & 0xffff);
1488			cfc_write_array_to_buffer(s, data, sizeof(data));
1489		}
1490	} else if (boardtype.reg_type == ni_reg_6143) {
1491		i = 0;
1492		while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1493			dl = ni_readl(AIFIFO_Data_6143);
1494
1495			/* This may get the hi/lo data in the wrong order */
1496			data[0] = (dl >> 16);
1497			data[1] = (dl & 0xffff);
1498			cfc_write_array_to_buffer(s, data, sizeof(data));
1499			i += 2;
1500		}
1501		/*  Check if stranded sample is present */
1502		if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1503			ni_writel(0x01, AIFIFO_Control_6143);	/*  Get stranded sample into FIFO */
1504			dl = ni_readl(AIFIFO_Data_6143);
1505			data[0] = (dl >> 16) & 0xffff;
1506			cfc_write_to_buffer(s, data[0]);
1507		}
1508
1509	} else {
1510		fifo_empty =
1511		    devpriv->stc_readw(dev,
1512				       AI_Status_1_Register) & AI_FIFO_Empty_St;
1513		while (fifo_empty == 0) {
1514			for (i = 0;
1515			     i <
1516			     sizeof(devpriv->ai_fifo_buffer) /
1517			     sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1518				fifo_empty =
1519				    devpriv->stc_readw(dev,
1520						       AI_Status_1_Register) &
1521				    AI_FIFO_Empty_St;
1522				if (fifo_empty)
1523					break;
1524				devpriv->ai_fifo_buffer[i] =
1525				    ni_readw(ADC_FIFO_Data_Register);
1526			}
1527			cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1528						  i *
1529						  sizeof(devpriv->
1530							 ai_fifo_buffer[0]));
1531		}
1532	}
1533}
1534
1535static void get_last_sample_611x(struct comedi_device *dev)
1536{
1537	struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1538	short data;
1539	u32 dl;
1540
1541	if (boardtype.reg_type != ni_reg_611x)
1542		return;
1543
1544	/* Check if there's a single sample stuck in the FIFO */
1545	if (ni_readb(XXX_Status) & 0x80) {
1546		dl = ni_readl(ADC_FIFO_Data_611x);
1547		data = (dl & 0xffff);
1548		cfc_write_to_buffer(s, data);
1549	}
1550}
1551
1552static void get_last_sample_6143(struct comedi_device *dev)
1553{
1554	struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1555	short data;
1556	u32 dl;
1557
1558	if (boardtype.reg_type != ni_reg_6143)
1559		return;
1560
1561	/* Check if there's a single sample stuck in the FIFO */
1562	if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1563		ni_writel(0x01, AIFIFO_Control_6143);	/*  Get stranded sample into FIFO */
1564		dl = ni_readl(AIFIFO_Data_6143);
1565
1566		/* This may get the hi/lo data in the wrong order */
1567		data = (dl >> 16) & 0xffff;
1568		cfc_write_to_buffer(s, data);
1569	}
1570}
1571
1572static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1573			void *data, unsigned int num_bytes,
1574			unsigned int chan_index)
1575{
1576	struct comedi_async *async = s->async;
1577	unsigned int i;
1578	unsigned int length = num_bytes / bytes_per_sample(s);
1579	short *array = data;
1580	unsigned int *larray = data;
1581	for (i = 0; i < length; i++) {
1582#ifdef PCIDMA
1583		if (s->subdev_flags & SDF_LSAMPL)
1584			larray[i] = le32_to_cpu(larray[i]);
1585		else
1586			array[i] = le16_to_cpu(array[i]);
1587#endif
1588		if (s->subdev_flags & SDF_LSAMPL)
1589			larray[i] += devpriv->ai_offset[chan_index];
1590		else
1591			array[i] += devpriv->ai_offset[chan_index];
1592		chan_index++;
1593		chan_index %= async->cmd.chanlist_len;
1594	}
1595}
1596
1597#ifdef PCIDMA
1598
1599static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1600{
1601	struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1602	int retval;
1603	unsigned long flags;
1604
1605	retval = ni_request_ai_mite_channel(dev);
1606	if (retval)
1607		return retval;
1608/* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1609
1610	/* write alloc the entire buffer */
1611	comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1612
1613	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1614	if (devpriv->ai_mite_chan == NULL) {
1615		spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1616		return -EIO;
1617	}
1618
1619	switch (boardtype.reg_type) {
1620	case ni_reg_611x:
1621	case ni_reg_6143:
1622		mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1623		break;
1624	case ni_reg_628x:
1625		mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1626		break;
1627	default:
1628		mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1629		break;
1630	}
1631	/*start the MITE */
1632	mite_dma_arm(devpriv->ai_mite_chan);
1633	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1634
1635	return 0;
1636}
1637
1638static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1639{
1640	struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1641	int retval;
1642	unsigned long flags;
1643
1644	retval = ni_request_ao_mite_channel(dev);
1645	if (retval)
1646		return retval;
1647
1648	/* read alloc the entire buffer */
1649	comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1650
1651	spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1652	if (devpriv->ao_mite_chan) {
1653		if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) {
1654			mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1655		} else {
1656			/* doing 32 instead of 16 bit wide transfers from memory
1657			   makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1658			mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1659		}
1660		mite_dma_arm(devpriv->ao_mite_chan);
1661	} else
1662		retval = -EIO;
1663	spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1664
1665	return retval;
1666}
1667
1668#endif /*  PCIDMA */
1669
1670/*
1671   used for both cancel ioctl and board initialization
1672
1673   this is pretty harsh for a cancel, but it works...
1674 */
1675
1676static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1677{
1678	ni_release_ai_mite_channel(dev);
1679	/* ai configuration */
1680	devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1681			    Joint_Reset_Register);
1682
1683	ni_set_bits(dev, Interrupt_A_Enable_Register,
1684		    AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1685		    AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1686		    AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1687		    AI_FIFO_Interrupt_Enable, 0);
1688
1689	ni_clear_ai_fifo(dev);
1690
1691	if (boardtype.reg_type != ni_reg_6143)
1692		ni_writeb(0, Misc_Command);
1693
1694	devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register);	/* reset pulses */
1695	devpriv->stc_writew(dev,
1696			    AI_Start_Stop | AI_Mode_1_Reserved
1697			    /*| AI_Trigger_Once */ ,
1698			    AI_Mode_1_Register);
1699	devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1700	/* generate FIFO interrupts on non-empty */
1701	devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1702	if (boardtype.reg_type == ni_reg_611x) {
1703		devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1704				    AI_SOC_Polarity |
1705				    AI_LOCALMUX_CLK_Pulse_Width,
1706				    AI_Personal_Register);
1707		devpriv->stc_writew(dev,
1708				    AI_SCAN_IN_PROG_Output_Select(3) |
1709				    AI_EXTMUX_CLK_Output_Select(0) |
1710				    AI_LOCALMUX_CLK_Output_Select(2) |
1711				    AI_SC_TC_Output_Select(3) |
1712				    AI_CONVERT_Output_Select
1713				    (AI_CONVERT_Output_Enable_High),
1714				    AI_Output_Control_Register);
1715	} else if (boardtype.reg_type == ni_reg_6143) {
1716		devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1717				    AI_SOC_Polarity |
1718				    AI_LOCALMUX_CLK_Pulse_Width,
1719				    AI_Personal_Register);
1720		devpriv->stc_writew(dev,
1721				    AI_SCAN_IN_PROG_Output_Select(3) |
1722				    AI_EXTMUX_CLK_Output_Select(0) |
1723				    AI_LOCALMUX_CLK_Output_Select(2) |
1724				    AI_SC_TC_Output_Select(3) |
1725				    AI_CONVERT_Output_Select
1726				    (AI_CONVERT_Output_Enable_Low),
1727				    AI_Output_Control_Register);
1728	} else {
1729		unsigned ai_output_control_bits;
1730		devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1731				    AI_SOC_Polarity |
1732				    AI_CONVERT_Pulse_Width |
1733				    AI_LOCALMUX_CLK_Pulse_Width,
1734				    AI_Personal_Register);
1735		ai_output_control_bits =
1736		    AI_SCAN_IN_PROG_Output_Select(3) |
1737		    AI_EXTMUX_CLK_Output_Select(0) |
1738		    AI_LOCALMUX_CLK_Output_Select(2) |
1739		    AI_SC_TC_Output_Select(3);
1740		if (boardtype.reg_type == ni_reg_622x)
1741			ai_output_control_bits |=
1742			    AI_CONVERT_Output_Select
1743			    (AI_CONVERT_Output_Enable_High);
1744		else
1745			ai_output_control_bits |=
1746			    AI_CONVERT_Output_Select
1747			    (AI_CONVERT_Output_Enable_Low);
1748		devpriv->stc_writew(dev, ai_output_control_bits,
1749				    AI_Output_Control_Register);
1750	}
1751	/* the following registers should not be changed, because there
1752	 * are no backup registers in devpriv.  If you want to chang…

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