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/drivers/staging/brcm80211/brcmsmac/phy/phy_int.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C Header | 1235 lines | 1027 code | 193 blank | 15 comment | 21 complexity | 0f838433f590c2e72aad6509fe5a41ed MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
   1/*
   2 * Copyright (c) 2010 Broadcom Corporation
   3 *
   4 * Permission to use, copy, modify, and/or distribute this software for any
   5 * purpose with or without fee is hereby granted, provided that the above
   6 * copyright notice and this permission notice appear in all copies.
   7 *
   8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15 */
  16
  17#ifndef _BRCM_PHY_INT_H_
  18#define _BRCM_PHY_INT_H_
  19
  20#include <types.h>
  21#include <brcmu_utils.h>
  22#include <brcmu_wifi.h>
  23
  24#define	PHY_VERSION			{ 1, 82, 8, 0 }
  25
  26#define PHYHAL_ERROR	0x0001
  27#define PHYHAL_TRACE	0x0002
  28#define PHYHAL_INFORM	0x0004
  29
  30extern u32 phyhal_msg_level;
  31
  32#define PHY_INFORM_ON()		(phyhal_msg_level & PHYHAL_INFORM)
  33#define PHY_THERMAL_ON()	(phyhal_msg_level & PHYHAL_THERMAL)
  34#define PHY_CAL_ON()		(phyhal_msg_level & PHYHAL_CAL)
  35
  36#ifdef BOARD_TYPE
  37#define BOARDTYPE(_type) BOARD_TYPE
  38#else
  39#define BOARDTYPE(_type) _type
  40#endif
  41
  42#define LCNXN_BASEREV		16
  43
  44struct brcms_phy_srom_fem {
  45	u8 tssipos;		/* TSSI positive slope, 1: positive, 0: negative */
  46	u8 extpagain;	/* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */
  47	u8 pdetrange;	/* support 32 combinations of different Pdet dynamic ranges */
  48	u8 triso;		/* TR switch isolation */
  49	u8 antswctrllut;	/* antswctrl lookup table configuration: 32 possible choices */
  50};
  51
  52typedef void (*initfn_t) (struct brcms_phy *);
  53typedef void (*chansetfn_t) (struct brcms_phy *, chanspec_t);
  54typedef int (*longtrnfn_t) (struct brcms_phy *, int);
  55typedef void (*txiqccgetfn_t) (struct brcms_phy *, u16 *, u16 *);
  56typedef void (*txiqccsetfn_t) (struct brcms_phy *, u16, u16);
  57typedef u16(*txloccgetfn_t) (struct brcms_phy *);
  58typedef void (*radioloftgetfn_t) (struct brcms_phy *, u8 *, u8 *, u8 *,
  59				  u8 *);
  60typedef s32(*rxsigpwrfn_t) (struct brcms_phy *, s32);
  61typedef void (*detachfn_t) (struct brcms_phy *);
  62
  63#undef ISNPHY
  64#undef ISLCNPHY
  65#define ISNPHY(pi)	PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
  66#define ISLCNPHY(pi)	PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
  67
  68#define ISPHY_11N_CAP(pi)	(ISNPHY(pi) || ISLCNPHY(pi))
  69
  70#define IS20MHZ(pi)	((pi)->bw == WL_CHANSPEC_BW_20)
  71#define IS40MHZ(pi)	((pi)->bw == WL_CHANSPEC_BW_40)
  72
  73#define PHY_GET_RFATTN(rfgain)	((rfgain) & 0x0f)
  74#define PHY_GET_PADMIX(rfgain)	(((rfgain) & 0x10) >> 4)
  75#define PHY_GET_RFGAINID(rfattn, padmix, width)	((rfattn) + ((padmix)*(width)))
  76#define PHY_SAT(x, n)		((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \
  77				((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x)))
  78#define PHY_SHIFT_ROUND(x, n)	((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n))
  79#define PHY_HW_ROUND(x, s)		((x >> s) + ((x >> (s-1)) & (s != 0)))
  80
  81#define CH_5G_GROUP	3
  82#define A_LOW_CHANS	0
  83#define A_MID_CHANS	1
  84#define A_HIGH_CHANS	2
  85#define CH_2G_GROUP	1
  86#define G_ALL_CHANS	0
  87
  88#define FIRST_REF5_CHANNUM	149
  89#define LAST_REF5_CHANNUM	165
  90#define	FIRST_5G_CHAN		14
  91#define	LAST_5G_CHAN		50
  92#define	FIRST_MID_5G_CHAN	14
  93#define	LAST_MID_5G_CHAN	35
  94#define	FIRST_HIGH_5G_CHAN	36
  95#define	LAST_HIGH_5G_CHAN	41
  96#define	FIRST_LOW_5G_CHAN	42
  97#define	LAST_LOW_5G_CHAN	50
  98
  99#define BASE_LOW_5G_CHAN	4900
 100#define BASE_MID_5G_CHAN	5100
 101#define BASE_HIGH_5G_CHAN	5500
 102
 103#define CHAN5G_FREQ(chan)  (5000 + chan*5)
 104#define CHAN2G_FREQ(chan)  (2407 + chan*5)
 105
 106#define TXP_FIRST_CCK		0
 107#define TXP_LAST_CCK		3
 108#define TXP_FIRST_OFDM		4
 109#define TXP_LAST_OFDM		11
 110#define TXP_FIRST_OFDM_20_CDD	12
 111#define TXP_LAST_OFDM_20_CDD	19
 112#define TXP_FIRST_MCS_20_SISO	20
 113#define TXP_LAST_MCS_20_SISO	27
 114#define TXP_FIRST_MCS_20_CDD	28
 115#define TXP_LAST_MCS_20_CDD	35
 116#define TXP_FIRST_MCS_20_STBC	36
 117#define TXP_LAST_MCS_20_STBC	43
 118#define TXP_FIRST_MCS_20_SDM	44
 119#define TXP_LAST_MCS_20_SDM	51
 120#define TXP_FIRST_OFDM_40_SISO	52
 121#define TXP_LAST_OFDM_40_SISO	59
 122#define TXP_FIRST_OFDM_40_CDD	60
 123#define TXP_LAST_OFDM_40_CDD	67
 124#define TXP_FIRST_MCS_40_SISO	68
 125#define TXP_LAST_MCS_40_SISO	75
 126#define TXP_FIRST_MCS_40_CDD	76
 127#define TXP_LAST_MCS_40_CDD	83
 128#define TXP_FIRST_MCS_40_STBC	84
 129#define TXP_LAST_MCS_40_STBC	91
 130#define TXP_FIRST_MCS_40_SDM	92
 131#define TXP_LAST_MCS_40_SDM	99
 132#define TXP_MCS_32	        100
 133#define TXP_NUM_RATES		101
 134#define ADJ_PWR_TBL_LEN		84
 135
 136#define TXP_FIRST_SISO_MCS_20	20
 137#define TXP_LAST_SISO_MCS_20	27
 138
 139#define PHY_CORE_NUM_1	1
 140#define PHY_CORE_NUM_2	2
 141#define PHY_CORE_NUM_3	3
 142#define PHY_CORE_NUM_4	4
 143#define PHY_CORE_MAX	PHY_CORE_NUM_4
 144#define PHY_CORE_0	0
 145#define PHY_CORE_1	1
 146#define PHY_CORE_2	2
 147#define PHY_CORE_3	3
 148
 149#define MA_WINDOW_SZ		8
 150
 151#define PHY_NOISE_SAMPLE_MON		1
 152#define PHY_NOISE_SAMPLE_EXTERNAL	2
 153#define PHY_NOISE_WINDOW_SZ	16
 154#define PHY_NOISE_GLITCH_INIT_MA 10
 155#define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10
 156#define PHY_NOISE_STATE_MON		0x1
 157#define PHY_NOISE_STATE_EXTERNAL	0x2
 158#define PHY_NOISE_SAMPLE_LOG_NUM_NPHY	10
 159#define PHY_NOISE_SAMPLE_LOG_NUM_UCODE	9
 160
 161#define PHY_NOISE_OFFSETFACT_4322  (-103)
 162#define PHY_NOISE_MA_WINDOW_SZ	2
 163
 164#define	PHY_RSSI_TABLE_SIZE	64
 165#define RSSI_ANT_MERGE_MAX	0
 166#define RSSI_ANT_MERGE_MIN	1
 167#define RSSI_ANT_MERGE_AVG	2
 168
 169#define	PHY_TSSI_TABLE_SIZE	64
 170#define	APHY_TSSI_TABLE_SIZE	256
 171#define	TX_GAIN_TABLE_LENGTH	64
 172#define	DEFAULT_11A_TXP_IDX	24
 173#define NUM_TSSI_FRAMES        4
 174#define	NULL_TSSI		0x7f
 175#define	NULL_TSSI_W		0x7f7f
 176
 177#define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64
 178
 179#define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9
 180
 181#define PHY_TXPWR_MIN		10
 182#define PHY_TXPWR_MIN_NPHY	8
 183#define RADIOPWR_OVERRIDE_DEF	(-1)
 184
 185#define PWRTBL_NUM_COEFF	3
 186
 187#define SPURAVOID_DISABLE	0
 188#define SPURAVOID_AUTO		1
 189#define SPURAVOID_FORCEON	2
 190#define SPURAVOID_FORCEON2	3
 191
 192#define PHY_SW_TIMER_FAST		15
 193#define PHY_SW_TIMER_SLOW		60
 194#define PHY_SW_TIMER_GLACIAL	120
 195
 196#define PHY_PERICAL_AUTO	0
 197#define PHY_PERICAL_FULL	1
 198#define PHY_PERICAL_PARTIAL	2
 199
 200#define PHY_PERICAL_NODELAY	0
 201#define PHY_PERICAL_INIT_DELAY	5
 202#define PHY_PERICAL_ASSOC_DELAY	5
 203#define PHY_PERICAL_WDOG_DELAY	5
 204
 205#define MPHASE_TXCAL_NUMCMDS	2
 206#define PHY_PERICAL_MPHASE_PENDING(pi)	(pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
 207
 208enum {
 209	MPHASE_CAL_STATE_IDLE = 0,
 210	MPHASE_CAL_STATE_INIT = 1,
 211	MPHASE_CAL_STATE_TXPHASE0,
 212	MPHASE_CAL_STATE_TXPHASE1,
 213	MPHASE_CAL_STATE_TXPHASE2,
 214	MPHASE_CAL_STATE_TXPHASE3,
 215	MPHASE_CAL_STATE_TXPHASE4,
 216	MPHASE_CAL_STATE_TXPHASE5,
 217	MPHASE_CAL_STATE_PAPDCAL,
 218	MPHASE_CAL_STATE_RXCAL,
 219	MPHASE_CAL_STATE_RSSICAL,
 220	MPHASE_CAL_STATE_IDLETSSI
 221};
 222
 223enum phy_cal_mode {
 224	CAL_FULL,
 225	CAL_RECAL,
 226	CAL_CURRECAL,
 227	CAL_DIGCAL,
 228	CAL_GCTRL,
 229	CAL_SOFT,
 230	CAL_DIGLO
 231};
 232
 233#define RDR_NTIERS  1
 234#define RDR_TIER_SIZE 64
 235#define RDR_LIST_SIZE (512/3)
 236#define RDR_EPOCH_SIZE 40
 237#define RDR_NANTENNAS 2
 238#define RDR_NTIER_SIZE  RDR_LIST_SIZE
 239#define RDR_LP_BUFFER_SIZE 64
 240#define LP_LEN_HIS_SIZE 10
 241
 242#define STATIC_NUM_RF 32
 243#define STATIC_NUM_BB 9
 244
 245#define BB_MULT_MASK		0x0000ffff
 246#define BB_MULT_VALID_MASK	0x80000000
 247
 248#define CORDIC_AG	39797
 249#define	CORDIC_NI	18
 250#define	FIXED(X)	((s32)((X) << 16))
 251#define	FLOAT(X)	(((X) >= 0) ? ((((X) >> 15) + 1) >> 1) : -((((-(X)) >> 15) + 1) >> 1))
 252
 253#define PHY_CHAIN_TX_DISABLE_TEMP	115
 254#define PHY_HYSTERESIS_DELTATEMP	5
 255
 256#define PHY_BITSCNT(x)	brcmu_bitcount((u8 *)&(x), sizeof(u8))
 257
 258#define MOD_PHY_REG(pi, phy_type, reg_name, field, value) \
 259	mod_phy_reg(pi, phy_type##_##reg_name, phy_type##_##reg_name##_##field##_MASK, \
 260	(value) << phy_type##_##reg_name##_##field##_##SHIFT);
 261#define READ_PHY_REG(pi, phy_type, reg_name, field) \
 262	((read_phy_reg(pi, phy_type##_##reg_name) & phy_type##_##reg_name##_##field##_##MASK)\
 263	>> phy_type##_##reg_name##_##field##_##SHIFT)
 264
 265#define	VALID_PHYTYPE(phytype)	(((uint)phytype == PHY_TYPE_N) || \
 266				((uint)phytype == PHY_TYPE_LCN))
 267
 268#define VALID_N_RADIO(radioid)	((radioid == BCM2055_ID) || (radioid == BCM2056_ID) || \
 269				(radioid == BCM2057_ID))
 270#define VALID_LCN_RADIO(radioid)	(radioid == BCM2064_ID)
 271
 272#define	VALID_RADIO(pi, radioid)	(\
 273	(ISNPHY(pi) ? VALID_N_RADIO(radioid) : false) || \
 274	(ISLCNPHY(pi) ? VALID_LCN_RADIO(radioid) : false))
 275
 276#define SCAN_INPROG_PHY(pi)	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
 277#define RM_INPROG_PHY(pi)	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_RM))
 278#define PLT_INPROG_PHY(pi)	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT))
 279#define ASSOC_INPROG_PHY(pi)	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
 280#define SCAN_RM_IN_PROGRESS(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM))
 281#define PHY_MUTED(pi)		(mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE))
 282#define PUB_NOT_ASSOC(pi)	(mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC))
 283
 284#if defined(EXT_CBALL)
 285#define NORADIO_ENAB(pub) ((pub).radioid == NORADIO_ID)
 286#else
 287#define NORADIO_ENAB(pub) 0
 288#endif
 289
 290#define PHY_LTRN_LIST_LEN	64
 291extern u16 ltrn_list[PHY_LTRN_LIST_LEN];
 292
 293struct phy_table_info {
 294	uint table;
 295	int q;
 296	uint max;
 297};
 298
 299struct phytbl_info {
 300	const void *tbl_ptr;
 301	u32 tbl_len;
 302	u32 tbl_id;
 303	u32 tbl_offset;
 304	u32 tbl_width;
 305};
 306
 307struct interference_info {
 308	u8 curr_home_channel;
 309	u16 crsminpwrthld_40_stored;
 310	u16 crsminpwrthld_20L_stored;
 311	u16 crsminpwrthld_20U_stored;
 312	u16 init_gain_code_core1_stored;
 313	u16 init_gain_code_core2_stored;
 314	u16 init_gain_codeb_core1_stored;
 315	u16 init_gain_codeb_core2_stored;
 316	u16 init_gain_table_stored[4];
 317
 318	u16 clip1_hi_gain_code_core1_stored;
 319	u16 clip1_hi_gain_code_core2_stored;
 320	u16 clip1_hi_gain_codeb_core1_stored;
 321	u16 clip1_hi_gain_codeb_core2_stored;
 322	u16 nb_clip_thresh_core1_stored;
 323	u16 nb_clip_thresh_core2_stored;
 324	u16 init_ofdmlna2gainchange_stored[4];
 325	u16 init_ccklna2gainchange_stored[4];
 326	u16 clip1_lo_gain_code_core1_stored;
 327	u16 clip1_lo_gain_code_core2_stored;
 328	u16 clip1_lo_gain_codeb_core1_stored;
 329	u16 clip1_lo_gain_codeb_core2_stored;
 330	u16 w1_clip_thresh_core1_stored;
 331	u16 w1_clip_thresh_core2_stored;
 332	u16 radio_2056_core1_rssi_gain_stored;
 333	u16 radio_2056_core2_rssi_gain_stored;
 334	u16 energy_drop_timeout_len_stored;
 335
 336	u16 ed_crs40_assertthld0_stored;
 337	u16 ed_crs40_assertthld1_stored;
 338	u16 ed_crs40_deassertthld0_stored;
 339	u16 ed_crs40_deassertthld1_stored;
 340	u16 ed_crs20L_assertthld0_stored;
 341	u16 ed_crs20L_assertthld1_stored;
 342	u16 ed_crs20L_deassertthld0_stored;
 343	u16 ed_crs20L_deassertthld1_stored;
 344	u16 ed_crs20U_assertthld0_stored;
 345	u16 ed_crs20U_assertthld1_stored;
 346	u16 ed_crs20U_deassertthld0_stored;
 347	u16 ed_crs20U_deassertthld1_stored;
 348
 349	u16 badplcp_ma;
 350	u16 badplcp_ma_previous;
 351	u16 badplcp_ma_total;
 352	u16 badplcp_ma_list[MA_WINDOW_SZ];
 353	int badplcp_ma_index;
 354	s16 pre_badplcp_cnt;
 355	s16 bphy_pre_badplcp_cnt;
 356
 357	u16 init_gain_core1;
 358	u16 init_gain_core2;
 359	u16 init_gainb_core1;
 360	u16 init_gainb_core2;
 361	u16 init_gain_rfseq[4];
 362
 363	u16 crsminpwr0;
 364	u16 crsminpwrl0;
 365	u16 crsminpwru0;
 366
 367	s16 crsminpwr_index;
 368
 369	u16 radio_2057_core1_rssi_wb1a_gc_stored;
 370	u16 radio_2057_core2_rssi_wb1a_gc_stored;
 371	u16 radio_2057_core1_rssi_wb1g_gc_stored;
 372	u16 radio_2057_core2_rssi_wb1g_gc_stored;
 373	u16 radio_2057_core1_rssi_wb2_gc_stored;
 374	u16 radio_2057_core2_rssi_wb2_gc_stored;
 375	u16 radio_2057_core1_rssi_nb_gc_stored;
 376	u16 radio_2057_core2_rssi_nb_gc_stored;
 377};
 378
 379struct aci_save_gphy {
 380	u16 rc_cal_ovr;
 381	u16 phycrsth1;
 382	u16 phycrsth2;
 383	u16 init_n1p1_gain;
 384	u16 p1_p2_gain;
 385	u16 n1_n2_gain;
 386	u16 n1_p1_gain;
 387	u16 div_search_gain;
 388	u16 div_p1_p2_gain;
 389	u16 div_search_gn_change;
 390	u16 table_7_2;
 391	u16 table_7_3;
 392	u16 cckshbits_gnref;
 393	u16 clip_thresh;
 394	u16 clip2_thresh;
 395	u16 clip3_thresh;
 396	u16 clip_p2_thresh;
 397	u16 clip_pwdn_thresh;
 398	u16 clip_n1p1_thresh;
 399	u16 clip_n1_pwdn_thresh;
 400	u16 bbconfig;
 401	u16 cthr_sthr_shdin;
 402	u16 energy;
 403	u16 clip_p1_p2_thresh;
 404	u16 threshold;
 405	u16 reg15;
 406	u16 reg16;
 407	u16 reg17;
 408	u16 div_srch_idx;
 409	u16 div_srch_p1_p2;
 410	u16 div_srch_gn_back;
 411	u16 ant_dwell;
 412	u16 ant_wr_settle;
 413};
 414
 415struct lo_complex_abgphy_info {
 416	s8 i;
 417	s8 q;
 418};
 419
 420struct nphy_iq_comp {
 421	s16 a0;
 422	s16 b0;
 423	s16 a1;
 424	s16 b1;
 425};
 426
 427struct nphy_txpwrindex {
 428	s8 index;
 429	s8 index_internal;
 430	s8 index_internal_save;
 431	u16 AfectrlOverride;
 432	u16 AfeCtrlDacGain;
 433	u16 rad_gain;
 434	u8 bbmult;
 435	u16 iqcomp_a;
 436	u16 iqcomp_b;
 437	u16 locomp;
 438};
 439
 440struct txiqcal_cache {
 441
 442	u16 txcal_coeffs_2G[8];
 443	u16 txcal_radio_regs_2G[8];
 444	struct nphy_iq_comp rxcal_coeffs_2G;
 445
 446	u16 txcal_coeffs_5G[8];
 447	u16 txcal_radio_regs_5G[8];
 448	struct nphy_iq_comp rxcal_coeffs_5G;
 449};
 450
 451struct nphy_pwrctrl {
 452	s8 max_pwr_2g;
 453	s8 idle_targ_2g;
 454	s16 pwrdet_2g_a1;
 455	s16 pwrdet_2g_b0;
 456	s16 pwrdet_2g_b1;
 457	s8 max_pwr_5gm;
 458	s8 idle_targ_5gm;
 459	s8 max_pwr_5gh;
 460	s8 max_pwr_5gl;
 461	s16 pwrdet_5gm_a1;
 462	s16 pwrdet_5gm_b0;
 463	s16 pwrdet_5gm_b1;
 464	s16 pwrdet_5gl_a1;
 465	s16 pwrdet_5gl_b0;
 466	s16 pwrdet_5gl_b1;
 467	s16 pwrdet_5gh_a1;
 468	s16 pwrdet_5gh_b0;
 469	s16 pwrdet_5gh_b1;
 470	s8 idle_targ_5gl;
 471	s8 idle_targ_5gh;
 472	s8 idle_tssi_2g;
 473	s8 idle_tssi_5g;
 474	s8 idle_tssi;
 475	s16 a1;
 476	s16 b0;
 477	s16 b1;
 478};
 479
 480struct nphy_txgains {
 481	u16 txlpf[2];
 482	u16 txgm[2];
 483	u16 pga[2];
 484	u16 pad[2];
 485	u16 ipa[2];
 486};
 487
 488#define PHY_NOISEVAR_BUFSIZE 10
 489
 490struct nphy_noisevar_buf {
 491	int bufcount;
 492	int tone_id[PHY_NOISEVAR_BUFSIZE];
 493	u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
 494	u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
 495};
 496
 497struct rssical_cache {
 498	u16 rssical_radio_regs_2G[2];
 499	u16 rssical_phyregs_2G[12];
 500
 501	u16 rssical_radio_regs_5G[2];
 502	u16 rssical_phyregs_5G[12];
 503};
 504
 505struct lcnphy_cal_results {
 506
 507	u16 txiqlocal_a;
 508	u16 txiqlocal_b;
 509	u16 txiqlocal_didq;
 510	u8 txiqlocal_ei0;
 511	u8 txiqlocal_eq0;
 512	u8 txiqlocal_fi0;
 513	u8 txiqlocal_fq0;
 514
 515	u16 txiqlocal_bestcoeffs[11];
 516	u16 txiqlocal_bestcoeffs_valid;
 517
 518	u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
 519	u16 analog_gain_ref;
 520	u16 lut_begin;
 521	u16 lut_end;
 522	u16 lut_step;
 523	u16 rxcompdbm;
 524	u16 papdctrl;
 525	u16 sslpnCalibClkEnCtrl;
 526
 527	u16 rxiqcal_coeff_a0;
 528	u16 rxiqcal_coeff_b0;
 529};
 530
 531struct shared_phy {
 532	struct brcms_phy *phy_head;
 533	uint unit;
 534	struct si_pub *sih;
 535	void *physhim;
 536	uint corerev;
 537	u32 machwcap;
 538	bool up;
 539	bool clk;
 540	uint now;
 541	u16 vid;
 542	u16 did;
 543	uint chip;
 544	uint chiprev;
 545	uint chippkg;
 546	uint sromrev;
 547	uint boardtype;
 548	uint boardrev;
 549	uint boardvendor;
 550	u32 boardflags;
 551	u32 boardflags2;
 552	uint bustype;
 553	uint buscorerev;
 554	uint fast_timer;
 555	uint slow_timer;
 556	uint glacial_timer;
 557	u8 rx_antdiv;
 558	s8 phy_noise_window[MA_WINDOW_SZ];
 559	uint phy_noise_index;
 560	u8 hw_phytxchain;
 561	u8 hw_phyrxchain;
 562	u8 phytxchain;
 563	u8 phyrxchain;
 564	u8 rssi_mode;
 565	bool _rifs_phy;
 566};
 567
 568struct brcms_phy_pub {
 569	uint phy_type;
 570	uint phy_rev;
 571	u8 phy_corenum;
 572	u16 radioid;
 573	u8 radiorev;
 574	u8 radiover;
 575
 576	uint coreflags;
 577	uint ana_rev;
 578	bool abgphy_encore;
 579};
 580
 581struct phy_func_ptr {
 582	initfn_t init;
 583	initfn_t calinit;
 584	chansetfn_t chanset;
 585	initfn_t txpwrrecalc;
 586	longtrnfn_t longtrn;
 587	txiqccgetfn_t txiqccget;
 588	txiqccsetfn_t txiqccset;
 589	txloccgetfn_t txloccget;
 590	radioloftgetfn_t radioloftget;
 591	initfn_t carrsuppr;
 592	rxsigpwrfn_t rxsigpwr;
 593	detachfn_t detach;
 594};
 595
 596struct brcms_phy {
 597	struct brcms_phy_pub pubpi_ro;
 598	struct shared_phy *sh;
 599	struct phy_func_ptr pi_fptr;
 600	void *pi_ptr;
 601
 602	union {
 603		struct brcms_phy_lcnphy *pi_lcnphy;
 604	} u;
 605	bool user_txpwr_at_rfport;
 606
 607	d11regs_t *regs;
 608	struct brcms_phy *next;
 609	char *vars;
 610	struct brcms_phy_pub pubpi;
 611
 612	bool do_initcal;
 613	bool phytest_on;
 614	bool ofdm_rateset_war;
 615	bool bf_preempt_4306;
 616	chanspec_t radio_chanspec;
 617	u8 antsel_type;
 618	u16 bw;
 619	u8 txpwr_percent;
 620	bool phy_init_por;
 621
 622	bool init_in_progress;
 623	bool initialized;
 624	bool sbtml_gm;
 625	uint refcnt;
 626	bool watchdog_override;
 627	u8 phynoise_state;
 628	uint phynoise_now;
 629	int phynoise_chan_watchdog;
 630	bool phynoise_polling;
 631	bool disable_percal;
 632	mbool measure_hold;
 633
 634	s16 txpa_2g[PWRTBL_NUM_COEFF];
 635	s16 txpa_2g_low_temp[PWRTBL_NUM_COEFF];
 636	s16 txpa_2g_high_temp[PWRTBL_NUM_COEFF];
 637	s16 txpa_5g_low[PWRTBL_NUM_COEFF];
 638	s16 txpa_5g_mid[PWRTBL_NUM_COEFF];
 639	s16 txpa_5g_hi[PWRTBL_NUM_COEFF];
 640
 641	u8 tx_srom_max_2g;
 642	u8 tx_srom_max_5g_low;
 643	u8 tx_srom_max_5g_mid;
 644	u8 tx_srom_max_5g_hi;
 645	u8 tx_srom_max_rate_2g[TXP_NUM_RATES];
 646	u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES];
 647	u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES];
 648	u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES];
 649	u8 tx_user_target[TXP_NUM_RATES];
 650	s8 tx_power_offset[TXP_NUM_RATES];
 651	u8 tx_power_target[TXP_NUM_RATES];
 652
 653	struct brcms_phy_srom_fem srom_fem2g;
 654	struct brcms_phy_srom_fem srom_fem5g;
 655
 656	u8 tx_power_max;
 657	u8 tx_power_max_rate_ind;
 658	bool hwpwrctrl;
 659	u8 nphy_txpwrctrl;
 660	s8 nphy_txrx_chain;
 661	bool phy_5g_pwrgain;
 662
 663	u16 phy_wreg;
 664	u16 phy_wreg_limit;
 665
 666	s8 n_preamble_override;
 667	u8 antswitch;
 668	u8 aa2g, aa5g;
 669
 670	s8 idle_tssi[CH_5G_GROUP];
 671	s8 target_idle_tssi;
 672	s8 txpwr_est_Pout;
 673	u8 tx_power_min;
 674	u8 txpwr_limit[TXP_NUM_RATES];
 675	u8 txpwr_env_limit[TXP_NUM_RATES];
 676	u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN];
 677
 678	bool channel_14_wide_filter;
 679
 680	bool txpwroverride;
 681	bool txpwridx_override_aphy;
 682	s16 radiopwr_override;
 683	u16 hwpwr_txcur;
 684	u8 saved_txpwr_idx;
 685
 686	bool edcrs_threshold_lock;
 687
 688	u32 tr_R_gain_val;
 689	u32 tr_T_gain_val;
 690
 691	s16 ofdm_analog_filt_bw_override;
 692	s16 cck_analog_filt_bw_override;
 693	s16 ofdm_rccal_override;
 694	s16 cck_rccal_override;
 695	u16 extlna_type;
 696
 697	uint interference_mode_crs_time;
 698	u16 crsglitch_prev;
 699	bool interference_mode_crs;
 700
 701	u32 phy_tx_tone_freq;
 702	uint phy_lastcal;
 703	bool phy_forcecal;
 704	bool phy_fixed_noise;
 705	u32 xtalfreq;
 706	u8 pdiv;
 707	s8 carrier_suppr_disable;
 708
 709	bool phy_bphy_evm;
 710	bool phy_bphy_rfcs;
 711	s8 phy_scraminit;
 712	u8 phy_gpiosel;
 713
 714	s16 phy_txcore_disable_temp;
 715	s16 phy_txcore_enable_temp;
 716	s8 phy_tempsense_offset;
 717	bool phy_txcore_heatedup;
 718
 719	u16 radiopwr;
 720	u16 bb_atten;
 721	u16 txctl1;
 722
 723	u16 mintxbias;
 724	u16 mintxmag;
 725	struct lo_complex_abgphy_info gphy_locomp_iq
 726					[STATIC_NUM_RF][STATIC_NUM_BB];
 727	s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB];
 728	u16 gain_table[TX_GAIN_TABLE_LENGTH];
 729	bool loopback_gain;
 730	s16 max_lpback_gain_hdB;
 731	s16 trsw_rx_gain_hdB;
 732	u8 power_vec[8];
 733
 734	u16 rc_cal;
 735	int nrssi_table_delta;
 736	int nrssi_slope_scale;
 737	int nrssi_slope_offset;
 738	int min_rssi;
 739	int max_rssi;
 740
 741	s8 txpwridx;
 742	u8 min_txpower;
 743
 744	u8 a_band_high_disable;
 745
 746	u16 tx_vos;
 747	u16 global_tx_bb_dc_bias_loft;
 748
 749	int rf_max;
 750	int bb_max;
 751	int rf_list_size;
 752	int bb_list_size;
 753	u16 *rf_attn_list;
 754	u16 *bb_attn_list;
 755	u16 padmix_mask;
 756	u16 padmix_reg;
 757	u16 *txmag_list;
 758	uint txmag_len;
 759	bool txmag_enable;
 760
 761	s8 *a_tssi_to_dbm;
 762	s8 *m_tssi_to_dbm;
 763	s8 *l_tssi_to_dbm;
 764	s8 *h_tssi_to_dbm;
 765	u8 *hwtxpwr;
 766
 767	u16 freqtrack_saved_regs[2];
 768	int cur_interference_mode;
 769	bool hwpwrctrl_capable;
 770	bool temppwrctrl_capable;
 771
 772	uint phycal_nslope;
 773	uint phycal_noffset;
 774	uint phycal_mlo;
 775	uint phycal_txpower;
 776
 777	u8 phy_aa2g;
 778
 779	bool nphy_tableloaded;
 780	s8 nphy_rssisel;
 781	u32 nphy_bb_mult_save;
 782	u16 nphy_txiqlocal_bestc[11];
 783	bool nphy_txiqlocal_coeffsvalid;
 784	struct nphy_txpwrindex nphy_txpwrindex[PHY_CORE_NUM_2];
 785	struct nphy_pwrctrl nphy_pwrctrl_info[PHY_CORE_NUM_2];
 786	u16 cck2gpo;
 787	u32 ofdm2gpo;
 788	u32 ofdm5gpo;
 789	u32 ofdm5glpo;
 790	u32 ofdm5ghpo;
 791	u8 bw402gpo;
 792	u8 bw405gpo;
 793	u8 bw405glpo;
 794	u8 bw405ghpo;
 795	u8 cdd2gpo;
 796	u8 cdd5gpo;
 797	u8 cdd5glpo;
 798	u8 cdd5ghpo;
 799	u8 stbc2gpo;
 800	u8 stbc5gpo;
 801	u8 stbc5glpo;
 802	u8 stbc5ghpo;
 803	u8 bwdup2gpo;
 804	u8 bwdup5gpo;
 805	u8 bwdup5glpo;
 806	u8 bwdup5ghpo;
 807	u16 mcs2gpo[8];
 808	u16 mcs5gpo[8];
 809	u16 mcs5glpo[8];
 810	u16 mcs5ghpo[8];
 811	u32 nphy_rxcalparams;
 812
 813	u8 phy_spuravoid;
 814	bool phy_isspuravoid;
 815
 816	u8 phy_pabias;
 817	u8 nphy_papd_skip;
 818	u8 nphy_tssi_slope;
 819
 820	s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
 821	u8 nphy_noise_index;
 822
 823	u8 nphy_txpid2g[PHY_CORE_NUM_2];
 824	u8 nphy_txpid5g[PHY_CORE_NUM_2];
 825	u8 nphy_txpid5gl[PHY_CORE_NUM_2];
 826	u8 nphy_txpid5gh[PHY_CORE_NUM_2];
 827
 828	bool nphy_gain_boost;
 829	bool nphy_elna_gain_config;
 830	u16 old_bphy_test;
 831	u16 old_bphy_testcontrol;
 832
 833	bool phyhang_avoid;
 834
 835	bool rssical_nphy;
 836	u8 nphy_perical;
 837	uint nphy_perical_last;
 838	u8 cal_type_override;
 839	u8 mphase_cal_phase_id;
 840	u8 mphase_txcal_cmdidx;
 841	u8 mphase_txcal_numcmds;
 842	u16 mphase_txcal_bestcoeffs[11];
 843	chanspec_t nphy_txiqlocal_chanspec;
 844	chanspec_t nphy_iqcal_chanspec_2G;
 845	chanspec_t nphy_iqcal_chanspec_5G;
 846	chanspec_t nphy_rssical_chanspec_2G;
 847	chanspec_t nphy_rssical_chanspec_5G;
 848	struct wlapi_timer *phycal_timer;
 849	bool use_int_tx_iqlo_cal_nphy;
 850	bool internal_tx_iqlo_cal_tapoff_intpa_nphy;
 851	s16 nphy_lastcal_temp;
 852
 853	struct txiqcal_cache calibration_cache;
 854	struct rssical_cache rssical_cache;
 855
 856	u8 nphy_txpwr_idx[2];
 857	u8 nphy_papd_cal_type;
 858	uint nphy_papd_last_cal;
 859	u16 nphy_papd_tx_gain_at_last_cal[2];
 860	u8 nphy_papd_cal_gain_index[2];
 861	s16 nphy_papd_epsilon_offset[2];
 862	bool nphy_papd_recal_enable;
 863	u32 nphy_papd_recal_counter;
 864	bool nphy_force_papd_cal;
 865	bool nphy_papdcomp;
 866	bool ipa2g_on;
 867	bool ipa5g_on;
 868
 869	u16 classifier_state;
 870	u16 clip_state[2];
 871	uint nphy_deaf_count;
 872	u8 rxiq_samps;
 873	u8 rxiq_antsel;
 874
 875	u16 rfctrlIntc1_save;
 876	u16 rfctrlIntc2_save;
 877	bool first_cal_after_assoc;
 878	u16 tx_rx_cal_radio_saveregs[22];
 879	u16 tx_rx_cal_phy_saveregs[15];
 880
 881	u8 nphy_cal_orig_pwr_idx[2];
 882	u8 nphy_txcal_pwr_idx[2];
 883	u8 nphy_rxcal_pwr_idx[2];
 884	u16 nphy_cal_orig_tx_gain[2];
 885	struct nphy_txgains nphy_cal_target_gain;
 886	u16 nphy_txcal_bbmult;
 887	u16 nphy_gmval;
 888
 889	u16 nphy_saved_bbconf;
 890
 891	bool nphy_gband_spurwar_en;
 892	bool nphy_gband_spurwar2_en;
 893	bool nphy_aband_spurwar_en;
 894	u16 nphy_rccal_value;
 895	u16 nphy_crsminpwr[3];
 896	struct nphy_noisevar_buf nphy_saved_noisevars;
 897	bool nphy_anarxlpf_adjusted;
 898	bool nphy_crsminpwr_adjusted;
 899	bool nphy_noisevars_adjusted;
 900
 901	bool nphy_rxcal_active;
 902	u16 radar_percal_mask;
 903	bool dfs_lp_buffer_nphy;
 904
 905	u16 nphy_fineclockgatecontrol;
 906
 907	s8 rx2tx_biasentry;
 908
 909	u16 crsminpwr0;
 910	u16 crsminpwrl0;
 911	u16 crsminpwru0;
 912	s16 noise_crsminpwr_index;
 913	u16 init_gain_core1;
 914	u16 init_gain_core2;
 915	u16 init_gainb_core1;
 916	u16 init_gainb_core2;
 917	u8 aci_noise_curr_channel;
 918	u16 init_gain_rfseq[4];
 919
 920	bool radio_is_on;
 921
 922	bool nphy_sample_play_lpf_bw_ctl_ovr;
 923
 924	u16 tbl_data_hi;
 925	u16 tbl_data_lo;
 926	u16 tbl_addr;
 927
 928	uint tbl_save_id;
 929	uint tbl_save_offset;
 930
 931	u8 txpwrctrl;
 932	s8 txpwrindex[PHY_CORE_MAX];
 933
 934	u8 phycal_tempdelta;
 935	u32 mcs20_po;
 936	u32 mcs40_po;
 937	struct wiphy *wiphy;
 938};
 939
 940struct _cs32 {
 941	fixed q;
 942	fixed i;
 943};
 944
 945struct radio_regs {
 946	u16 address;
 947	u32 init_a;
 948	u32 init_g;
 949	u8 do_init_a;
 950	u8 do_init_g;
 951};
 952
 953struct radio_20xx_regs {
 954	u16 address;
 955	u8 init;
 956	u8 do_init;
 957};
 958
 959struct lcnphy_radio_regs {
 960	u16 address;
 961	u8 init_a;
 962	u8 init_g;
 963	u8 do_init_a;
 964	u8 do_init_g;
 965};
 966
 967extern struct lcnphy_radio_regs lcnphy_radio_regs_2064[];
 968extern struct lcnphy_radio_regs lcnphy_radio_regs_2066[];
 969extern struct radio_regs regs_2055[], regs_SYN_2056[], regs_TX_2056[],
 970	regs_RX_2056[];
 971extern struct radio_regs regs_SYN_2056_A1[], regs_TX_2056_A1[],
 972	      regs_RX_2056_A1[];
 973extern struct radio_regs regs_SYN_2056_rev5[], regs_TX_2056_rev5[],
 974	regs_RX_2056_rev5[];
 975extern struct radio_regs regs_SYN_2056_rev6[], regs_TX_2056_rev6[],
 976	regs_RX_2056_rev6[];
 977extern struct radio_regs regs_SYN_2056_rev7[], regs_TX_2056_rev7[],
 978	regs_RX_2056_rev7[];
 979extern struct radio_regs regs_SYN_2056_rev8[], regs_TX_2056_rev8[],
 980	regs_RX_2056_rev8[];
 981extern struct radio_20xx_regs regs_2057_rev4[], regs_2057_rev5[],
 982	      regs_2057_rev5v1[];
 983extern struct radio_20xx_regs regs_2057_rev7[], regs_2057_rev8[];
 984
 985extern char *phy_getvar(struct brcms_phy *pi, const char *name);
 986extern int phy_getintvar(struct brcms_phy *pi, const char *name);
 987#define PHY_GETVAR(pi, name)	phy_getvar(pi, name)
 988#define PHY_GETINTVAR(pi, name)	phy_getintvar(pi, name)
 989
 990extern u16 read_phy_reg(struct brcms_phy *pi, u16 addr);
 991extern void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
 992extern void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
 993extern void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
 994extern void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val);
 995
 996extern u16 read_radio_reg(struct brcms_phy *pi, u16 addr);
 997extern void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
 998extern void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
 999extern void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask,
1000			  u16 val);
1001extern void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask);
1002
1003extern void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
1004
1005extern void wlc_phyreg_enter(struct brcms_phy_pub *pih);
1006extern void wlc_phyreg_exit(struct brcms_phy_pub *pih);
1007extern void wlc_radioreg_enter(struct brcms_phy_pub *pih);
1008extern void wlc_radioreg_exit(struct brcms_phy_pub *pih);
1009
1010extern void wlc_phy_read_table(struct brcms_phy *pi,
1011			       const struct phytbl_info *ptbl_info,
1012			       u16 tblAddr, u16 tblDataHi,
1013			       u16 tblDatalo);
1014extern void wlc_phy_write_table(struct brcms_phy *pi,
1015				const struct phytbl_info *ptbl_info,
1016				u16 tblAddr, u16 tblDataHi, u16 tblDatalo);
1017extern void wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id,
1018			       uint tbl_offset, u16 tblAddr, u16 tblDataHi,
1019			       u16 tblDataLo);
1020extern void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val);
1021
1022extern void write_phy_channel_reg(struct brcms_phy *pi, uint val);
1023extern void wlc_phy_txpower_update_shm(struct brcms_phy *pi);
1024
1025extern void wlc_phy_cordic(fixed theta, cs32 *val);
1026extern u8 wlc_phy_nbits(s32 value);
1027extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
1028
1029extern uint wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi,
1030					     struct radio_20xx_regs *radioregs);
1031extern uint wlc_phy_init_radio_regs(struct brcms_phy *pi,
1032				    struct radio_regs *radioregs,
1033				    u16 core_offset);
1034
1035extern void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi);
1036
1037extern void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on);
1038extern void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real,
1039					s32 *eps_imag);
1040
1041extern void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi);
1042extern void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi);
1043
1044extern bool wlc_phy_attach_nphy(struct brcms_phy *pi);
1045extern bool wlc_phy_attach_lcnphy(struct brcms_phy *pi);
1046
1047extern void wlc_phy_detach_lcnphy(struct brcms_phy *pi);
1048
1049extern void wlc_phy_init_nphy(struct brcms_phy *pi);
1050extern void wlc_phy_init_lcnphy(struct brcms_phy *pi);
1051
1052extern void wlc_phy_cal_init_nphy(struct brcms_phy *pi);
1053extern void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi);
1054
1055extern void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi,
1056				      chanspec_t chanspec);
1057extern void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi,
1058					chanspec_t chanspec);
1059extern void wlc_phy_chanspec_set_fixup_lcnphy(struct brcms_phy *pi,
1060					      chanspec_t chanspec);
1061extern int wlc_phy_channel2freq(uint channel);
1062extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
1063extern int wlc_phy_chanspec_bandrange_get(struct brcms_phy *, chanspec_t);
1064
1065extern void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi, u16 mode);
1066extern s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi);
1067
1068extern void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi);
1069extern void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi);
1070extern void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi);
1071
1072extern void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi, int index);
1073extern void wlc_lcnphy_tx_pu(struct brcms_phy *pi, bool bEnable);
1074extern void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi);
1075extern void wlc_lcnphy_start_tx_tone(struct brcms_phy *pi, s32 f_kHz,
1076				     u16 max_val, bool iqcalmode);
1077
1078extern void wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi, uint chan,
1079					       u8 *max_pwr, u8 rate_id);
1080extern void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
1081					    u8 rate_mcs_end,
1082					    u8 rate_ofdm_start);
1083extern void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power,
1084					    u8 rate_ofdm_start,
1085					    u8 rate_ofdm_end,
1086					    u8 rate_mcs_start);
1087
1088extern u16 wlc_lcnphy_tempsense(struct brcms_phy *pi, bool mode);
1089extern s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi, bool mode);
1090extern s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi, bool mode);
1091extern s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi, bool mode);
1092extern void wlc_phy_carrier_suppress_lcnphy(struct brcms_phy *pi);
1093extern void wlc_lcnphy_crsuprs(struct brcms_phy *pi, int channel);
1094extern void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode);
1095extern void wlc_2064_vco_cal(struct brcms_phy *pi);
1096
1097extern void wlc_phy_txpower_recalc_target(struct brcms_phy *pi);
1098
1099#define LCNPHY_TBL_ID_PAPDCOMPDELTATBL	0x18
1100#define LCNPHY_TX_POWER_TABLE_SIZE	128
1101#define LCNPHY_MAX_TX_POWER_INDEX	(LCNPHY_TX_POWER_TABLE_SIZE - 1)
1102#define LCNPHY_TBL_ID_TXPWRCTL	0x07
1103#define LCNPHY_TX_PWR_CTRL_OFF	0
1104#define LCNPHY_TX_PWR_CTRL_SW		(0x1 << 15)
1105#define LCNPHY_TX_PWR_CTRL_HW         ((0x1 << 15) | \
1106					(0x1 << 14) | \
1107					(0x1 << 13))
1108
1109#define LCNPHY_TX_PWR_CTRL_TEMPBASED	0xE001
1110
1111extern void wlc_lcnphy_write_table(struct brcms_phy *pi,
1112				   const struct phytbl_info *pti);
1113extern void wlc_lcnphy_read_table(struct brcms_phy *pi,
1114				  struct phytbl_info *pti);
1115extern void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi, u16 a, u16 b);
1116extern void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi, u16 didq);
1117extern void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi, u16 *a, u16 *b);
1118extern u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi);
1119extern void wlc_lcnphy_get_radio_loft(struct brcms_phy *pi, u8 *ei0,
1120				      u8 *eq0, u8 *fi0, u8 *fq0);
1121extern void wlc_lcnphy_calib_modes(struct brcms_phy *pi, uint mode);
1122extern void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode);
1123extern bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi);
1124extern void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi);
1125extern s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1);
1126extern void wlc_lcnphy_get_tssi(struct brcms_phy *pi, s8 *ofdm_pwr,
1127				s8 *cck_pwr);
1128extern void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi);
1129
1130extern s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi, s32 gain_index);
1131
1132#define NPHY_MAX_HPVGA1_INDEX		10
1133#define NPHY_DEF_HPVGA1_INDEXLIMIT	7
1134
1135struct phy_iq_est {
1136	s32 iq_prod;
1137	u32 i_pwr;
1138	u32 q_pwr;
1139};
1140
1141extern void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi,
1142					       bool enable);
1143extern void wlc_nphy_deaf_mode(struct brcms_phy *pi, bool mode);
1144
1145#define wlc_phy_write_table_nphy(pi, pti)	wlc_phy_write_table(pi, pti, 0x72, \
1146	0x74, 0x73)
1147#define wlc_phy_read_table_nphy(pi, pti)	wlc_phy_read_table(pi, pti, 0x72, \
1148	0x74, 0x73)
1149#define wlc_nphy_table_addr(pi, id, off)	wlc_phy_table_addr((pi), (id), (off), \
1150	0x72, 0x74, 0x73)
1151#define wlc_nphy_table_data_write(pi, w, v)	wlc_phy_table_data_write((pi), (w), (v))
1152
1153extern void wlc_phy_table_read_nphy(struct brcms_phy *pi, u32, u32 l, u32 o,
1154				    u32 w, void *d);
1155extern void wlc_phy_table_write_nphy(struct brcms_phy *pi, u32, u32, u32,
1156				     u32, const void *);
1157
1158#define	PHY_IPA(pi) \
1159	((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
1160	 (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
1161
1162#define BRCMS_PHY_WAR_PR51571(pi) \
1163	if (((pi)->sh->bustype == PCI_BUS) && NREV_LT((pi)->pubpi.phy_rev, 3)) \
1164		(void)R_REG(&(pi)->regs->maccontrol)
1165
1166extern void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype);
1167extern void wlc_phy_aci_reset_nphy(struct brcms_phy *pi);
1168extern void wlc_phy_pa_override_nphy(struct brcms_phy *pi, bool en);
1169
1170extern u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi, uint chan);
1171extern void wlc_phy_switch_radio_nphy(struct brcms_phy *pi, bool on);
1172
1173extern void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi);
1174
1175extern void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi, u8 cmd);
1176extern s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi);
1177
1178extern u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val);
1179
1180extern void wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi, struct phy_iq_est *est,
1181				   u16 num_samps, u8 wait_time,
1182				   u8 wait_for_crs);
1183
1184extern void wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi, u8 write,
1185				      struct nphy_iq_comp *comp);
1186extern void wlc_phy_aci_and_noise_reduction_nphy(struct brcms_phy *pi);
1187
1188extern void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih,
1189					 u8 rxcore_bitmask);
1190extern u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih);
1191
1192extern void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi, u8 ctrl_type);
1193extern void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi);
1194extern void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi);
1195extern void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi);
1196extern u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi);
1197
1198extern struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi);
1199extern int wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi,
1200				   struct nphy_txgains target_gain,
1201				   bool full, bool m);
1202extern int wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi,
1203				 struct nphy_txgains target_gain,
1204				 u8 type, bool d);
1205extern void wlc_phy_txpwr_index_nphy(struct brcms_phy *pi, u8 core_mask,
1206				     s8 txpwrindex, bool res);
1207extern void wlc_phy_rssisel_nphy(struct brcms_phy *pi, u8 core, u8 rssi_type);
1208extern int wlc_phy_poll_rssi_nphy(struct brcms_phy *pi, u8 rssi_type,
1209				  s32 *rssi_buf, u8 nsamps);
1210extern void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi);
1211extern int wlc_phy_aci_scan_nphy(struct brcms_phy *pi);
1212extern void wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi,
1213					s32 dBm_targetpower, bool debug);
1214extern int wlc_phy_tx_tone_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val,
1215				u8 mode, u8, bool);
1216extern void wlc_phy_stopplayback_nphy(struct brcms_phy *pi);
1217extern void wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi, s32 *qdBm_pwrbuf,
1218				     u8 num_samps);
1219extern void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi);
1220
1221extern int wlc_phy_rssi_compute_nphy(struct brcms_phy *pi,
1222				     struct brcms_d11rxhdr *wlc_rxh);
1223
1224#define NPHY_TESTPATTERN_BPHY_EVM   0
1225#define NPHY_TESTPATTERN_BPHY_RFCS  1
1226
1227extern void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi, u8 rifs);
1228
1229void wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset,
1230				s8 *ofdmoffset);
1231extern s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi,
1232				    chanspec_t chanspec);
1233
1234extern bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pih);
1235#endif				/* _BRCM_PHY_INT_H_ */