/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
C | 6772 lines | 5051 code | 1015 blank | 706 comment | 946 complexity | 02856cd1f5dfd7e3cc5f432120f1cff0 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
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1/* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/types.h> 18#include <linux/kernel.h> 19#include <linux/kthread.h> 20#include <linux/printk.h> 21#include <linux/pci_ids.h> 22#include <linux/netdevice.h> 23#include <linux/interrupt.h> 24#include <linux/sched.h> 25#include <linux/mmc/sdio.h> 26#include <linux/mmc/sdio_func.h> 27#include <linux/semaphore.h> 28#include <linux/firmware.h> 29#include <asm/unaligned.h> 30#include <defs.h> 31#include <brcmu_wifi.h> 32#include <brcmu_utils.h> 33#include <brcm_hw_ids.h> 34#include <soc.h> 35#include "sdio_host.h" 36 37/* register access macros */ 38#ifndef __BIG_ENDIAN 39#ifndef __mips__ 40#define R_REG(r, typ) \ 41 brcmf_sdcard_reg_read(NULL, (r), sizeof(typ)) 42#else /* __mips__ */ 43#define R_REG(r, typ) \ 44 ({ \ 45 __typeof(*(r)) __osl_v; \ 46 __asm__ __volatile__("sync"); \ 47 __osl_v = brcmf_sdcard_reg_read(NULL, (r),\ 48 sizeof(typ)); \ 49 __asm__ __volatile__("sync"); \ 50 __osl_v; \ 51 }) 52#endif /* __mips__ */ 53 54#else /* __BIG_ENDIAN */ 55#define R_REG(r, typ) \ 56 brcmf_sdcard_reg_read(NULL, (r), sizeof(typ)) 57#endif /* __BIG_ENDIAN */ 58 59#define OR_REG(r, v, typ) \ 60 brcmf_sdcard_reg_write(NULL, (r), sizeof(typ), R_REG(r, typ) | (v)) 61 62#ifdef BCMDBG 63 64/* ARM trap handling */ 65 66/* Trap types defined by ARM (see arminc.h) */ 67 68#if defined(__ARM_ARCH_4T__) 69#define MAX_TRAP_TYPE (TR_FIQ + 1) 70#elif defined(__ARM_ARCH_7M__) 71#define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS) 72#endif /* __ARM_ARCH_7M__ */ 73 74/* The trap structure is defined here as offsets for assembly */ 75#define TR_TYPE 0x00 76#define TR_EPC 0x04 77#define TR_CPSR 0x08 78#define TR_SPSR 0x0c 79#define TR_REGS 0x10 80#define TR_REG(n) (TR_REGS + (n) * 4) 81#define TR_SP TR_REG(13) 82#define TR_LR TR_REG(14) 83#define TR_PC TR_REG(15) 84 85#define TRAP_T_SIZE 80 86 87struct brcmf_trap { 88 u32 type; 89 u32 epc; 90 u32 cpsr; 91 u32 spsr; 92 u32 r0; 93 u32 r1; 94 u32 r2; 95 u32 r3; 96 u32 r4; 97 u32 r5; 98 u32 r6; 99 u32 r7; 100 u32 r8; 101 u32 r9; 102 u32 r10; 103 u32 r11; 104 u32 r12; 105 u32 r13; 106 u32 r14; 107 u32 pc; 108}; 109 110#define CBUF_LEN (128) 111 112struct rte_log { 113 u32 buf; /* Can't be pointer on (64-bit) hosts */ 114 uint buf_size; 115 uint idx; 116 char *_buf_compat; /* Redundant pointer for backward compat. */ 117}; 118 119struct rte_console { 120 /* Virtual UART 121 * When there is no UART (e.g. Quickturn), 122 * the host should write a complete 123 * input line directly into cbuf and then write 124 * the length into vcons_in. 125 * This may also be used when there is a real UART 126 * (at risk of conflicting with 127 * the real UART). vcons_out is currently unused. 128 */ 129 volatile uint vcons_in; 130 volatile uint vcons_out; 131 132 /* Output (logging) buffer 133 * Console output is written to a ring buffer log_buf at index log_idx. 134 * The host may read the output when it sees log_idx advance. 135 * Output will be lost if the output wraps around faster than the host 136 * polls. 137 */ 138 struct rte_log log; 139 140 /* Console input line buffer 141 * Characters are read one at a time into cbuf 142 * until <CR> is received, then 143 * the buffer is processed as a command line. 144 * Also used for virtual UART. 145 */ 146 uint cbuf_idx; 147 char cbuf[CBUF_LEN]; 148}; 149 150#endif /* BCMDBG */ 151#include <chipcommon.h> 152 153#include "dhd.h" 154#include "dhd_bus.h" 155#include "dhd_proto.h" 156#include "dhd_dbg.h" 157#include <bcmchip.h> 158 159#define TXQLEN 2048 /* bulk tx queue length */ 160#define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ 161#define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ 162#define PRIOMASK 7 163 164#define TXRETRIES 2 /* # of retries for tx frames */ 165 166#define BRCMF_RXBOUND 50 /* Default for max rx frames in 167 one scheduling */ 168 169#define BRCMF_TXBOUND 20 /* Default for max tx frames in 170 one scheduling */ 171 172#define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ 173 174#define MEMBLOCK 2048 /* Block size used for downloading 175 of dongle image */ 176#define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold 177 biggest possible glom */ 178 179#ifndef BRCMF_FIRSTREAD 180#define BRCMF_FIRSTREAD 32 181#endif 182 183#if !ISPOWEROF2(BRCMF_FIRSTREAD) 184#error BRCMF_FIRSTREAD is not a power of 2! 185#endif 186 187/* SBSDIO_DEVICE_CTL */ 188#define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when 189 * receiving CMD53 190 */ 191#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is 192 * synchronous to the sdio clock 193 */ 194#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host 195 * except the chipActive (rev 8) 196 */ 197#define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put 198 * external pads in tri-state; requires 199 * sdio bus power cycle to clear (rev 9) 200 */ 201#define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */ 202#define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */ 203#define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */ 204#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */ 205 206/* SBSDIO_FUNC1_CHIPCLKCSR */ 207#define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */ 208#define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */ 209#define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */ 210#define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */ 211#define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */ 212#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */ 213#define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */ 214#define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */ 215 216#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) 217#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) 218#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) 219#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) 220#define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \ 221 (alponly ? 1 : SBSDIO_HTAV(regval))) 222/* direct(mapped) cis space */ 223#define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */ 224#define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */ 225#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */ 226 227#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple, 228 * link bytes 229 */ 230 231/* intstatus */ 232#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ 233#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ 234#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ 235#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ 236#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ 237#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ 238#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ 239#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ 240#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ 241#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ 242#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ 243#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ 244#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ 245#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ 246#define I_PC (1 << 10) /* descriptor error */ 247#define I_PD (1 << 11) /* data error */ 248#define I_DE (1 << 12) /* Descriptor protocol Error */ 249#define I_RU (1 << 13) /* Receive descriptor Underflow */ 250#define I_RO (1 << 14) /* Receive fifo Overflow */ 251#define I_XU (1 << 15) /* Transmit fifo Underflow */ 252#define I_RI (1 << 16) /* Receive Interrupt */ 253#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ 254#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ 255#define I_XI (1 << 24) /* Transmit Interrupt */ 256#define I_RF_TERM (1 << 25) /* Read Frame Terminate */ 257#define I_WF_TERM (1 << 26) /* Write Frame Terminate */ 258#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ 259#define I_SBINT (1 << 28) /* sbintstatus Interrupt */ 260#define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ 261#define I_SRESET (1 << 30) /* CCCR RES interrupt */ 262#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ 263#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) 264#define I_DMA (I_RI | I_XI | I_ERRORS) 265 266/* corecontrol */ 267#define CC_CISRDY (1 << 0) /* CIS Ready */ 268#define CC_BPRESEN (1 << 1) /* CCCR RES signal */ 269#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ 270#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ 271#define CC_XMTDATAAVAIL_MODE (1 << 4) 272#define CC_XMTDATAAVAIL_CTRL (1 << 5) 273 274/* SDA_FRAMECTRL */ 275#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 276#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 277#define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ 278#define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ 279 280/* HW frame tag */ 281#define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */ 282 283/* Total length of frame header for dongle protocol */ 284#define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN) 285#ifdef SDTEST 286#define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + BRCMF_SDALIGN) 287#else 288#define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN) 289#endif 290 291/* 292 * Software allocation of To SB Mailbox resources 293 */ 294 295/* tosbmailbox bits corresponding to intstatus bits */ 296#define SMB_NAK (1 << 0) /* Frame NAK */ 297#define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ 298#define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ 299#define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ 300 301/* tosbmailboxdata */ 302#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ 303 304/* 305 * Software allocation of To Host Mailbox resources 306 */ 307 308/* intstatus bits */ 309#define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ 310#define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ 311#define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ 312#define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ 313 314/* tohostmailboxdata */ 315#define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */ 316#define HMB_DATA_DEVREADY 2 /* talk to host after enable */ 317#define HMB_DATA_FC 4 /* per prio flowcontrol update flag */ 318#define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */ 319 320#define HMB_DATA_FCDATA_MASK 0xff000000 321#define HMB_DATA_FCDATA_SHIFT 24 322 323#define HMB_DATA_VERSION_MASK 0x00ff0000 324#define HMB_DATA_VERSION_SHIFT 16 325 326/* 327 * Software-defined protocol header 328 */ 329 330/* Current protocol version */ 331#define SDPCM_PROT_VERSION 4 332 333/* SW frame header */ 334#define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff) 335 336#define SDPCM_CHANNEL_MASK 0x00000f00 337#define SDPCM_CHANNEL_SHIFT 8 338#define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f) 339 340#define SDPCM_NEXTLEN_OFFSET 2 341 342/* Data Offset from SOF (HW Tag, SW Tag, Pad) */ 343#define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */ 344#define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff) 345#define SDPCM_DOFFSET_MASK 0xff000000 346#define SDPCM_DOFFSET_SHIFT 24 347#define SDPCM_FCMASK_OFFSET 4 /* Flow control */ 348#define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff) 349#define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */ 350#define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff) 351 352#define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */ 353 354/* logical channel numbers */ 355#define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */ 356#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */ 357#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */ 358#define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */ 359#define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */ 360 361#define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */ 362 363#define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) 364 365/* For TEST_CHANNEL packets, define another 4-byte header */ 366#define SDPCM_TEST_HDRLEN 4 /* 367 * Generally: Cmd(1), Ext(1), Len(2); 368 * Semantics of Ext byte depend on 369 * command. Len is current or requested 370 * frame length, not including test 371 * header; sent little-endian. 372 */ 373#define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext:pattern id. */ 374#define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext:pattern id. */ 375#define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext:pattern id. */ 376#define SDPCM_TEST_BURST 0x04 /* 377 * Receiver to send a burst. 378 * Ext is a frame count 379 */ 380#define SDPCM_TEST_SEND 0x05 /* 381 * Receiver sets send mode. 382 * Ext is boolean on/off 383 */ 384 385/* Handy macro for filling in datagen packets with a pattern */ 386#define SDPCM_TEST_FILL(byteno, id) ((u8)(id + byteno)) 387 388/* 389 * Shared structure between dongle and the host. 390 * The structure contains pointers to trap or assert information. 391 */ 392#define SDPCM_SHARED_VERSION 0x0002 393#define SDPCM_SHARED_VERSION_MASK 0x00FF 394#define SDPCM_SHARED_ASSERT_BUILT 0x0100 395#define SDPCM_SHARED_ASSERT 0x0200 396#define SDPCM_SHARED_TRAP 0x0400 397 398 399/* Space for header read, limit for data packets */ 400#ifndef MAX_HDR_READ 401#define MAX_HDR_READ 32 402#endif 403#if !ISPOWEROF2(MAX_HDR_READ) 404#error MAX_HDR_READ is not a power of 2! 405#endif 406 407#define MAX_RX_DATASZ 2048 408 409/* Maximum milliseconds to wait for F2 to come up */ 410#define BRCMF_WAIT_F2RDY 3000 411 412/* Bump up limit on waiting for HT to account for first startup; 413 * if the image is doing a CRC calculation before programming the PMU 414 * for HT availability, it could take a couple hundred ms more, so 415 * max out at a 1 second (1000000us). 416 */ 417#if (PMU_MAX_TRANSITION_DLY <= 1000000) 418#undef PMU_MAX_TRANSITION_DLY 419#define PMU_MAX_TRANSITION_DLY 1000000 420#endif 421 422/* Value for ChipClockCSR during initial setup */ 423#define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ 424 SBSDIO_ALP_AVAIL_REQ) 425 426/* Flags for SDH calls */ 427#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) 428 429/* sbimstate */ 430#define SBIM_IBE 0x20000 /* inbanderror */ 431#define SBIM_TO 0x40000 /* timeout */ 432#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */ 433#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */ 434 435/* sbtmstatelow */ 436#define SBTML_RESET 0x0001 /* reset */ 437#define SBTML_REJ_MASK 0x0006 /* reject field */ 438#define SBTML_REJ 0x0002 /* reject */ 439#define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */ 440 441#define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */ 442 443/* sbtmstatehigh */ 444#define SBTMH_SERR 0x0001 /* serror */ 445#define SBTMH_INT 0x0002 /* interrupt */ 446#define SBTMH_BUSY 0x0004 /* busy */ 447#define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */ 448 449#define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */ 450 451/* sbidlow */ 452#define SBIDL_INIT 0x80 /* initiator */ 453 454/* sbidhigh */ 455#define SBIDH_RC_MASK 0x000f /* revision code */ 456#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */ 457#define SBIDH_RCE_SHIFT 8 458#define SBCOREREV(sbidh) \ 459 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK)) 460#define SBIDH_CC_MASK 0x8ff0 /* core code */ 461#define SBIDH_CC_SHIFT 4 462#define SBIDH_VC_MASK 0xffff0000 /* vendor code */ 463#define SBIDH_VC_SHIFT 16 464 465/* 466 * Conversion of 802.1D priority to precedence level 467 */ 468#define PRIO2PREC(prio) \ 469 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \ 470 ((prio^2)) : (prio)) 471 472BRCMF_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep); 473 474/* 475 * Core reg address translation. 476 * Both macro's returns a 32 bits byte address on the backplane bus. 477 */ 478#define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field)) 479#define CORE_BUS_REG(base, field) \ 480 (base + offsetof(struct sdpcmd_regs, field)) 481#define CORE_SB(base, field) \ 482 (base + SBCONFIGOFF + offsetof(struct sbconfig, field)) 483 484/* core registers */ 485struct sdpcmd_regs { 486 u32 corecontrol; /* 0x00, rev8 */ 487 u32 corestatus; /* rev8 */ 488 u32 PAD[1]; 489 u32 biststatus; /* rev8 */ 490 491 /* PCMCIA access */ 492 u16 pcmciamesportaladdr; /* 0x010, rev8 */ 493 u16 PAD[1]; 494 u16 pcmciamesportalmask; /* rev8 */ 495 u16 PAD[1]; 496 u16 pcmciawrframebc; /* rev8 */ 497 u16 PAD[1]; 498 u16 pcmciaunderflowtimer; /* rev8 */ 499 u16 PAD[1]; 500 501 /* interrupt */ 502 u32 intstatus; /* 0x020, rev8 */ 503 u32 hostintmask; /* rev8 */ 504 u32 intmask; /* rev8 */ 505 u32 sbintstatus; /* rev8 */ 506 u32 sbintmask; /* rev8 */ 507 u32 funcintmask; /* rev4 */ 508 u32 PAD[2]; 509 u32 tosbmailbox; /* 0x040, rev8 */ 510 u32 tohostmailbox; /* rev8 */ 511 u32 tosbmailboxdata; /* rev8 */ 512 u32 tohostmailboxdata; /* rev8 */ 513 514 /* synchronized access to registers in SDIO clock domain */ 515 u32 sdioaccess; /* 0x050, rev8 */ 516 u32 PAD[3]; 517 518 /* PCMCIA frame control */ 519 u8 pcmciaframectrl; /* 0x060, rev8 */ 520 u8 PAD[3]; 521 u8 pcmciawatermark; /* rev8 */ 522 u8 PAD[155]; 523 524 /* interrupt batching control */ 525 u32 intrcvlazy; /* 0x100, rev8 */ 526 u32 PAD[3]; 527 528 /* counters */ 529 u32 cmd52rd; /* 0x110, rev8 */ 530 u32 cmd52wr; /* rev8 */ 531 u32 cmd53rd; /* rev8 */ 532 u32 cmd53wr; /* rev8 */ 533 u32 abort; /* rev8 */ 534 u32 datacrcerror; /* rev8 */ 535 u32 rdoutofsync; /* rev8 */ 536 u32 wroutofsync; /* rev8 */ 537 u32 writebusy; /* rev8 */ 538 u32 readwait; /* rev8 */ 539 u32 readterm; /* rev8 */ 540 u32 writeterm; /* rev8 */ 541 u32 PAD[40]; 542 u32 clockctlstatus; /* rev8 */ 543 u32 PAD[7]; 544 545 u32 PAD[128]; /* DMA engines */ 546 547 /* SDIO/PCMCIA CIS region */ 548 char cis[512]; /* 0x400-0x5ff, rev6 */ 549 550 /* PCMCIA function control registers */ 551 char pcmciafcr[256]; /* 0x600-6ff, rev6 */ 552 u16 PAD[55]; 553 554 /* PCMCIA backplane access */ 555 u16 backplanecsr; /* 0x76E, rev6 */ 556 u16 backplaneaddr0; /* rev6 */ 557 u16 backplaneaddr1; /* rev6 */ 558 u16 backplaneaddr2; /* rev6 */ 559 u16 backplaneaddr3; /* rev6 */ 560 u16 backplanedata0; /* rev6 */ 561 u16 backplanedata1; /* rev6 */ 562 u16 backplanedata2; /* rev6 */ 563 u16 backplanedata3; /* rev6 */ 564 u16 PAD[31]; 565 566 /* sprom "size" & "blank" info */ 567 u16 spromstatus; /* 0x7BE, rev2 */ 568 u32 PAD[464]; 569 570 u16 PAD[0x80]; 571}; 572 573#ifdef BCMDBG 574/* Device console log buffer state */ 575struct brcmf_console { 576 uint count; /* Poll interval msec counter */ 577 uint log_addr; /* Log struct address (fixed) */ 578 struct rte_log log; /* Log struct (host copy) */ 579 uint bufsize; /* Size of log buffer */ 580 u8 *buf; /* Log buffer (host copy) */ 581 uint last; /* Last buffer read index */ 582}; 583#endif /* BCMDBG */ 584 585struct sdpcm_shared { 586 u32 flags; 587 u32 trap_addr; 588 u32 assert_exp_addr; 589 u32 assert_file_addr; 590 u32 assert_line; 591 u32 console_addr; /* Address of struct rte_console */ 592 u32 msgtrace_addr; 593 u8 tag[32]; 594}; 595 596 597/* misc chip info needed by some of the routines */ 598struct chip_info { 599 u32 chip; 600 u32 chiprev; 601 u32 cccorebase; 602 u32 ccrev; 603 u32 cccaps; 604 u32 buscorebase; /* 32 bits backplane bus address */ 605 u32 buscorerev; 606 u32 buscoretype; 607 u32 ramcorebase; 608 u32 armcorebase; 609 u32 pmurev; 610 u32 ramsize; 611}; 612 613/* Private data for SDIO bus interaction */ 614struct brcmf_bus { 615 struct brcmf_pub *drvr; 616 617 struct brcmf_sdio_card *card; /* Handle for sdio card calls */ 618 struct chip_info *ci; /* Chip info struct */ 619 char *vars; /* Variables (from CIS and/or other) */ 620 uint varsz; /* Size of variables buffer */ 621 622 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */ 623 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */ 624 625 u32 bus; /* gSPI or SDIO bus */ 626 u32 hostintmask; /* Copy of Host Interrupt Mask */ 627 u32 intstatus; /* Intstatus bits (events) pending */ 628 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */ 629 bool fcstate; /* State of dongle flow-control */ 630 631 u16 cl_devid; /* cached devid for brcmf_sdio_probe_attach() */ 632 633 uint blocksize; /* Block size of SDIO transfers */ 634 uint roundup; /* Max roundup limit */ 635 636 struct pktq txq; /* Queue length used for flow-control */ 637 u8 flowcontrol; /* per prio flow control bitmask */ 638 u8 tx_seq; /* Transmit sequence number (next) */ 639 u8 tx_max; /* Maximum transmit sequence allowed */ 640 641 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN]; 642 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ 643 u16 nextlen; /* Next Read Len from last header */ 644 u8 rx_seq; /* Receive sequence number (expected) */ 645 bool rxskip; /* Skip receive (awaiting NAK ACK) */ 646 647 struct sk_buff *glomd; /* Packet containing glomming descriptor */ 648 struct sk_buff *glom; /* Packet chain for glommed superframe */ 649 uint glomerr; /* Glom packet read errors */ 650 651 u8 *rxbuf; /* Buffer for receiving control packets */ 652 uint rxblen; /* Allocated length of rxbuf */ 653 u8 *rxctl; /* Aligned pointer into rxbuf */ 654 u8 *databuf; /* Buffer for receiving big glom packet */ 655 u8 *dataptr; /* Aligned pointer into databuf */ 656 uint rxlen; /* Length of valid data in buffer */ 657 658 u8 sdpcm_ver; /* Bus protocol reported by dongle */ 659 660 bool intr; /* Use interrupts */ 661 bool poll; /* Use polling */ 662 bool ipend; /* Device interrupt is pending */ 663 bool intdis; /* Interrupts disabled by isr */ 664 uint intrcount; /* Count of device interrupt callbacks */ 665 uint lastintrs; /* Count as of last watchdog timer */ 666 uint spurious; /* Count of spurious interrupts */ 667 uint pollrate; /* Ticks between device polls */ 668 uint polltick; /* Tick counter */ 669 uint pollcnt; /* Count of active polls */ 670 671#ifdef BCMDBG 672 struct brcmf_console console; /* Console output polling support */ 673 uint console_addr; /* Console address from shared struct */ 674#endif /* BCMDBG */ 675 676 uint regfails; /* Count of R_REG failures */ 677 678 uint clkstate; /* State of sd and backplane clock(s) */ 679 bool activity; /* Activity flag for clock down */ 680 s32 idletime; /* Control for activity timeout */ 681 s32 idlecount; /* Activity timeout counter */ 682 s32 idleclock; /* How to set bus driver when idle */ 683 s32 sd_rxchain; 684 bool use_rxchain; /* If brcmf should use PKT chains */ 685 bool sleeping; /* Is SDIO bus sleeping? */ 686 bool rxflow_mode; /* Rx flow control mode */ 687 bool rxflow; /* Is rx flow control on */ 688 bool alp_only; /* Don't use HT clock (ALP only) */ 689/* Field to decide if rx of control frames happen in rxbuf or lb-pool */ 690 bool usebufpool; 691 692#ifdef SDTEST 693 /* external loopback */ 694 bool ext_loop; 695 u8 loopid; 696 697 /* pktgen configuration */ 698 uint pktgen_freq; /* Ticks between bursts */ 699 uint pktgen_count; /* Packets to send each burst */ 700 uint pktgen_print; /* Bursts between count displays */ 701 uint pktgen_total; /* Stop after this many */ 702 uint pktgen_minlen; /* Minimum packet data len */ 703 uint pktgen_maxlen; /* Maximum packet data len */ 704 uint pktgen_mode; /* Configured mode: tx, rx, or echo */ 705 uint pktgen_stop; /* Number of tx failures causing stop */ 706 707 /* active pktgen fields */ 708 uint pktgen_tick; /* Tick counter for bursts */ 709 uint pktgen_ptick; /* Burst counter for printing */ 710 uint pktgen_sent; /* Number of test packets generated */ 711 uint pktgen_rcvd; /* Number of test packets received */ 712 uint pktgen_fail; /* Number of failed send attempts */ 713 u16 pktgen_len; /* Length of next packet to send */ 714#endif /* SDTEST */ 715 716 /* Some additional counters */ 717 uint tx_sderrs; /* Count of tx attempts with sd errors */ 718 uint fcqueued; /* Tx packets that got queued */ 719 uint rxrtx; /* Count of rtx requests (NAK to dongle) */ 720 uint rx_toolong; /* Receive frames too long to receive */ 721 uint rxc_errors; /* SDIO errors when reading control frames */ 722 uint rx_hdrfail; /* SDIO errors on header reads */ 723 uint rx_badhdr; /* Bad received headers (roosync?) */ 724 uint rx_badseq; /* Mismatched rx sequence number */ 725 uint fc_rcvd; /* Number of flow-control events received */ 726 uint fc_xoff; /* Number which turned on flow-control */ 727 uint fc_xon; /* Number which turned off flow-control */ 728 uint rxglomfail; /* Failed deglom attempts */ 729 uint rxglomframes; /* Number of glom frames (superframes) */ 730 uint rxglompkts; /* Number of packets from glom frames */ 731 uint f2rxhdrs; /* Number of header reads */ 732 uint f2rxdata; /* Number of frame data reads */ 733 uint f2txdata; /* Number of f2 frame writes */ 734 uint f1regdata; /* Number of f1 register accesses */ 735 736 u8 *ctrl_frame_buf; 737 u32 ctrl_frame_len; 738 bool ctrl_frame_stat; 739 740 spinlock_t txqlock; 741 wait_queue_head_t ctrl_wait; 742 743 struct timer_list timer; 744 struct completion watchdog_wait; 745 struct task_struct *watchdog_tsk; 746 bool wd_timer_valid; 747 748 struct tasklet_struct tasklet; 749 struct task_struct *dpc_tsk; 750 struct completion dpc_wait; 751 752 bool threads_only; 753 struct semaphore sdsem; 754 spinlock_t sdlock; 755 756 const char *fw_name; 757 const struct firmware *firmware; 758 const char *nv_name; 759 u32 fw_ptr; 760}; 761 762struct sbconfig { 763 u32 PAD[2]; 764 u32 sbipsflag; /* initiator port ocp slave flag */ 765 u32 PAD[3]; 766 u32 sbtpsflag; /* target port ocp slave flag */ 767 u32 PAD[11]; 768 u32 sbtmerrloga; /* (sonics >= 2.3) */ 769 u32 PAD; 770 u32 sbtmerrlog; /* (sonics >= 2.3) */ 771 u32 PAD[3]; 772 u32 sbadmatch3; /* address match3 */ 773 u32 PAD; 774 u32 sbadmatch2; /* address match2 */ 775 u32 PAD; 776 u32 sbadmatch1; /* address match1 */ 777 u32 PAD[7]; 778 u32 sbimstate; /* initiator agent state */ 779 u32 sbintvec; /* interrupt mask */ 780 u32 sbtmstatelow; /* target state */ 781 u32 sbtmstatehigh; /* target state */ 782 u32 sbbwa0; /* bandwidth allocation table0 */ 783 u32 PAD; 784 u32 sbimconfiglow; /* initiator configuration */ 785 u32 sbimconfighigh; /* initiator configuration */ 786 u32 sbadmatch0; /* address match0 */ 787 u32 PAD; 788 u32 sbtmconfiglow; /* target configuration */ 789 u32 sbtmconfighigh; /* target configuration */ 790 u32 sbbconfig; /* broadcast configuration */ 791 u32 PAD; 792 u32 sbbstate; /* broadcast state */ 793 u32 PAD[3]; 794 u32 sbactcnfg; /* activate configuration */ 795 u32 PAD[3]; 796 u32 sbflagst; /* current sbflags */ 797 u32 PAD[3]; 798 u32 sbidlow; /* identification */ 799 u32 sbidhigh; /* identification */ 800}; 801 802/* clkstate */ 803#define CLK_NONE 0 804#define CLK_SDONLY 1 805#define CLK_PENDING 2 /* Not used yet */ 806#define CLK_AVAIL 3 807 808#define BRCMF_NOPMU(brcmf) (false) 809 810#ifdef BCMDBG 811static int qcount[NUMPRIO]; 812static int tx_packets[NUMPRIO]; 813#endif /* BCMDBG */ 814 815/* Deferred transmit */ 816uint brcmf_deferred_tx = 1; 817module_param(brcmf_deferred_tx, uint, 0); 818 819/* Watchdog thread priority, -1 to use kernel timer */ 820int brcmf_watchdog_prio = 97; 821module_param(brcmf_watchdog_prio, int, 0); 822 823/* Watchdog interval */ 824uint brcmf_watchdog_ms = 10; 825module_param(brcmf_watchdog_ms, uint, 0); 826 827/* DPC thread priority, -1 to use tasklet */ 828int brcmf_dpc_prio = 98; 829module_param(brcmf_dpc_prio, int, 0); 830 831#ifdef BCMDBG 832/* Console poll interval */ 833uint brcmf_console_ms; 834module_param(brcmf_console_ms, uint, 0); 835#endif /* BCMDBG */ 836 837/* Tx/Rx bounds */ 838uint brcmf_txbound; 839uint brcmf_rxbound; 840uint brcmf_txminmax; 841 842/* override the RAM size if possible */ 843#define DONGLE_MIN_MEMSIZE (128 * 1024) 844int brcmf_dongle_memsize; 845 846static bool brcmf_alignctl; 847 848static bool sd1idle; 849 850static bool retrydata; 851#define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata) 852 853static const uint watermark = 8; 854static const uint firstread = BRCMF_FIRSTREAD; 855 856/* Retry count for register access failures */ 857static const uint retry_limit = 2; 858 859/* Force even SD lengths (some host controllers mess up on odd bytes) */ 860static bool forcealign; 861 862#define ALIGNMENT 4 863 864#define PKTALIGN(_p, _len, _align) \ 865 do { \ 866 uint datalign; \ 867 datalign = (unsigned long)((_p)->data); \ 868 datalign = roundup(datalign, (_align)) - datalign; \ 869 if (datalign) \ 870 skb_pull((_p), datalign); \ 871 __skb_trim((_p), (_len)); \ 872 } while (0) 873 874/* Limit on rounding up frames */ 875static const uint max_roundup = 512; 876 877/* Try doing readahead */ 878static bool brcmf_readahead; 879 880/* To check if there's window offered */ 881#define DATAOK(bus) \ 882 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \ 883 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0)) 884 885/* 886 * Reads a register in the SDIO hardware block. This block occupies a series of 887 * adresses on the 32 bit backplane bus. 888 */ 889static void 890r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar) 891{ 892 *retryvar = 0; 893 do { 894 *regvar = R_REG(bus->ci->buscorebase + reg_offset, u32); 895 } while (brcmf_sdcard_regfail(bus->card) && 896 (++(*retryvar) <= retry_limit)); 897 if (*retryvar) { 898 bus->regfails += (*retryvar-1); 899 if (*retryvar > retry_limit) { 900 BRCMF_ERROR(("FAILED READ %Xh\n", reg_offset)); 901 *regvar = 0; 902 } 903 } 904} 905 906static void 907w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar) 908{ 909 *retryvar = 0; 910 do { 911 brcmf_sdcard_reg_write(NULL, bus->ci->buscorebase + reg_offset, 912 sizeof(u32), regval); 913 } while (brcmf_sdcard_regfail(bus->card) && 914 (++(*retryvar) <= retry_limit)); 915 if (*retryvar) { 916 bus->regfails += (*retryvar-1); 917 if (*retryvar > retry_limit) 918 BRCMF_ERROR(("FAILED REGISTER WRITE" 919 " %Xh\n", reg_offset)); 920 } 921} 922 923#define BRCMF_BUS SDIO_BUS 924 925#define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND) 926 927#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) 928 929#ifdef SDTEST 930static void brcmf_sdbrcm_checkdied(struct brcmf_bus *bus, void *pkt, uint seq); 931static void brcmf_sdbrcm_sdtest_set(struct brcmf_bus *bus, bool start); 932#endif 933 934#ifdef BCMDBG 935static int brcmf_sdbrcm_bus_console_in(struct brcmf_pub *drvr, 936 unsigned char *msg, uint msglen); 937static int brcmf_sdbrcm_checkdied(struct brcmf_bus *bus, u8 *data, uint size); 938static int brcmf_sdbrcm_mem_dump(struct brcmf_bus *bus); 939#endif /* BCMDBG */ 940static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter); 941 942static void brcmf_sdbrcm_release(struct brcmf_bus *bus); 943static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus); 944static void brcmf_sdbrcm_disconnect(void *ptr); 945static bool brcmf_sdbrcm_chipmatch(u16 chipid); 946static bool brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, void *card, 947 u32 regsva, u16 devid); 948static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus, void *card); 949static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus, void *card); 950static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus); 951 952static uint brcmf_process_nvram_vars(char *varbuf, uint len); 953 954static void brcmf_sdbrcm_setmemsize(struct brcmf_bus *bus, int mem_size); 955static int brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, 956 uint flags, u8 *buf, uint nbytes, 957 struct sk_buff *pkt, 958 void (*complete)(void *handle, int status, 959 bool sync_waiting), 960 void *handle); 961 962static bool brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus, void *card); 963static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus); 964 965static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus); 966static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus); 967 968static void 969brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_card *card, u32 corebase); 970 971static int brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs); 972 973static void 974brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_card *card, u32 corebase); 975 976static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus, 977 u32 drivestrength); 978static void brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus); 979static void brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar); 980static void brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus); 981static void brcmf_sdbrcm_watchdog(unsigned long data); 982static int brcmf_sdbrcm_watchdog_thread(void *data); 983static int brcmf_sdbrcm_dpc_thread(void *data); 984static void brcmf_sdbrcm_dpc_tasklet(unsigned long data); 985static void brcmf_sdbrcm_sched_dpc(struct brcmf_bus *bus); 986static void brcmf_sdbrcm_sdlock(struct brcmf_bus *bus); 987static void brcmf_sdbrcm_sdunlock(struct brcmf_bus *bus); 988static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus); 989 990/* Packet free applicable unconditionally for sdio and sdspi. 991 * Conditional if bufpool was present for gspi bus. 992 */ 993static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt) 994{ 995 if ((bus->bus != SPI_BUS) || bus->usebufpool) 996 brcmu_pkt_buf_free_skb(pkt); 997} 998 999static void brcmf_sdbrcm_setmemsize(struct brcmf_bus *bus, int mem_size) 1000{ 1001 s32 min_size = DONGLE_MIN_MEMSIZE; 1002 /* Restrict the memsize to user specified limit */ 1003 BRCMF_ERROR(("user: Restrict the dongle ram size to %d, min %d\n", 1004 brcmf_dongle_memsize, min_size)); 1005 if ((brcmf_dongle_memsize > min_size) && 1006 (brcmf_dongle_memsize < (s32) bus->orig_ramsize)) 1007 bus->ramsize = brcmf_dongle_memsize; 1008} 1009 1010static int brcmf_sdbrcm_set_siaddr_window(struct brcmf_bus *bus, u32 address) 1011{ 1012 int err = 0; 1013 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW, 1014 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err); 1015 if (!err) 1016 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1, 1017 SBSDIO_FUNC1_SBADDRMID, 1018 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err); 1019 if (!err) 1020 brcmf_sdcard_cfg_write(bus->card, SDIO_FUNC_1, 1021 SBSDIO_FUNC1_SBADDRHIGH, 1022 (address >> 24) & SBSDIO_SBADDRHIGH_MASK, 1023 &err); 1024 return err; 1025} 1026 1027/* Turn backplane clock on or off */ 1028static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok) 1029{ 1030 int err; 1031 u8 clkctl, clkreq, devctl; 1032 struct brcmf_sdio_card *card; 1033 1034 BRCMF_TRACE(("%s: Enter\n", __func__)); 1035 1036 clkctl = 0; 1037 card = bus->card; 1038 1039 if (on) { 1040 /* Request HT Avail */ 1041 clkreq = 1042 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; 1043 1044 if ((bus->ci->chip == BCM4329_CHIP_ID) 1045 && (bus->ci->chiprev == 0)) 1046 clkreq |= SBSDIO_FORCE_ALP; 1047 1048 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, 1049 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err); 1050 if (err) { 1051 BRCMF_ERROR(("%s: HT Avail request error: %d\n", 1052 __func__, err)); 1053 return -EBADE; 1054 } 1055 1056 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID) 1057 && (bus->ci->buscorerev == 9))) { 1058 u32 dummy, retries; 1059 r_sdreg32(bus, &dummy, 1060 offsetof(struct sdpcmd_regs, clockctlstatus), 1061 &retries); 1062 } 1063 1064 /* Check current status */ 1065 clkctl = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1, 1066 SBSDIO_FUNC1_CHIPCLKCSR, &err); 1067 if (err) { 1068 BRCMF_ERROR(("%s: HT Avail read error: %d\n", 1069 __func__, err)); 1070 return -EBADE; 1071 } 1072 1073 /* Go to pending and await interrupt if appropriate */ 1074 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { 1075 /* Allow only clock-available interrupt */ 1076 devctl = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1, 1077 SBSDIO_DEVICE_CTL, &err); 1078 if (err) { 1079 BRCMF_ERROR(("%s: Devctl error setting CA:" 1080 " %d\n", __func__, err)); 1081 return -EBADE; 1082 } 1083 1084 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; 1085 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, 1086 SBSDIO_DEVICE_CTL, devctl, &err); 1087 BRCMF_INFO(("CLKCTL: set PENDING\n")); 1088 bus->clkstate = CLK_PENDING; 1089 1090 return 0; 1091 } else if (bus->clkstate == CLK_PENDING) { 1092 /* Cancel CA-only interrupt filter */ 1093 devctl = 1094 brcmf_sdcard_cfg_read(card, SDIO_FUNC_1, 1095 SBSDIO_DEVICE_CTL, &err); 1096 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 1097 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, 1098 SBSDIO_DEVICE_CTL, devctl, &err); 1099 } 1100 1101 /* Otherwise, wait here (polling) for HT Avail */ 1102 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 1103 BRCMF_SPINWAIT_SLEEP(sdioh_spinwait_sleep, 1104 ((clkctl = 1105 brcmf_sdcard_cfg_read(card, SDIO_FUNC_1, 1106 SBSDIO_FUNC1_CHIPCLKCSR, 1107 &err)), 1108 !SBSDIO_CLKAV(clkctl, bus->alp_only)), 1109 PMU_MAX_TRANSITION_DLY); 1110 } 1111 if (err) { 1112 BRCMF_ERROR(("%s: HT Avail request error: %d\n", 1113 __func__, err)); 1114 return -EBADE; 1115 } 1116 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 1117 BRCMF_ERROR(("%s: HT Avail timeout (%d): " 1118 "clkctl 0x%02x\n", __func__, 1119 PMU_MAX_TRANSITION_DLY, clkctl)); 1120 return -EBADE; 1121 } 1122 1123 /* Mark clock available */ 1124 bus->clkstate = CLK_AVAIL; 1125 BRCMF_INFO(("CLKCTL: turned ON\n")); 1126 1127#if defined(BCMDBG) 1128 if (bus->alp_only != true) { 1129 if (SBSDIO_ALPONLY(clkctl)) { 1130 BRCMF_ERROR(("%s: HT Clock should be on.\n", 1131 __func__)); 1132 } 1133 } 1134#endif /* defined (BCMDBG) */ 1135 1136 bus->activity = true; 1137 } else { 1138 clkreq = 0; 1139 1140 if (bus->clkstate == CLK_PENDING) { 1141 /* Cancel CA-only interrupt filter */ 1142 devctl = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1, 1143 SBSDIO_DEVICE_CTL, &err); 1144 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 1145 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, 1146 SBSDIO_DEVICE_CTL, devctl, &err); 1147 } 1148 1149 bus->clkstate = CLK_SDONLY; 1150 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, 1151 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err); 1152 BRCMF_INFO(("CLKCTL: turned OFF\n")); 1153 if (err) { 1154 BRCMF_ERROR(("%s: Failed access turning clock off:" 1155 " %d\n", __func__, err)); 1156 return -EBADE; 1157 } 1158 } 1159 return 0; 1160} 1161 1162/* Change idle/active SD state */ 1163static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on) 1164{ 1165 BRCMF_TRACE(("%s: Enter\n", __func__)); 1166 1167 if (on) 1168 bus->clkstate = CLK_SDONLY; 1169 else 1170 bus->clkstate = CLK_NONE; 1171 1172 return 0; 1173} 1174 1175/* Transition SD and backplane clock readiness */ 1176static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok) 1177{ 1178#ifdef BCMDBG 1179 uint oldstate = bus->clkstate; 1180#endif /* BCMDBG */ 1181 1182 BRCMF_TRACE(("%s: Enter\n", __func__)); 1183 1184 /* Early exit if we're already there */ 1185 if (bus->clkstate == target) { 1186 if (target == CLK_AVAIL) { 1187 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms); 1188 bus->activity = true; 1189 } 1190 return 0; 1191 } 1192 1193 switch (target) { 1194 case CLK_AVAIL: 1195 /* Make sure SD clock is available */ 1196 if (bus->clkstate == CLK_NONE) 1197 brcmf_sdbrcm_sdclk(bus, true); 1198 /* Now request HT Avail on the backplane */ 1199 brcmf_sdbrcm_htclk(bus, true, pendok); 1200 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms); 1201 bus->activity = true; 1202 break; 1203 1204 case CLK_SDONLY: 1205 /* Remove HT request, or bring up SD clock */ 1206 if (bus->clkstate == CLK_NONE) 1207 brcmf_sdbrcm_sdclk(bus, true); 1208 else if (bus->clkstate == CLK_AVAIL) 1209 brcmf_sdbrcm_htclk(bus, false, false); 1210 else 1211 BRCMF_ERROR(("brcmf_sdbrcm_clkctl: request for %d -> %d" 1212 "\n", bus->clkstate, target)); 1213 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms); 1214 break; 1215 1216 case CLK_NONE: 1217 /* Make sure to remove HT request */ 1218 if (bus->clkstate == CLK_AVAIL) 1219 brcmf_sdbrcm_htclk(bus, false, false); 1220 /* Now remove the SD clock */ 1221 brcmf_sdbrcm_sdclk(bus, false); 1222 brcmf_sdbrcm_wd_timer(bus, 0); 1223 break; 1224 } 1225#ifdef BCMDBG 1226 BRCMF_INFO(("brcmf_sdbrcm_clkctl: %d -> %d\n", 1227 oldstate, bus->clkstate)); 1228#endif /* BCMDBG */ 1229 1230 return 0; 1231} 1232 1233int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep) 1234{ 1235 struct brcmf_sdio_card *card = bus->card; 1236 uint retries = 0; 1237 1238 BRCMF_INFO(("brcmf_sdbrcm_bussleep: request %s (currently %s)\n", 1239 (sleep ? "SLEEP" : "WAKE"), 1240 (bus->sleeping ? "SLEEP" : "WAKE"))); 1241 1242 /* Done if we're already in the requested state */ 1243 if (sleep == bus->sleeping) 1244 return 0; 1245 1246 /* Going to sleep: set the alarm and turn off the lights... */ 1247 if (sleep) { 1248 /* Don't sleep if something is pending */ 1249 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq)) 1250 return -EBUSY; 1251 1252 /* Disable SDIO interrupts (no longer interested) */ 1253 brcmf_sdcard_intr_disable(bus->card); 1254 1255 /* Make sure the controller has the bus up */ 1256 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); 1257 1258 /* Tell device to start using OOB wakeup */ 1259 w_sdreg32(bus, SMB_USE_OOB, 1260 offsetof(struct sdpcmd_regs, tosbmailbox), &retries); 1261 if (retries > retry_limit) 1262 BRCMF_ERROR(("CANNOT SIGNAL CHIP, " 1263 "WILL NOT WAKE UP!!\n")); 1264 1265 /* Turn off our contribution to the HT clock request */ 1266 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); 1267 1268 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, 1269 SBSDIO_FUNC1_CHIPCLKCSR, 1270 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL); 1271 1272 /* Isolate the bus */ 1273 if (bus->ci->chip != BCM4329_CHIP_ID 1274 && bus->ci->chip != BCM4319_CHIP_ID) { 1275 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, 1276 SBSDIO_DEVICE_CTL, 1277 SBSDIO_DEVCTL_PADS_ISO, NULL); 1278 } 1279 1280 /* Change state */ 1281 bus->sleeping = true; 1282 1283 } else { 1284 /* Waking up: bus power up is ok, set local state */ 1285 1286 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, 1287 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); 1288 1289 /* Force pad isolation off if possible 1290 (in case power never toggled) */ 1291 if ((bus->ci->buscoretype == PCMCIA_CORE_ID) 1292 && (bus->ci->buscorerev >= 10)) 1293 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, 1294 SBSDIO_DEVICE_CTL, 0, NULL); 1295 1296 /* Make sure the controller has the bus up */ 1297 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false); 1298 1299 /* Send misc interrupt to indicate OOB not needed */ 1300 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata), 1301 &retries); 1302 if (retries <= retry_limit) 1303 w_sdreg32(bus, SMB_DEV_INT, 1304 offsetof(struct sdpcmd_regs, tosbmailbox), 1305 &retries); 1306 1307 if (retries > retry_limit) 1308 BRCMF_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n")); 1309 1310 /* Make sure we have SD bus access */ 1311 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false); 1312 1313 /* Change state */ 1314 bus->sleeping = false; 1315 1316 /* Enable interrupts again */ 1317 if (bus->intr && (bus->drvr->busstate == BRCMF_BUS_DATA)) { 1318 bus->intdis = false; 1319 brcmf_sdcard_intr_enable(bus->card); 1320 } 1321 } 1322 1323 return 0; 1324} 1325 1326#define BUS_WAKE(bus) \ 1327 do { \ 1328 if ((bus)->sleeping) \ 1329 brcmf_sdbrcm_bussleep((bus), false); \ 1330 } while (0); 1331 1332/* Writes a HW/SW header into the packet and sends it. */ 1333/* Assumes: (a) header space already there, (b) caller holds lock */ 1334static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt, uint chan, 1335 bool free_pkt) 1336{ 1337 int ret; 1338 u8 *frame; 1339 u16 len, pad = 0; 1340 u32 swheader; 1341 uint retries = 0; 1342 struct brcmf_sdio_card *card; 1343 struct sk_buff *new; 1344 int i; 1345 1346 BRCMF_TRACE(("%s: Enter\n", __func__)); 1347 1348 card = bus->card; 1349 1350 if (bus->drvr->dongle_reset) { 1351 ret = -EPERM; 1352 goto done; 1353 } 1354 1355 frame = (u8 *) (pkt->data); 1356 1357 /* Add alignment padding, allocate new packet if needed */ 1358 pad = ((unsigned long)frame % BRCMF_SDALIGN); 1359 if (pad) { 1360 if (skb_headroom(pkt) < pad) { 1361 BRCMF_INFO(("%s: insufficient headroom %d for %d pad\n", 1362 __func__, skb_headroom(pkt), pad)); 1363 bus->drvr->tx_realloc++; 1364 new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN); 1365 if (!new) { 1366 BRCMF_ERROR(("%s: couldn't allocate new " 1367 "%d-byte packet\n", __func__, 1368 pkt->len + BRCMF_SDALIGN)); 1369 ret = -ENOMEM; 1370 goto done; 1371 } 1372 1373 PKTALIGN(new, pkt->len, BRCMF_SDALIGN); 1374 memcpy(new->data, pkt->data, pkt->len); 1375 if (free_pkt) 1376 brcmu_pkt_buf_free_skb(pkt); 1377 /* free the pkt if canned one is not used */ 1378 free_pkt = true; 1379 pkt = new; 1380 frame = (u8 *) (pkt->data); 1381 /* precondition: (frame % BRCMF_SDALIGN) == 0) */ 1382 pad = 0; 1383 } else { 1384 skb_push(pkt, pad); 1385 frame = (u8 *) (pkt->data); 1386 /* precondition: pad + SDPCM_HDRLEN <= pkt->len */ 1387 memset(frame, 0, pad + SDPCM_HDRLEN); 1388 } 1389 } 1390 /* precondition: pad < BRCMF_SDALIGN */ 1391 1392 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */ 1393 len = (u16) (pkt->len); 1394 *(u16 *) frame = cpu_to_le16(len); 1395 *(((u16 *) frame) + 1) = cpu_to_le16(~len); 1396 1397 /* Software tag: channel, sequence number, data offset */ 1398 swheader = 1399 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq | 1400 (((pad + 1401 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK); 1402 1403 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN); 1404 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader)); 1405 1406#ifdef BCMDBG 1407 tx_packets[pkt->priority]++; 1408 if (BRCMF_BYTES_ON() && 1409 (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) || 1410 (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) { 1411 printk(KERN_DEBUG "Tx Frame:\n"); 1412 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len); 1413 } else if (BRCMF_HDRS_ON()) { 1414 printk(KERN_DEBUG "TxHdr:\n"); 1415 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, 1416 frame, min_t(u16, len, 16)); 1417 } 1418#endif 1419 1420 /* Raise len to next SDIO block to eliminate tail command */ 1421 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { 1422 u16 pad = bus->blocksize - (len % bus->blocksize); 1423 if ((pad <= bus->roundup) && (pad < bus->blocksize)) 1424 len += pad; 1425 } else if (len % BRCMF_SDALIGN) { 1426 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN); 1427 } 1428 1429 /* Some controllers have trouble with odd bytes -- round to even */ 1430 if (forcealign && (len & (ALIGNMENT - 1))) { 1431 len = roundup(len, ALIGNMENT); 1432 } 1433 1434 do { 1435 ret = brcmf_sdbrcm_send_buf(bus, brcmf_sdcard_cur_sbwad(card), 1436 SDIO_FUNC_2, F2SYNC, frame, len, pkt, NULL, NULL); 1437 bus->f2txdata++; 1438 1439 if (ret < 0) { 1440 /* On failure, abort the command 1441 and terminate the frame */ 1442 BRCMF_INFO(("%s: sdio error %d, abort command and " 1443 "terminate frame.\n", __func__, ret)); 1444 bus->tx_sderrs++; 1445 1446 brcmf_sdcard_abort(card, SDIO_FUNC_2); 1447 brcmf_sdcard_cfg_write(card, SDIO_FUNC_1, 1448 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, 1449 NULL); 1450 bus->f1regdata++; 1451 1452 for (i = 0; i < 3; i++) { 1453 u8 hi, lo; 1454 hi = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1, 1455 SBSDIO_FUNC1_WFRAMEBCHI, 1456 NULL); 1457 lo = brcmf_sdcard_cfg_read(card, SDIO_FUNC_1, 1458 SBSDIO_FUNC1_WFRAMEBCLO, 1459 NULL); 1460 bus->f1regdata += 2; 1461 if ((hi == 0) && (lo == 0)) 1462 break; 1463 } 1464 1465 } 1466 if (ret == 0) 1467 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP; 1468 1469 } while ((ret < 0) && retrydata && retries++ < TXRETRIES); 1470 1471done: 1472 /* restore pkt buffer pointer before calling tx complete routine */ 1473 skb_pull(pkt, SDPCM_HDRLEN + pad); 1474 brcmf_sdbrcm_sdunlock(bus); 1475 brcmf_txcomplete(bus->drvr, pkt, ret != 0); 1476 brcmf_sdbrcm_sdlock(bus); 1477 1478 if (free_pkt) 1479 brcmu_pkt_buf_free_skb(pkt); 1480 1481 return ret; 1482} 1483 1484int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt) 1485{ 1486 int ret = -EBADE; 1487 uint datalen, prec; 1488 1489 BRCMF_TRACE(("%s: Enter\n", __func__)); 1490 1491 datalen = pkt->len; 1492 1493#ifdef SDTEST 1494 /* Push the test header if doing loopback */ 1495 if (bus->ext_loop) { 1496 u8 *data; 1497 skb_push(pkt, SDPCM_TEST_HDRLEN); 1498 data = pkt->data; 1499 *data++ = SDPCM_TEST_ECHOREQ; 1500 *data++ = (u8) bus->loopid++; 1501 *data++ = (datalen >> 0); 1502 *data++ = (datalen >> 8); 1503 datalen += SDPCM_TEST_HDRLEN; 1504 } 1505#endif /* SDTEST */ 1506 1507 /* Add space for the header */ 1508 skb_push(pkt, SDPCM_HDRLEN); 1509 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ 1510 1511 prec = PRIO2PREC((pkt->priority & PRIOMASK)); 1512 1513 /* Check for existing queue, current flow-control, 1514 pending event, or pending clock */ 1515 if (brcmf_deferred_tx || bus->fcstate || pktq_len(&bus->txq) 1516 || bus->dpc_sched || (!DATAOK(bus)) 1517 || (bus->flowcontrol & NBITVAL(prec)) 1518 || (bus->clkstate != CLK_AVAIL)) { 1519 BRCMF_TRACE(("%s: deferring pktq len %d\n", __func__, 1520 pktq_len(&bus->txq))); 1521 bus->fcqueued++; 1522 1523 /* Priority based enq */ 1524 spin_lock_bh(&bus->txqlock); 1525 if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) { 1526 skb_pull(pkt, SDPCM_HDRLEN); 1527 brcmf_txcomplete(bus->drvr, pkt, false); 1528 brcmu_pkt_buf_free_skb(pkt); 1529 BRCMF_ERROR(("%s: out of bus->txq !!!\n", __func__)); 1530 ret = -ENOSR; 1531 } else { 1532 ret = 0; 1533 } 1534 spin_unlock_bh(&bus->txqlock); 1535 1536 if (pktq_len(&bus->txq) >= TXHI) 1537 brcmf_txflowcontrol(bus->drvr, 0, ON); 1538 1539#ifdef BCMDBG 1540 if (pktq_plen(&bus->txq, prec) > qcount[prec]) 1541 qcount[prec] = pktq_plen(&bus->txq, prec); 1542#endif 1543 /* Schedule DPC if needed to send queued packet(s) */ 1544 if (brcmf_deferred_tx && !bus->dpc_sched) { 1545 bus->dpc_sched = true; 1546 brcmf_sdbrcm_sched_dpc(bus); 1547 } 1548 } else { 1549 /* Lock: we're about to use shared data/code (and SDIO) */ 1550 brcmf_sdbrcm_sdlock(bus); 1551 1552 /* Otherwise, send it now */ 1553 BUS_WAKE(bus); 1554 /* Make sure back plane ht clk is on, no pending allowed */ 1555 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true); 1556 1557#ifndef SDTEST 1558 BRCMF_TRACE(("%s: calling txpkt\n", __func__)); 1559 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true); 1560#else 1561 ret = brcmf_sdbrcm_txpkt(bus, pkt, 1562 (bus->ext_loop ? SDPCM_TEST_CHANNEL : 1563 SDPCM_DATA_CHANNEL), true); 1564#endif 1565 if (ret) 1566 bus->drvr->tx_errors++; 1567 else 1568 bus->drvr->dstats.tx_bytes += datalen; 1569 1570 if (bus->idletime == BRCMF_IDLE_IMMEDIATE && 1571 !bus->dpc_sched) { 1572 bus->activity = false; 1573 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true); 1574 } 1575 1576 brcmf_sdbrcm_sdunlock(bus); 1577 } 1578 1579 return ret; 1580} 1581 1582static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes) 1583{ 1584 struct sk_buff *pkt; 1585 u32 intstatus = 0; 1586 uint retries = 0; 1587 int ret = 0, prec_out; 1588 uint cnt = 0; 1589 uint datalen; 1590 u8 tx_prec_map; 1591 1592 struct brcmf_pub *drvr = bus->drvr; 1593 1594 BRCMF_TRACE(("%s: Enter\n", __func__)); 1595 1596 tx_prec_map = ~bus->flowcontrol; 1597 1598 /* Send frames until the limit or some other event */ 1599 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) { 1600 spin_lock_bh(&bus->txqlock); 1601 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out); 1602 if (pkt == NULL) { 1603 spin_unlock_bh(&bus->txqlock); 1604 break; 1605 } 1606 spin_unlock_bh(&bus->txqlock); 1607 datalen = pkt->len - SDPCM_HDRLEN; 1608 1609#ifndef SDTEST 1610 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true); 1611#else 1612 ret = brcmf_sdbrcm_txpkt(bus, pkt, 1613 (bus->ext_loop ? SDPCM_TEST_CHANNEL : 1614 SDPCM_DATA_CHANNEL), true); 1615#endif 1616 if (ret) 1617 bus->drvr->tx_errors++; 1618 else 1619 bus->drvr->dstats.tx_bytes += datalen; 1620 1621 /* In poll mode, need to check for other events */ 1622 if (!bus->intr && cnt) { 1623 /* Check device status, signal pending interrupt */ 1624 r_sdreg32(bus, &intstatus, 1625 offsetof(struct sdpcmd_regs, intstatus), 1626 &retries); 1627 bus->f2txdata++; 1628 if (brcmf_sdcard_regfail(bus->card)) 1629 break; 1630 if (intstatus & bus->hostintmask) 1631 bus->ipend = true; 1632 } 1633 } 1634 1635 /* Deflow-control stack if needed */ 1636 if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) && 1637 drvr->txoff && (pktq_len(&bus->txq) < TXLOW)) 1638 brcmf_txflowcontrol(drvr, 0, OFF); 1639 1640 return cnt; 1641} 1642 1643int 1644brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen) 1645{ 1646 u8 *frame; 1647 u16 len; 1648 u32 swheader; 1649 uint retries = 0; 1650 struct brcmf_sdio_card *card = bus->card; 1651 u8 doff = 0; 1652 int ret = -1; 1653 int i; 1654 1655 BRCMF_TRACE(("%s: Enter\n", __func__)); 1656 1657 if (bus->drvr->dongle_reset) 1658 return -EIO; 1659 1660 /* Back the pointer to make a room for bus header */ 1661 frame = msg - SDPCM_HDRLEN; 1662 len = (msglen += SDPCM_HDRLEN); 1663 1664 /* Add alignme…
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