/drivers/net/sky2.h
C Header | 2427 lines | 1871 code | 338 blank | 218 comment | 4 complexity | 24259ddd6a6cd9d49e88976d4a70aea1 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
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1/* 2 * Definitions for the new Marvell Yukon 2 driver. 3 */ 4#ifndef _SKY2_H 5#define _SKY2_H 6 7#define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */ 8 9/* PCI config registers */ 10enum { 11 PCI_DEV_REG1 = 0x40, 12 PCI_DEV_REG2 = 0x44, 13 PCI_DEV_STATUS = 0x7c, 14 PCI_DEV_REG3 = 0x80, 15 PCI_DEV_REG4 = 0x84, 16 PCI_DEV_REG5 = 0x88, 17 PCI_CFG_REG_0 = 0x90, 18 PCI_CFG_REG_1 = 0x94, 19 20 PSM_CONFIG_REG0 = 0x98, 21 PSM_CONFIG_REG1 = 0x9C, 22 PSM_CONFIG_REG2 = 0x160, 23 PSM_CONFIG_REG3 = 0x164, 24 PSM_CONFIG_REG4 = 0x168, 25 26}; 27 28/* Yukon-2 */ 29enum pci_dev_reg_1 { 30 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ 31 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */ 32 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */ 33 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */ 34 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */ 35 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */ 36 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */ 37 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */ 38 39 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */ 40 PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */ 41 PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */ 42 PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */ 43}; 44 45enum pci_dev_reg_2 { 46 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */ 47 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */ 48 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */ 49 50 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */ 51 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */ 52 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */ 53 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */ 54 55 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */ 56}; 57 58/* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */ 59enum pci_dev_reg_3 { 60 P_CLK_ASF_REGS_DIS = 1<<18,/* Disable Clock ASF (Yukon-Ext.) */ 61 P_CLK_COR_REGS_D0_DIS = 1<<17,/* Disable Clock Core Regs D0 */ 62 P_CLK_MACSEC_DIS = 1<<17,/* Disable Clock MACSec (Yukon-Ext.) */ 63 P_CLK_PCI_REGS_D0_DIS = 1<<16,/* Disable Clock PCI Regs D0 */ 64 P_CLK_COR_YTB_ARB_DIS = 1<<15,/* Disable Clock YTB Arbiter */ 65 P_CLK_MAC_LNK1_D3_DIS = 1<<14,/* Disable Clock MAC Link1 D3 */ 66 P_CLK_COR_LNK1_D0_DIS = 1<<13,/* Disable Clock Core Link1 D0 */ 67 P_CLK_MAC_LNK1_D0_DIS = 1<<12,/* Disable Clock MAC Link1 D0 */ 68 P_CLK_COR_LNK1_D3_DIS = 1<<11,/* Disable Clock Core Link1 D3 */ 69 P_CLK_PCI_MST_ARB_DIS = 1<<10,/* Disable Clock PCI Master Arb. */ 70 P_CLK_COR_REGS_D3_DIS = 1<<9, /* Disable Clock Core Regs D3 */ 71 P_CLK_PCI_REGS_D3_DIS = 1<<8, /* Disable Clock PCI Regs D3 */ 72 P_CLK_REF_LNK1_GM_DIS = 1<<7, /* Disable Clock Ref. Link1 GMAC */ 73 P_CLK_COR_LNK1_GM_DIS = 1<<6, /* Disable Clock Core Link1 GMAC */ 74 P_CLK_PCI_COMMON_DIS = 1<<5, /* Disable Clock PCI Common */ 75 P_CLK_COR_COMMON_DIS = 1<<4, /* Disable Clock Core Common */ 76 P_CLK_PCI_LNK1_BMU_DIS = 1<<3, /* Disable Clock PCI Link1 BMU */ 77 P_CLK_COR_LNK1_BMU_DIS = 1<<2, /* Disable Clock Core Link1 BMU */ 78 P_CLK_PCI_LNK1_BIU_DIS = 1<<1, /* Disable Clock PCI Link1 BIU */ 79 P_CLK_COR_LNK1_BIU_DIS = 1<<0, /* Disable Clock Core Link1 BIU */ 80 PCIE_OUR3_WOL_D3_COLD_SET = P_CLK_ASF_REGS_DIS | 81 P_CLK_COR_REGS_D0_DIS | 82 P_CLK_COR_LNK1_D0_DIS | 83 P_CLK_MAC_LNK1_D0_DIS | 84 P_CLK_PCI_MST_ARB_DIS | 85 P_CLK_COR_COMMON_DIS | 86 P_CLK_COR_LNK1_BMU_DIS, 87}; 88 89/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ 90enum pci_dev_reg_4 { 91 /* (Link Training & Status State Machine) */ 92 P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */ 93#define P_PEX_LTSSM_STAT(x) ((x << 25) & P_PEX_LTSSM_STAT_MSK) 94 P_PEX_LTSSM_L1_STAT = 0x34, 95 P_PEX_LTSSM_DET_STAT = 0x01, 96 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */ 97 /* (Active State Power Management) */ 98 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */ 99 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */ 100 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */ 101 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */ 102 103 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */ 104 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */ 105 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */ 106 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */ 107 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */ 108 P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN 109 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY, 110}; 111 112/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ 113enum pci_dev_reg_5 { 114 /* Bit 31..27: for A3 & later */ 115 P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */ 116 P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */ 117 P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */ 118 P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */ 119 /* Bit 26..16: Release Clock on Event */ 120 P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */ 121 P_REL_GPHY_REC_PACKET = 1<<25, /* GPHY Received Packet */ 122 P_REL_INT_FIFO_N_EMPTY = 1<<24, /* Internal FIFO Not Empty */ 123 P_REL_MAIN_PWR_AVAIL = 1<<23, /* Main Power Available */ 124 P_REL_CLKRUN_REQ_REL = 1<<22, /* CLKRUN Request Release */ 125 P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */ 126 P_REL_PME_ASSERTED = 1<<20, /* PME Asserted */ 127 P_REL_PCIE_EXIT_L1_ST = 1<<19, /* PCIe Exit L1 State */ 128 P_REL_LOADER_NOT_FIN = 1<<18, /* EPROM Loader Not Finished */ 129 P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */ 130 P_REL_GPHY_LINK_UP = 1<<16, /* GPHY Link Up */ 131 132 /* Bit 10.. 0: Mask for Gate Clock */ 133 P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */ 134 P_GAT_GPHY_N_REC_PACKET = 1<<9, /* GPHY Not Received Packet */ 135 P_GAT_INT_FIFO_EMPTY = 1<<8, /* Internal FIFO Empty */ 136 P_GAT_MAIN_PWR_N_AVAIL = 1<<7, /* Main Power Not Available */ 137 P_GAT_CLKRUN_REQ_REL = 1<<6, /* CLKRUN Not Requested */ 138 P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */ 139 P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */ 140 P_GAT_PCIE_ENTER_L1_ST = 1<<3, /* PCIe Enter L1 State */ 141 P_GAT_LOADER_FINISHED = 1<<2, /* EPROM Loader Finished */ 142 P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */ 143 P_GAT_GPHY_LINK_DOWN = 1<<0, /* GPHY Link Down */ 144 145 PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET | 146 P_REL_INT_FIFO_N_EMPTY | 147 P_REL_PCIE_EXIT_L1_ST | 148 P_REL_PCIE_RX_EX_IDLE | 149 P_GAT_GPHY_N_REC_PACKET | 150 P_GAT_INT_FIFO_EMPTY | 151 P_GAT_PCIE_ENTER_L1_ST | 152 P_GAT_PCIE_RX_EL_IDLE, 153}; 154 155/* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */ 156enum pci_cfg_reg1 { 157 P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */ 158 /* Bit 23..21: Release Clock on Event */ 159 P_CF1_REL_LDR_NOT_FIN = 1<<23, /* EEPROM Loader Not Finished */ 160 P_CF1_REL_VMAIN_AVLBL = 1<<22, /* Vmain available */ 161 P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */ 162 /* Bit 20..18: Gate Clock on Event */ 163 P_CF1_GAT_LDR_NOT_FIN = 1<<20, /* EEPROM Loader Finished */ 164 P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */ 165 P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */ 166 P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */ 167 P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */ 168 169 P_CF1_ENA_CFG_LDR_DONE = 1<<8, /* Enable core level Config loader done */ 170 171 P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */ 172 P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */ 173 174 PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST | 175 P_CF1_REL_LDR_NOT_FIN | 176 P_CF1_REL_VMAIN_AVLBL | 177 P_CF1_REL_PCIE_RESET | 178 P_CF1_GAT_LDR_NOT_FIN | 179 P_CF1_GAT_PCIE_RESET | 180 P_CF1_PRST_PHY_CLKREQ | 181 P_CF1_ENA_CFG_LDR_DONE | 182 P_CF1_ENA_TXBMU_RD_IDLE | 183 P_CF1_ENA_TXBMU_WR_IDLE, 184}; 185 186/* Yukon-Optima */ 187enum { 188 PSM_CONFIG_REG1_AC_PRESENT_STATUS = 1<<31, /* AC Present Status */ 189 190 PSM_CONFIG_REG1_PTP_CLK_SEL = 1<<29, /* PTP Clock Select */ 191 PSM_CONFIG_REG1_PTP_MODE = 1<<28, /* PTP Mode */ 192 193 PSM_CONFIG_REG1_MUX_PHY_LINK = 1<<27, /* PHY Energy Detect Event */ 194 195 PSM_CONFIG_REG1_EN_PIN63_AC_PRESENT = 1<<26, /* Enable LED_DUPLEX for ac_present */ 196 PSM_CONFIG_REG1_EN_PCIE_TIMER = 1<<25, /* Enable PCIe Timer */ 197 PSM_CONFIG_REG1_EN_SPU_TIMER = 1<<24, /* Enable SPU Timer */ 198 PSM_CONFIG_REG1_POLARITY_AC_PRESENT = 1<<23, /* AC Present Polarity */ 199 200 PSM_CONFIG_REG1_EN_AC_PRESENT = 1<<21, /* Enable AC Present */ 201 202 PSM_CONFIG_REG1_EN_GPHY_INT_PSM = 1<<20, /* Enable GPHY INT for PSM */ 203 PSM_CONFIG_REG1_DIS_PSM_TIMER = 1<<19, /* Disable PSM Timer */ 204}; 205 206/* Yukon-Supreme */ 207enum { 208 PSM_CONFIG_REG1_GPHY_ENERGY_STS = 1<<31, /* GPHY Energy Detect Status */ 209 210 PSM_CONFIG_REG1_UART_MODE_MSK = 3<<29, /* UART_Mode */ 211 PSM_CONFIG_REG1_CLK_RUN_ASF = 1<<28, /* Enable Clock Free Running for ASF Subsystem */ 212 PSM_CONFIG_REG1_UART_CLK_DISABLE= 1<<27, /* Disable UART clock */ 213 PSM_CONFIG_REG1_VAUX_ONE = 1<<26, /* Tie internal Vaux to 1'b1 */ 214 PSM_CONFIG_REG1_UART_FC_RI_VAL = 1<<25, /* Default value for UART_RI_n */ 215 PSM_CONFIG_REG1_UART_FC_DCD_VAL = 1<<24, /* Default value for UART_DCD_n */ 216 PSM_CONFIG_REG1_UART_FC_DSR_VAL = 1<<23, /* Default value for UART_DSR_n */ 217 PSM_CONFIG_REG1_UART_FC_CTS_VAL = 1<<22, /* Default value for UART_CTS_n */ 218 PSM_CONFIG_REG1_LATCH_VAUX = 1<<21, /* Enable Latch current Vaux_avlbl */ 219 PSM_CONFIG_REG1_FORCE_TESTMODE_INPUT= 1<<20, /* Force Testmode pin as input PAD */ 220 PSM_CONFIG_REG1_UART_RST = 1<<19, /* UART_RST */ 221 PSM_CONFIG_REG1_PSM_PCIE_L1_POL = 1<<18, /* PCIE L1 Event Polarity for PSM */ 222 PSM_CONFIG_REG1_TIMER_STAT = 1<<17, /* PSM Timer Status */ 223 PSM_CONFIG_REG1_GPHY_INT = 1<<16, /* GPHY INT Status */ 224 PSM_CONFIG_REG1_FORCE_TESTMODE_ZERO= 1<<15, /* Force internal Testmode as 1'b0 */ 225 PSM_CONFIG_REG1_EN_INT_ASPM_CLKREQ = 1<<14, /* ENABLE INT for CLKRUN on ASPM and CLKREQ */ 226 PSM_CONFIG_REG1_EN_SND_TASK_ASPM_CLKREQ = 1<<13, /* ENABLE Snd_task for CLKRUN on ASPM and CLKREQ */ 227 PSM_CONFIG_REG1_DIS_CLK_GATE_SND_TASK = 1<<12, /* Disable CLK_GATE control snd_task */ 228 PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA = 1<<11, /* Disable flip-flop chain for sndmsg_inta */ 229 230 PSM_CONFIG_REG1_DIS_LOADER = 1<<9, /* Disable Loader SM after PSM Goes back to IDLE */ 231 PSM_CONFIG_REG1_DO_PWDN = 1<<8, /* Do Power Down, Start PSM Scheme */ 232 PSM_CONFIG_REG1_DIS_PIG = 1<<7, /* Disable Plug-in-Go SM after PSM Goes back to IDLE */ 233 PSM_CONFIG_REG1_DIS_PERST = 1<<6, /* Disable Internal PCIe Reset after PSM Goes back to IDLE */ 234 PSM_CONFIG_REG1_EN_REG18_PD = 1<<5, /* Enable REG18 Power Down for PSM */ 235 PSM_CONFIG_REG1_EN_PSM_LOAD = 1<<4, /* Disable EEPROM Loader after PSM Goes back to IDLE */ 236 PSM_CONFIG_REG1_EN_PSM_HOT_RST = 1<<3, /* Enable PCIe Hot Reset for PSM */ 237 PSM_CONFIG_REG1_EN_PSM_PERST = 1<<2, /* Enable PCIe Reset Event for PSM */ 238 PSM_CONFIG_REG1_EN_PSM_PCIE_L1 = 1<<1, /* Enable PCIe L1 Event for PSM */ 239 PSM_CONFIG_REG1_EN_PSM = 1<<0, /* Enable PSM Scheme */ 240}; 241 242/* PSM_CONFIG_REG4 0x0168 PSM Config Register 4 */ 243enum { 244 /* PHY Link Detect Timer */ 245 PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_MSK = 0xf<<4, 246 PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE = 4, 247 248 PSM_CONFIG_REG4_DEBUG_TIMER = 1<<1, /* Debug Timer */ 249 PSM_CONFIG_REG4_RST_PHY_LINK_DETECT = 1<<0, /* Reset GPHY Link Detect */ 250}; 251 252 253#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 254 PCI_STATUS_SIG_SYSTEM_ERROR | \ 255 PCI_STATUS_REC_MASTER_ABORT | \ 256 PCI_STATUS_REC_TARGET_ABORT | \ 257 PCI_STATUS_PARITY) 258 259enum csr_regs { 260 B0_RAP = 0x0000, 261 B0_CTST = 0x0004, 262 263 B0_POWER_CTRL = 0x0007, 264 B0_ISRC = 0x0008, 265 B0_IMSK = 0x000c, 266 B0_HWE_ISRC = 0x0010, 267 B0_HWE_IMSK = 0x0014, 268 269 /* Special ISR registers (Yukon-2 only) */ 270 B0_Y2_SP_ISRC2 = 0x001c, 271 B0_Y2_SP_ISRC3 = 0x0020, 272 B0_Y2_SP_EISR = 0x0024, 273 B0_Y2_SP_LISR = 0x0028, 274 B0_Y2_SP_ICR = 0x002c, 275 276 B2_MAC_1 = 0x0100, 277 B2_MAC_2 = 0x0108, 278 B2_MAC_3 = 0x0110, 279 B2_CONN_TYP = 0x0118, 280 B2_PMD_TYP = 0x0119, 281 B2_MAC_CFG = 0x011a, 282 B2_CHIP_ID = 0x011b, 283 B2_E_0 = 0x011c, 284 285 B2_Y2_CLK_GATE = 0x011d, 286 B2_Y2_HW_RES = 0x011e, 287 B2_E_3 = 0x011f, 288 B2_Y2_CLK_CTRL = 0x0120, 289 290 B2_TI_INI = 0x0130, 291 B2_TI_VAL = 0x0134, 292 B2_TI_CTRL = 0x0138, 293 B2_TI_TEST = 0x0139, 294 295 B2_TST_CTRL1 = 0x0158, 296 B2_TST_CTRL2 = 0x0159, 297 B2_GP_IO = 0x015c, 298 299 B2_I2C_CTRL = 0x0160, 300 B2_I2C_DATA = 0x0164, 301 B2_I2C_IRQ = 0x0168, 302 B2_I2C_SW = 0x016c, 303 304 Y2_PEX_PHY_DATA = 0x0170, 305 Y2_PEX_PHY_ADDR = 0x0172, 306 307 B3_RAM_ADDR = 0x0180, 308 B3_RAM_DATA_LO = 0x0184, 309 B3_RAM_DATA_HI = 0x0188, 310 311/* RAM Interface Registers */ 312/* Yukon-2: use RAM_BUFFER() to access the RAM buffer */ 313/* 314 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are 315 * not usable in SW. Please notice these are NOT real timeouts, these are 316 * the number of qWords transferred continuously. 317 */ 318#define RAM_BUFFER(port, reg) (reg | (port <<6)) 319 320 B3_RI_WTO_R1 = 0x0190, 321 B3_RI_WTO_XA1 = 0x0191, 322 B3_RI_WTO_XS1 = 0x0192, 323 B3_RI_RTO_R1 = 0x0193, 324 B3_RI_RTO_XA1 = 0x0194, 325 B3_RI_RTO_XS1 = 0x0195, 326 B3_RI_WTO_R2 = 0x0196, 327 B3_RI_WTO_XA2 = 0x0197, 328 B3_RI_WTO_XS2 = 0x0198, 329 B3_RI_RTO_R2 = 0x0199, 330 B3_RI_RTO_XA2 = 0x019a, 331 B3_RI_RTO_XS2 = 0x019b, 332 B3_RI_TO_VAL = 0x019c, 333 B3_RI_CTRL = 0x01a0, 334 B3_RI_TEST = 0x01a2, 335 B3_MA_TOINI_RX1 = 0x01b0, 336 B3_MA_TOINI_RX2 = 0x01b1, 337 B3_MA_TOINI_TX1 = 0x01b2, 338 B3_MA_TOINI_TX2 = 0x01b3, 339 B3_MA_TOVAL_RX1 = 0x01b4, 340 B3_MA_TOVAL_RX2 = 0x01b5, 341 B3_MA_TOVAL_TX1 = 0x01b6, 342 B3_MA_TOVAL_TX2 = 0x01b7, 343 B3_MA_TO_CTRL = 0x01b8, 344 B3_MA_TO_TEST = 0x01ba, 345 B3_MA_RCINI_RX1 = 0x01c0, 346 B3_MA_RCINI_RX2 = 0x01c1, 347 B3_MA_RCINI_TX1 = 0x01c2, 348 B3_MA_RCINI_TX2 = 0x01c3, 349 B3_MA_RCVAL_RX1 = 0x01c4, 350 B3_MA_RCVAL_RX2 = 0x01c5, 351 B3_MA_RCVAL_TX1 = 0x01c6, 352 B3_MA_RCVAL_TX2 = 0x01c7, 353 B3_MA_RC_CTRL = 0x01c8, 354 B3_MA_RC_TEST = 0x01ca, 355 B3_PA_TOINI_RX1 = 0x01d0, 356 B3_PA_TOINI_RX2 = 0x01d4, 357 B3_PA_TOINI_TX1 = 0x01d8, 358 B3_PA_TOINI_TX2 = 0x01dc, 359 B3_PA_TOVAL_RX1 = 0x01e0, 360 B3_PA_TOVAL_RX2 = 0x01e4, 361 B3_PA_TOVAL_TX1 = 0x01e8, 362 B3_PA_TOVAL_TX2 = 0x01ec, 363 B3_PA_CTRL = 0x01f0, 364 B3_PA_TEST = 0x01f2, 365 366 Y2_CFG_SPC = 0x1c00, /* PCI config space region */ 367 Y2_CFG_AER = 0x1d00, /* PCI Advanced Error Report region */ 368}; 369 370/* B0_CTST 24 bit Control/Status register */ 371enum { 372 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */ 373 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */ 374 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */ 375 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */ 376 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */ 377 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */ 378 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */ 379 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */ 380 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */ 381 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */ 382 383 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */ 384 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */ 385 CS_STOP_DONE = 1<<5, /* Stop Master is finished */ 386 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */ 387 CS_MRST_CLR = 1<<3, /* Clear Master reset */ 388 CS_MRST_SET = 1<<2, /* Set Master reset */ 389 CS_RST_CLR = 1<<1, /* Clear Software reset */ 390 CS_RST_SET = 1, /* Set Software reset */ 391}; 392 393/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ 394enum { 395 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */ 396 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */ 397 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */ 398 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */ 399 PC_VAUX_ON = 1<<3, /* Switch VAUX On */ 400 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */ 401 PC_VCC_ON = 1<<1, /* Switch VCC On */ 402 PC_VCC_OFF = 1<<0, /* Switch VCC Off */ 403}; 404 405/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ 406 407/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ 408/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ 409/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ 410/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ 411enum { 412 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */ 413 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */ 414 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */ 415 Y2_IS_CPU_TO = 1<<28, /* CPU Timeout */ 416 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */ 417 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */ 418 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */ 419 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */ 420 421 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */ 422 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */ 423 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */ 424 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */ 425 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */ 426 427 Y2_IS_PSM_ACK = 1<<7, /* PSM Acknowledge (Yukon-Optima only) */ 428 Y2_IS_PTP_TIST = 1<<6, /* PTP Time Stamp (Yukon-Optima only) */ 429 Y2_IS_PHY_QLNK = 1<<5, /* PHY Quick Link (Yukon-Optima only) */ 430 431 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */ 432 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */ 433 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */ 434 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */ 435 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */ 436 437 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU, 438 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 439 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1, 440 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 441 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2, 442 Y2_IS_ERROR = Y2_IS_HW_ERR | 443 Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 | 444 Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2, 445}; 446 447/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ 448enum { 449 IS_ERR_MSK = 0x00003fff,/* All Error bits */ 450 451 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */ 452 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */ 453 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */ 454 IS_IRQ_STAT = 1<<10, /* IRQ status exception */ 455 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */ 456 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */ 457 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */ 458 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */ 459 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */ 460 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */ 461 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */ 462 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */ 463 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */ 464 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */ 465}; 466 467/* Hardware error interrupt mask for Yukon 2 */ 468enum { 469 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */ 470 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */ 471 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */ 472 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */ 473 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */ 474 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */ 475 /* Link 2 */ 476 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */ 477 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */ 478 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */ 479 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */ 480 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */ 481 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */ 482 /* Link 1 */ 483 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */ 484 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */ 485 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */ 486 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */ 487 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */ 488 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */ 489 490 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 | 491 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1, 492 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 | 493 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2, 494 495 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT | 496 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK, 497}; 498 499/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ 500enum { 501 DPT_START = 1<<1, 502 DPT_STOP = 1<<0, 503}; 504 505/* B2_TST_CTRL1 8 bit Test Control Register 1 */ 506enum { 507 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */ 508 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */ 509 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */ 510 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */ 511 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */ 512 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */ 513 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */ 514 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */ 515}; 516 517/* B2_GPIO */ 518enum { 519 GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */ 520 GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */ 521 522 GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */ 523 GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */ 524 GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */ 525 GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */ 526 GLB_GPIO_TEST_SEL_BASE = 1<<11, 527 GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */ 528 GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */ 529}; 530 531/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ 532enum { 533 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */ 534 /* Bit 3.. 2: reserved */ 535 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */ 536 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/ 537}; 538 539/* B2_CHIP_ID 8 bit Chip Identification Number */ 540enum { 541 CHIP_ID_YUKON_XL = 0xb3, /* YUKON-2 XL */ 542 CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */ 543 CHIP_ID_YUKON_EX = 0xb5, /* YUKON-2 Extreme */ 544 CHIP_ID_YUKON_EC = 0xb6, /* YUKON-2 EC */ 545 CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */ 546 CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */ 547 CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */ 548 CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */ 549 CHIP_ID_YUKON_OPT = 0xbc, /* YUKON-2 Optima */ 550 CHIP_ID_YUKON_PRM = 0xbd, /* YUKON-2 Optima Prime */ 551 CHIP_ID_YUKON_OP_2 = 0xbe, /* YUKON-2 Optima 2 */ 552}; 553 554enum yukon_xl_rev { 555 CHIP_REV_YU_XL_A0 = 0, 556 CHIP_REV_YU_XL_A1 = 1, 557 CHIP_REV_YU_XL_A2 = 2, 558 CHIP_REV_YU_XL_A3 = 3, 559}; 560 561enum yukon_ec_rev { 562 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */ 563 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */ 564 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */ 565}; 566enum yukon_ec_u_rev { 567 CHIP_REV_YU_EC_U_A0 = 1, 568 CHIP_REV_YU_EC_U_A1 = 2, 569 CHIP_REV_YU_EC_U_B0 = 3, 570 CHIP_REV_YU_EC_U_B1 = 5, 571}; 572enum yukon_fe_rev { 573 CHIP_REV_YU_FE_A1 = 1, 574 CHIP_REV_YU_FE_A2 = 2, 575}; 576enum yukon_fe_p_rev { 577 CHIP_REV_YU_FE2_A0 = 0, 578}; 579enum yukon_ex_rev { 580 CHIP_REV_YU_EX_A0 = 1, 581 CHIP_REV_YU_EX_B0 = 2, 582}; 583enum yukon_supr_rev { 584 CHIP_REV_YU_SU_A0 = 0, 585 CHIP_REV_YU_SU_B0 = 1, 586 CHIP_REV_YU_SU_B1 = 3, 587}; 588 589 590/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 591enum { 592 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */ 593 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */ 594 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */ 595 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */ 596 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */ 597 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */ 598 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */ 599 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */ 600}; 601 602/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ 603enum { 604 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */ 605 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */ 606 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */ 607}; 608#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) 609#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) 610 611 612/* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */ 613enum { 614 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */ 615#define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK) 616 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */ 617 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */ 618#define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK) 619#define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK) 620 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */ 621 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */ 622}; 623 624/* B2_TI_CTRL 8 bit Timer control */ 625/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ 626enum { 627 TIM_START = 1<<2, /* Start Timer */ 628 TIM_STOP = 1<<1, /* Stop Timer */ 629 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */ 630}; 631 632/* B2_TI_TEST 8 Bit Timer Test */ 633/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ 634/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ 635enum { 636 TIM_T_ON = 1<<2, /* Test mode on */ 637 TIM_T_OFF = 1<<1, /* Test mode off */ 638 TIM_T_STEP = 1<<0, /* Test step */ 639}; 640 641/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */ 642enum { 643 PEX_RD_ACCESS = 1<<31, /* Access Mode Read = 1, Write = 0 */ 644 PEX_DB_ACCESS = 1<<30, /* Access to debug register */ 645}; 646 647/* B3_RAM_ADDR 32 bit RAM Address, to read or write */ 648 /* Bit 31..19: reserved */ 649#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ 650/* RAM Interface Registers */ 651 652/* B3_RI_CTRL 16 bit RAM Interface Control Register */ 653enum { 654 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */ 655 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/ 656 657 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */ 658 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */ 659}; 660 661#define SK_RI_TO_53 36 /* RAM interface timeout */ 662 663 664/* Port related registers FIFO, and Arbiter */ 665#define SK_REG(port,reg) (((port)<<7)+(reg)) 666 667/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ 668/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 669/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 670/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 671/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ 672 673#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */ 674 675/* TXA_CTRL 8 bit Tx Arbiter Control Register */ 676enum { 677 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */ 678 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */ 679 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */ 680 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */ 681 TXA_START_RC = 1<<3, /* Start sync Rate Control */ 682 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */ 683 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */ 684 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */ 685}; 686 687/* 688 * Bank 4 - 5 689 */ 690/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ 691enum { 692 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/ 693 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */ 694 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */ 695 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */ 696 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */ 697 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */ 698 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */ 699 700 RSS_KEY = 0x0220, /* RSS Key setup */ 701 RSS_CFG = 0x0248, /* RSS Configuration */ 702}; 703 704enum { 705 HASH_TCP_IPV6_EX_CTRL = 1<<5, 706 HASH_IPV6_EX_CTRL = 1<<4, 707 HASH_TCP_IPV6_CTRL = 1<<3, 708 HASH_IPV6_CTRL = 1<<2, 709 HASH_TCP_IPV4_CTRL = 1<<1, 710 HASH_IPV4_CTRL = 1<<0, 711 712 HASH_ALL = 0x3f, 713}; 714 715enum { 716 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */ 717 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */ 718 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */ 719 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */ 720 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */ 721 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */ 722 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */ 723 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */ 724 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */ 725}; 726 727/* Queue Register Offsets, use Q_ADDR() to access */ 728enum { 729 B8_Q_REGS = 0x0400, /* base of Queue registers */ 730 Q_D = 0x00, /* 8*32 bit Current Descriptor */ 731 Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */ 732 Q_DONE = 0x24, /* 16 bit Done Index */ 733 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */ 734 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */ 735 Q_BC = 0x30, /* 32 bit Current Byte Counter */ 736 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */ 737 Q_TEST = 0x38, /* 32 bit Test/Control Register */ 738 739/* Yukon-2 */ 740 Q_WM = 0x40, /* 16 bit FIFO Watermark */ 741 Q_AL = 0x42, /* 8 bit FIFO Alignment */ 742 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */ 743 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */ 744 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */ 745 Q_RL = 0x4a, /* 8 bit FIFO Read Level */ 746 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */ 747 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */ 748 Q_WL = 0x4e, /* 8 bit FIFO Write Level */ 749 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */ 750}; 751#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) 752 753/* Q_TEST 32 bit Test Register */ 754enum { 755 /* Transmit */ 756 F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */ 757 F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */ 758 759 /* Receive */ 760 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */ 761 762 /* Hardware testbits not used */ 763}; 764 765/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ 766enum { 767 Y2_B8_PREF_REGS = 0x0450, 768 769 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */ 770 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */ 771 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */ 772 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/ 773 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */ 774 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */ 775 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */ 776 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */ 777 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */ 778 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */ 779 780 PREF_UNIT_MASK_IDX = 0x0fff, 781}; 782#define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg)) 783 784/* RAM Buffer Register Offsets */ 785enum { 786 787 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */ 788 RB_END = 0x04,/* 32 bit RAM Buffer End Address */ 789 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */ 790 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */ 791 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */ 792 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */ 793 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */ 794 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */ 795 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ 796 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */ 797 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */ 798 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ 799 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */ 800 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */ 801}; 802 803/* Receive and Transmit Queues */ 804enum { 805 Q_R1 = 0x0000, /* Receive Queue 1 */ 806 Q_R2 = 0x0080, /* Receive Queue 2 */ 807 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */ 808 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */ 809 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */ 810 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */ 811}; 812 813/* Different PHY Types */ 814enum { 815 PHY_ADDR_MARV = 0, 816}; 817 818#define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs)) 819 820 821enum { 822 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */ 823 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */ 824 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */ 825 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */ 826 827 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */ 828 829/* Receive GMAC FIFO (YUKON and Yukon-2) */ 830 831 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */ 832 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */ 833 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */ 834 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ 835 RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */ 836 RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */ 837 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */ 838 RX_GMF_UP_THR = 0x0c58,/* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ 839 RX_GMF_LP_THR = 0x0c5a,/* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ 840 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */ 841 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */ 842 843 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */ 844 845 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */ 846 847 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */ 848}; 849 850 851/* Q_BC 32 bit Current Byte Counter */ 852 853/* BMU Control Status Registers */ 854/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ 855/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ 856/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ 857/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ 858/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ 859/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ 860/* Q_CSR 32 bit BMU Control/Status Register */ 861 862/* Rx BMU Control / Status Registers (Yukon-2) */ 863enum { 864 BMU_IDLE = 1<<31, /* BMU Idle State */ 865 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */ 866 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */ 867 868 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */ 869 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */ 870 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */ 871 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */ 872 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */ 873 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */ 874 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */ 875 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */ 876 BMU_START = 1<<8, /* Start Rx/Tx Queue */ 877 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */ 878 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */ 879 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */ 880 BMU_FIFO_RST = 1<<4, /* Reset FIFO */ 881 BMU_OP_ON = 1<<3, /* BMU Operational On */ 882 BMU_OP_OFF = 1<<2, /* BMU Operational Off */ 883 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */ 884 BMU_RST_SET = 1<<0, /* Set BMU Reset */ 885 886 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR, 887 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | 888 BMU_FIFO_ENA | BMU_OP_ON, 889 890 BMU_WM_DEFAULT = 0x600, 891 BMU_WM_PEX = 0x80, 892}; 893 894/* Tx BMU Control / Status Registers (Yukon-2) */ 895 /* Bit 31: same as for Rx */ 896enum { 897 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */ 898 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */ 899 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */ 900}; 901 902/* TBMU_TEST 0x06B8 Transmit BMU Test Register */ 903enum { 904 TBMU_TEST_BMU_TX_CHK_AUTO_OFF = 1<<31, /* BMU Tx Checksum Auto Calculation Disable */ 905 TBMU_TEST_BMU_TX_CHK_AUTO_ON = 1<<30, /* BMU Tx Checksum Auto Calculation Enable */ 906 TBMU_TEST_HOME_ADD_PAD_FIX1_EN = 1<<29, /* Home Address Paddiing FIX1 Enable */ 907 TBMU_TEST_HOME_ADD_PAD_FIX1_DIS = 1<<28, /* Home Address Paddiing FIX1 Disable */ 908 TBMU_TEST_ROUTING_ADD_FIX_EN = 1<<27, /* Routing Address Fix Enable */ 909 TBMU_TEST_ROUTING_ADD_FIX_DIS = 1<<26, /* Routing Address Fix Disable */ 910 TBMU_TEST_HOME_ADD_FIX_EN = 1<<25, /* Home address checksum fix enable */ 911 TBMU_TEST_HOME_ADD_FIX_DIS = 1<<24, /* Home address checksum fix disable */ 912 913 TBMU_TEST_TEST_RSPTR_ON = 1<<22, /* Testmode Shadow Read Ptr On */ 914 TBMU_TEST_TEST_RSPTR_OFF = 1<<21, /* Testmode Shadow Read Ptr Off */ 915 TBMU_TEST_TESTSTEP_RSPTR = 1<<20, /* Teststep Shadow Read Ptr */ 916 917 TBMU_TEST_TEST_RPTR_ON = 1<<18, /* Testmode Read Ptr On */ 918 TBMU_TEST_TEST_RPTR_OFF = 1<<17, /* Testmode Read Ptr Off */ 919 TBMU_TEST_TESTSTEP_RPTR = 1<<16, /* Teststep Read Ptr */ 920 921 TBMU_TEST_TEST_WSPTR_ON = 1<<14, /* Testmode Shadow Write Ptr On */ 922 TBMU_TEST_TEST_WSPTR_OFF = 1<<13, /* Testmode Shadow Write Ptr Off */ 923 TBMU_TEST_TESTSTEP_WSPTR = 1<<12, /* Teststep Shadow Write Ptr */ 924 925 TBMU_TEST_TEST_WPTR_ON = 1<<10, /* Testmode Write Ptr On */ 926 TBMU_TEST_TEST_WPTR_OFF = 1<<9, /* Testmode Write Ptr Off */ 927 TBMU_TEST_TESTSTEP_WPTR = 1<<8, /* Teststep Write Ptr */ 928 929 TBMU_TEST_TEST_REQ_NB_ON = 1<<6, /* Testmode Req Nbytes/Addr On */ 930 TBMU_TEST_TEST_REQ_NB_OFF = 1<<5, /* Testmode Req Nbytes/Addr Off */ 931 TBMU_TEST_TESTSTEP_REQ_NB = 1<<4, /* Teststep Req Nbytes/Addr */ 932 933 TBMU_TEST_TEST_DONE_IDX_ON = 1<<2, /* Testmode Done Index On */ 934 TBMU_TEST_TEST_DONE_IDX_OFF = 1<<1, /* Testmode Done Index Off */ 935 TBMU_TEST_TESTSTEP_DONE_IDX = 1<<0, /* Teststep Done Index */ 936}; 937 938/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ 939/* PREF_UNIT_CTRL 32 bit Prefetch Control register */ 940enum { 941 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */ 942 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */ 943 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */ 944 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */ 945}; 946 947/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ 948/* RB_START 32 bit RAM Buffer Start Address */ 949/* RB_END 32 bit RAM Buffer End Address */ 950/* RB_WP 32 bit RAM Buffer Write Pointer */ 951/* RB_RP 32 bit RAM Buffer Read Pointer */ 952/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ 953/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ 954/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ 955/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ 956/* RB_PC 32 bit RAM Buffer Packet Counter */ 957/* RB_LEV 32 bit RAM Buffer Level Register */ 958 959#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ 960/* RB_TST2 8 bit RAM Buffer Test Register 2 */ 961/* RB_TST1 8 bit RAM Buffer Test Register 1 */ 962 963/* RB_CTRL 8 bit RAM Buffer Control Register */ 964enum { 965 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */ 966 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */ 967 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */ 968 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */ 969 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */ 970 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */ 971}; 972 973 974/* Transmit GMAC FIFO (YUKON only) */ 975enum { 976 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */ 977 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 978 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */ 979 980 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */ 981 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ 982 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */ 983 984 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */ 985 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */ 986 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */ 987 988 /* Threshold values for Yukon-EC Ultra and Extreme */ 989 ECU_AE_THR = 0x0070, /* Almost Empty Threshold */ 990 ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */ 991 ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */ 992}; 993 994/* Descriptor Poll Timer Registers */ 995enum { 996 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */ 997 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */ 998 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */ 999 1000 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */ 1001}; 1002 1003/* Time Stamp Timer Registers (YUKON only) */ 1004enum { 1005 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */ 1006 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */ 1007 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */ 1008}; 1009 1010/* Polling Unit Registers (Yukon-2 only) */ 1011enum { 1012 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */ 1013 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */ 1014 1015 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */ 1016 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */ 1017}; 1018 1019enum { 1020 SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */ 1021 SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */ 1022}; 1023 1024enum { 1025 CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */ 1026 CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */ 1027 CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */ 1028 CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */ 1029 CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */ 1030 CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */ 1031 HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */ 1032 CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */ 1033 HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */ 1034 HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */ 1035}; 1036 1037/* ASF Subsystem Registers (Yukon-2 only) */ 1038enum { 1039 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */ 1040 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */ 1041 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */ 1042 1043 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */ 1044 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */ 1045 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */ 1046 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */ 1047 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */ 1048 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */ 1049}; 1050 1051/* Status BMU Registers (Yukon-2 only)*/ 1052enum { 1053 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */ 1054 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */ 1055 1056 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */ 1057 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */ 1058 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */ 1059 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */ 1060 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */ 1061 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */ 1062 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */ 1063 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */ 1064 1065/* FIFO Control/Status Registers (Yukon-2 only)*/ 1066 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */ 1067 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */ 1068 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */ 1069 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */ 1070 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */ 1071 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */ 1072 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */ 1073 1074/* Level and ISR Timer Registers (Yukon-2 only)*/ 1075 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */ 1076 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */ 1077 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */ 1078 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */ 1079 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */ 1080 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */ 1081 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */ 1082 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */ 1083 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */ 1084 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */ 1085 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */ 1086 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */ 1087}; 1088 1089enum { 1090 LINKLED_OFF = 0x01, 1091 LINKLED_ON = 0x02, 1092 LINKLED_LINKSYNC_OFF = 0x04, 1093 LINKLED_LINKSYNC_ON = 0x08, 1094 LINKLED_BLINK_OFF = 0x10, 1095 LINKLED_BLINK_ON = 0x20, 1096}; 1097 1098/* GMAC and GPHY Control Registers (YUKON only) */ 1099enum { 1100 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ 1101 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */ 1102 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */ 1103 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */ 1104 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */ 1105 1106/* Wake-up Frame Pattern Match Control Registers (YUKON only) */ 1107 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */ 1108 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */ 1109 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */ 1110 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */ 1111 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */ 1112 1113/* WOL Pattern Length Registers (YUKON only) */ 1114 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */ 1115 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */ 1116 1117/* WOL Pattern Counter Registers (YUKON only) */ 1118 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */ 1119 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */ 1120}; 1121#define WOL_REGS(port, x) (x + (port)*0x80) 1122 1123enum { 1124 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */ 1125 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */ 1126}; 1127#define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400) 1128 1129enum { 1130 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */ 1131 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */ 1132}; 1133 1134/* 1135 * Marvel-PHY Registers, indirect addressed over GMAC 1136 */ 1137enum { 1138 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ 1139 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */ 1140 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ 1141 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ 1142 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ 1143 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */ 1144 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ 1145 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */ 1146 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ 1147 /* Marvel-specific registers */ 1148 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */ 1149 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */ 1150 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */ 1151 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */ 1152 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */ 1153 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */ 1154 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */ 1155 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */ 1156 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */ 1157 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */ 1158 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */ 1159 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */ 1160 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */ 1161 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */ 1162 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */ 1163 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */ 1164 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */ 1165 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */ 1166 1167/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1168 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */ 1169 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */ 1170 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */ 1171 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */ 1172 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */ 1173}; 1174 1175enum { 1176 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */ 1177 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */ 1178 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */ 1179 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */ 1180 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */ 1181 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */ 1182 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */ 1183 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */ 1184 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */ 1185 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */ 1186}; 1187 1188enum { 1189 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */ 1190 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */ 1191 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */ 1192}; 1193 1194enum { 1195 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */ 1196 1197 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */ 1198 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */ 1199 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */ 1200 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */ 1201 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */ 1202 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */ 1203 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */ 1204}; 1205 1206enum { 1207 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */ 1208 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */ 1209 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */ 1210}; 1211 1212/* different Marvell PHY Ids */ 1213enum { 1214 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */ 1215 1216 PHY_BCOM_ID1_A1 = 0x6041, 1217 PHY_BCOM_ID1_B2 = 0x6043, 1218 PHY_BCOM_ID1_C0 = 0x6044, 1219 PHY_BCOM_ID1_C5 = 0x6047, 1220 1221 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */ 1222 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */ 1223 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */ 1224 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ 1225 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */ 1226 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */ 1227}; 1228 1229/* Advertisement register bits */ 1230enum { 1231 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */ 1232 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */ 1233 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */ 1234 1235 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */ 1236 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */ 1237 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */ 1238 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */ 1239 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */ 1240 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */ 1241 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */ 1242 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */ 1243 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/ 1244 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA, 1245 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL | 1246 PHY_AN_100HALF | PHY_AN_100FULL, 1247}; 1248 1249/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 1250/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 1251enum { 1252 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */ 1253 PHY_B_1000S_MSR = 1<<14, /* B…
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