/drivers/net/ftgmac100.c
C | 1365 lines | 959 code | 279 blank | 127 comment | 104 complexity | 9c8da4cdc486a5920719de3d2296edac MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
1/* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * (C) Copyright 2009-2011 Faraday Technology 5 * Po-Yu Chuang <ratbert@faraday-tech.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 23 24#include <linux/dma-mapping.h> 25#include <linux/etherdevice.h> 26#include <linux/ethtool.h> 27#include <linux/init.h> 28#include <linux/io.h> 29#include <linux/module.h> 30#include <linux/netdevice.h> 31#include <linux/phy.h> 32#include <linux/platform_device.h> 33#include <net/ip.h> 34 35#include "ftgmac100.h" 36 37#define DRV_NAME "ftgmac100" 38#define DRV_VERSION "0.7" 39 40#define RX_QUEUE_ENTRIES 256 /* must be power of 2 */ 41#define TX_QUEUE_ENTRIES 512 /* must be power of 2 */ 42 43#define MAX_PKT_SIZE 1518 44#define RX_BUF_SIZE PAGE_SIZE /* must be smaller than 0x3fff */ 45 46/****************************************************************************** 47 * private data 48 *****************************************************************************/ 49struct ftgmac100_descs { 50 struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES]; 51 struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES]; 52}; 53 54struct ftgmac100 { 55 struct resource *res; 56 void __iomem *base; 57 int irq; 58 59 struct ftgmac100_descs *descs; 60 dma_addr_t descs_dma_addr; 61 62 unsigned int rx_pointer; 63 unsigned int tx_clean_pointer; 64 unsigned int tx_pointer; 65 unsigned int tx_pending; 66 67 spinlock_t tx_lock; 68 69 struct net_device *netdev; 70 struct device *dev; 71 struct napi_struct napi; 72 73 struct mii_bus *mii_bus; 74 int phy_irq[PHY_MAX_ADDR]; 75 struct phy_device *phydev; 76 int old_speed; 77}; 78 79static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv, 80 struct ftgmac100_rxdes *rxdes, gfp_t gfp); 81 82/****************************************************************************** 83 * internal functions (hardware register access) 84 *****************************************************************************/ 85#define INT_MASK_ALL_ENABLED (FTGMAC100_INT_RPKT_LOST | \ 86 FTGMAC100_INT_XPKT_ETH | \ 87 FTGMAC100_INT_XPKT_LOST | \ 88 FTGMAC100_INT_AHB_ERR | \ 89 FTGMAC100_INT_PHYSTS_CHG | \ 90 FTGMAC100_INT_RPKT_BUF | \ 91 FTGMAC100_INT_NO_RXBUF) 92 93static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr) 94{ 95 iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR); 96} 97 98static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv, 99 unsigned int size) 100{ 101 size = FTGMAC100_RBSR_SIZE(size); 102 iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR); 103} 104 105static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv, 106 dma_addr_t addr) 107{ 108 iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); 109} 110 111static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv) 112{ 113 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); 114} 115 116static int ftgmac100_reset_hw(struct ftgmac100 *priv) 117{ 118 struct net_device *netdev = priv->netdev; 119 int i; 120 121 /* NOTE: reset clears all registers */ 122 iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR); 123 for (i = 0; i < 5; i++) { 124 unsigned int maccr; 125 126 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); 127 if (!(maccr & FTGMAC100_MACCR_SW_RST)) 128 return 0; 129 130 udelay(1000); 131 } 132 133 netdev_err(netdev, "software reset failed\n"); 134 return -EIO; 135} 136 137static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac) 138{ 139 unsigned int maddr = mac[0] << 8 | mac[1]; 140 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 141 142 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); 143 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); 144} 145 146static void ftgmac100_init_hw(struct ftgmac100 *priv) 147{ 148 /* setup ring buffer base registers */ 149 ftgmac100_set_rx_ring_base(priv, 150 priv->descs_dma_addr + 151 offsetof(struct ftgmac100_descs, rxdes)); 152 ftgmac100_set_normal_prio_tx_ring_base(priv, 153 priv->descs_dma_addr + 154 offsetof(struct ftgmac100_descs, txdes)); 155 156 ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE); 157 158 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC); 159 160 ftgmac100_set_mac(priv, priv->netdev->dev_addr); 161} 162 163#define MACCR_ENABLE_ALL (FTGMAC100_MACCR_TXDMA_EN | \ 164 FTGMAC100_MACCR_RXDMA_EN | \ 165 FTGMAC100_MACCR_TXMAC_EN | \ 166 FTGMAC100_MACCR_RXMAC_EN | \ 167 FTGMAC100_MACCR_FULLDUP | \ 168 FTGMAC100_MACCR_CRC_APD | \ 169 FTGMAC100_MACCR_RX_RUNT | \ 170 FTGMAC100_MACCR_RX_BROADPKT) 171 172static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed) 173{ 174 int maccr = MACCR_ENABLE_ALL; 175 176 switch (speed) { 177 default: 178 case 10: 179 break; 180 181 case 100: 182 maccr |= FTGMAC100_MACCR_FAST_MODE; 183 break; 184 185 case 1000: 186 maccr |= FTGMAC100_MACCR_GIGA_MODE; 187 break; 188 } 189 190 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); 191} 192 193static void ftgmac100_stop_hw(struct ftgmac100 *priv) 194{ 195 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); 196} 197 198/****************************************************************************** 199 * internal functions (receive descriptor) 200 *****************************************************************************/ 201static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes) 202{ 203 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS); 204} 205 206static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes) 207{ 208 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS); 209} 210 211static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes) 212{ 213 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY); 214} 215 216static void ftgmac100_rxdes_set_dma_own(struct ftgmac100_rxdes *rxdes) 217{ 218 /* clear status bits */ 219 rxdes->rxdes0 &= cpu_to_le32(FTGMAC100_RXDES0_EDORR); 220} 221 222static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes) 223{ 224 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR); 225} 226 227static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes) 228{ 229 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR); 230} 231 232static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes) 233{ 234 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL); 235} 236 237static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes) 238{ 239 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT); 240} 241 242static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes) 243{ 244 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB); 245} 246 247static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes) 248{ 249 return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC; 250} 251 252static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes) 253{ 254 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST); 255} 256 257static void ftgmac100_rxdes_set_end_of_ring(struct ftgmac100_rxdes *rxdes) 258{ 259 rxdes->rxdes0 |= cpu_to_le32(FTGMAC100_RXDES0_EDORR); 260} 261 262static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes, 263 dma_addr_t addr) 264{ 265 rxdes->rxdes3 = cpu_to_le32(addr); 266} 267 268static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes) 269{ 270 return le32_to_cpu(rxdes->rxdes3); 271} 272 273static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes) 274{ 275 return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) == 276 cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP); 277} 278 279static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes) 280{ 281 return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) == 282 cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP); 283} 284 285static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes) 286{ 287 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR); 288} 289 290static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes) 291{ 292 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR); 293} 294 295static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes) 296{ 297 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR); 298} 299 300/* 301 * rxdes2 is not used by hardware. We use it to keep track of page. 302 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu(). 303 */ 304static void ftgmac100_rxdes_set_page(struct ftgmac100_rxdes *rxdes, struct page *page) 305{ 306 rxdes->rxdes2 = (unsigned int)page; 307} 308 309static struct page *ftgmac100_rxdes_get_page(struct ftgmac100_rxdes *rxdes) 310{ 311 return (struct page *)rxdes->rxdes2; 312} 313 314/****************************************************************************** 315 * internal functions (receive) 316 *****************************************************************************/ 317static int ftgmac100_next_rx_pointer(int pointer) 318{ 319 return (pointer + 1) & (RX_QUEUE_ENTRIES - 1); 320} 321 322static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv) 323{ 324 priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer); 325} 326 327static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv) 328{ 329 return &priv->descs->rxdes[priv->rx_pointer]; 330} 331 332static struct ftgmac100_rxdes * 333ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv) 334{ 335 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv); 336 337 while (ftgmac100_rxdes_packet_ready(rxdes)) { 338 if (ftgmac100_rxdes_first_segment(rxdes)) 339 return rxdes; 340 341 ftgmac100_rxdes_set_dma_own(rxdes); 342 ftgmac100_rx_pointer_advance(priv); 343 rxdes = ftgmac100_current_rxdes(priv); 344 } 345 346 return NULL; 347} 348 349static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv, 350 struct ftgmac100_rxdes *rxdes) 351{ 352 struct net_device *netdev = priv->netdev; 353 bool error = false; 354 355 if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) { 356 if (net_ratelimit()) 357 netdev_info(netdev, "rx err\n"); 358 359 netdev->stats.rx_errors++; 360 error = true; 361 } 362 363 if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) { 364 if (net_ratelimit()) 365 netdev_info(netdev, "rx crc err\n"); 366 367 netdev->stats.rx_crc_errors++; 368 error = true; 369 } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) { 370 if (net_ratelimit()) 371 netdev_info(netdev, "rx IP checksum err\n"); 372 373 error = true; 374 } 375 376 if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) { 377 if (net_ratelimit()) 378 netdev_info(netdev, "rx frame too long\n"); 379 380 netdev->stats.rx_length_errors++; 381 error = true; 382 } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) { 383 if (net_ratelimit()) 384 netdev_info(netdev, "rx runt\n"); 385 386 netdev->stats.rx_length_errors++; 387 error = true; 388 } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) { 389 if (net_ratelimit()) 390 netdev_info(netdev, "rx odd nibble\n"); 391 392 netdev->stats.rx_length_errors++; 393 error = true; 394 } 395 396 return error; 397} 398 399static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv) 400{ 401 struct net_device *netdev = priv->netdev; 402 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv); 403 bool done = false; 404 405 if (net_ratelimit()) 406 netdev_dbg(netdev, "drop packet %p\n", rxdes); 407 408 do { 409 if (ftgmac100_rxdes_last_segment(rxdes)) 410 done = true; 411 412 ftgmac100_rxdes_set_dma_own(rxdes); 413 ftgmac100_rx_pointer_advance(priv); 414 rxdes = ftgmac100_current_rxdes(priv); 415 } while (!done && ftgmac100_rxdes_packet_ready(rxdes)); 416 417 netdev->stats.rx_dropped++; 418} 419 420static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) 421{ 422 struct net_device *netdev = priv->netdev; 423 struct ftgmac100_rxdes *rxdes; 424 struct sk_buff *skb; 425 bool done = false; 426 427 rxdes = ftgmac100_rx_locate_first_segment(priv); 428 if (!rxdes) 429 return false; 430 431 if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) { 432 ftgmac100_rx_drop_packet(priv); 433 return true; 434 } 435 436 /* start processing */ 437 skb = netdev_alloc_skb_ip_align(netdev, 128); 438 if (unlikely(!skb)) { 439 if (net_ratelimit()) 440 netdev_err(netdev, "rx skb alloc failed\n"); 441 442 ftgmac100_rx_drop_packet(priv); 443 return true; 444 } 445 446 if (unlikely(ftgmac100_rxdes_multicast(rxdes))) 447 netdev->stats.multicast++; 448 449 /* 450 * It seems that HW does checksum incorrectly with fragmented packets, 451 * so we are conservative here - if HW checksum error, let software do 452 * the checksum again. 453 */ 454 if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) || 455 (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes))) 456 skb->ip_summed = CHECKSUM_UNNECESSARY; 457 458 do { 459 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes); 460 struct page *page = ftgmac100_rxdes_get_page(rxdes); 461 unsigned int size; 462 463 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 464 465 size = ftgmac100_rxdes_data_length(rxdes); 466 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size); 467 468 skb->len += size; 469 skb->data_len += size; 470 skb->truesize += size; 471 472 if (ftgmac100_rxdes_last_segment(rxdes)) 473 done = true; 474 475 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC); 476 477 ftgmac100_rx_pointer_advance(priv); 478 rxdes = ftgmac100_current_rxdes(priv); 479 } while (!done); 480 481 __pskb_pull_tail(skb, min(skb->len, 64U)); 482 skb->protocol = eth_type_trans(skb, netdev); 483 484 netdev->stats.rx_packets++; 485 netdev->stats.rx_bytes += skb->len; 486 487 /* push packet to protocol stack */ 488 napi_gro_receive(&priv->napi, skb); 489 490 (*processed)++; 491 return true; 492} 493 494/****************************************************************************** 495 * internal functions (transmit descriptor) 496 *****************************************************************************/ 497static void ftgmac100_txdes_reset(struct ftgmac100_txdes *txdes) 498{ 499 /* clear all except end of ring bit */ 500 txdes->txdes0 &= cpu_to_le32(FTGMAC100_TXDES0_EDOTR); 501 txdes->txdes1 = 0; 502 txdes->txdes2 = 0; 503 txdes->txdes3 = 0; 504} 505 506static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes) 507{ 508 return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN); 509} 510 511static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes) 512{ 513 /* 514 * Make sure dma own bit will not be set before any other 515 * descriptor fields. 516 */ 517 wmb(); 518 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN); 519} 520 521static void ftgmac100_txdes_set_end_of_ring(struct ftgmac100_txdes *txdes) 522{ 523 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_EDOTR); 524} 525 526static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes) 527{ 528 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS); 529} 530 531static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes) 532{ 533 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS); 534} 535 536static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes, 537 unsigned int len) 538{ 539 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len)); 540} 541 542static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes) 543{ 544 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC); 545} 546 547static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes) 548{ 549 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM); 550} 551 552static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes) 553{ 554 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM); 555} 556 557static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes) 558{ 559 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM); 560} 561 562static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes, 563 dma_addr_t addr) 564{ 565 txdes->txdes3 = cpu_to_le32(addr); 566} 567 568static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes) 569{ 570 return le32_to_cpu(txdes->txdes3); 571} 572 573/* 574 * txdes2 is not used by hardware. We use it to keep track of socket buffer. 575 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu(). 576 */ 577static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes, 578 struct sk_buff *skb) 579{ 580 txdes->txdes2 = (unsigned int)skb; 581} 582 583static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes) 584{ 585 return (struct sk_buff *)txdes->txdes2; 586} 587 588/****************************************************************************** 589 * internal functions (transmit) 590 *****************************************************************************/ 591static int ftgmac100_next_tx_pointer(int pointer) 592{ 593 return (pointer + 1) & (TX_QUEUE_ENTRIES - 1); 594} 595 596static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv) 597{ 598 priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer); 599} 600 601static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv) 602{ 603 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer); 604} 605 606static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv) 607{ 608 return &priv->descs->txdes[priv->tx_pointer]; 609} 610 611static struct ftgmac100_txdes * 612ftgmac100_current_clean_txdes(struct ftgmac100 *priv) 613{ 614 return &priv->descs->txdes[priv->tx_clean_pointer]; 615} 616 617static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) 618{ 619 struct net_device *netdev = priv->netdev; 620 struct ftgmac100_txdes *txdes; 621 struct sk_buff *skb; 622 dma_addr_t map; 623 624 if (priv->tx_pending == 0) 625 return false; 626 627 txdes = ftgmac100_current_clean_txdes(priv); 628 629 if (ftgmac100_txdes_owned_by_dma(txdes)) 630 return false; 631 632 skb = ftgmac100_txdes_get_skb(txdes); 633 map = ftgmac100_txdes_get_dma_addr(txdes); 634 635 netdev->stats.tx_packets++; 636 netdev->stats.tx_bytes += skb->len; 637 638 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE); 639 640 dev_kfree_skb(skb); 641 642 ftgmac100_txdes_reset(txdes); 643 644 ftgmac100_tx_clean_pointer_advance(priv); 645 646 spin_lock(&priv->tx_lock); 647 priv->tx_pending--; 648 spin_unlock(&priv->tx_lock); 649 netif_wake_queue(netdev); 650 651 return true; 652} 653 654static void ftgmac100_tx_complete(struct ftgmac100 *priv) 655{ 656 while (ftgmac100_tx_complete_packet(priv)) 657 ; 658} 659 660static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb, 661 dma_addr_t map) 662{ 663 struct net_device *netdev = priv->netdev; 664 struct ftgmac100_txdes *txdes; 665 unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len; 666 667 txdes = ftgmac100_current_txdes(priv); 668 ftgmac100_tx_pointer_advance(priv); 669 670 /* setup TX descriptor */ 671 ftgmac100_txdes_set_skb(txdes, skb); 672 ftgmac100_txdes_set_dma_addr(txdes, map); 673 ftgmac100_txdes_set_buffer_size(txdes, len); 674 675 ftgmac100_txdes_set_first_segment(txdes); 676 ftgmac100_txdes_set_last_segment(txdes); 677 ftgmac100_txdes_set_txint(txdes); 678 if (skb->ip_summed == CHECKSUM_PARTIAL) { 679 __be16 protocol = skb->protocol; 680 681 if (protocol == cpu_to_be16(ETH_P_IP)) { 682 u8 ip_proto = ip_hdr(skb)->protocol; 683 684 ftgmac100_txdes_set_ipcs(txdes); 685 if (ip_proto == IPPROTO_TCP) 686 ftgmac100_txdes_set_tcpcs(txdes); 687 else if (ip_proto == IPPROTO_UDP) 688 ftgmac100_txdes_set_udpcs(txdes); 689 } 690 } 691 692 spin_lock(&priv->tx_lock); 693 priv->tx_pending++; 694 if (priv->tx_pending == TX_QUEUE_ENTRIES) 695 netif_stop_queue(netdev); 696 697 /* start transmit */ 698 ftgmac100_txdes_set_dma_own(txdes); 699 spin_unlock(&priv->tx_lock); 700 701 ftgmac100_txdma_normal_prio_start_polling(priv); 702 703 return NETDEV_TX_OK; 704} 705 706/****************************************************************************** 707 * internal functions (buffer) 708 *****************************************************************************/ 709static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv, 710 struct ftgmac100_rxdes *rxdes, gfp_t gfp) 711{ 712 struct net_device *netdev = priv->netdev; 713 struct page *page; 714 dma_addr_t map; 715 716 page = alloc_page(gfp); 717 if (!page) { 718 if (net_ratelimit()) 719 netdev_err(netdev, "failed to allocate rx page\n"); 720 return -ENOMEM; 721 } 722 723 map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE); 724 if (unlikely(dma_mapping_error(priv->dev, map))) { 725 if (net_ratelimit()) 726 netdev_err(netdev, "failed to map rx page\n"); 727 __free_page(page); 728 return -ENOMEM; 729 } 730 731 ftgmac100_rxdes_set_page(rxdes, page); 732 ftgmac100_rxdes_set_dma_addr(rxdes, map); 733 ftgmac100_rxdes_set_dma_own(rxdes); 734 return 0; 735} 736 737static void ftgmac100_free_buffers(struct ftgmac100 *priv) 738{ 739 int i; 740 741 for (i = 0; i < RX_QUEUE_ENTRIES; i++) { 742 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; 743 struct page *page = ftgmac100_rxdes_get_page(rxdes); 744 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes); 745 746 if (!page) 747 continue; 748 749 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); 750 __free_page(page); 751 } 752 753 for (i = 0; i < TX_QUEUE_ENTRIES; i++) { 754 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i]; 755 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes); 756 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes); 757 758 if (!skb) 759 continue; 760 761 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE); 762 dev_kfree_skb(skb); 763 } 764 765 dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs), 766 priv->descs, priv->descs_dma_addr); 767} 768 769static int ftgmac100_alloc_buffers(struct ftgmac100 *priv) 770{ 771 int i; 772 773 priv->descs = dma_alloc_coherent(priv->dev, 774 sizeof(struct ftgmac100_descs), 775 &priv->descs_dma_addr, GFP_KERNEL); 776 if (!priv->descs) 777 return -ENOMEM; 778 779 memset(priv->descs, 0, sizeof(struct ftgmac100_descs)); 780 781 /* initialize RX ring */ 782 ftgmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]); 783 784 for (i = 0; i < RX_QUEUE_ENTRIES; i++) { 785 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; 786 787 if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL)) 788 goto err; 789 } 790 791 /* initialize TX ring */ 792 ftgmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]); 793 return 0; 794 795err: 796 ftgmac100_free_buffers(priv); 797 return -ENOMEM; 798} 799 800/****************************************************************************** 801 * internal functions (mdio) 802 *****************************************************************************/ 803static void ftgmac100_adjust_link(struct net_device *netdev) 804{ 805 struct ftgmac100 *priv = netdev_priv(netdev); 806 struct phy_device *phydev = priv->phydev; 807 int ier; 808 809 if (phydev->speed == priv->old_speed) 810 return; 811 812 priv->old_speed = phydev->speed; 813 814 ier = ioread32(priv->base + FTGMAC100_OFFSET_IER); 815 816 /* disable all interrupts */ 817 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 818 819 netif_stop_queue(netdev); 820 ftgmac100_stop_hw(priv); 821 822 netif_start_queue(netdev); 823 ftgmac100_init_hw(priv); 824 ftgmac100_start_hw(priv, phydev->speed); 825 826 /* re-enable interrupts */ 827 iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER); 828} 829 830static int ftgmac100_mii_probe(struct ftgmac100 *priv) 831{ 832 struct net_device *netdev = priv->netdev; 833 struct phy_device *phydev = NULL; 834 int i; 835 836 /* search for connect PHY device */ 837 for (i = 0; i < PHY_MAX_ADDR; i++) { 838 struct phy_device *tmp = priv->mii_bus->phy_map[i]; 839 840 if (tmp) { 841 phydev = tmp; 842 break; 843 } 844 } 845 846 /* now we are supposed to have a proper phydev, to attach to... */ 847 if (!phydev) { 848 netdev_info(netdev, "%s: no PHY found\n", netdev->name); 849 return -ENODEV; 850 } 851 852 phydev = phy_connect(netdev, dev_name(&phydev->dev), 853 &ftgmac100_adjust_link, 0, 854 PHY_INTERFACE_MODE_GMII); 855 856 if (IS_ERR(phydev)) { 857 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); 858 return PTR_ERR(phydev); 859 } 860 861 priv->phydev = phydev; 862 return 0; 863} 864 865/****************************************************************************** 866 * struct mii_bus functions 867 *****************************************************************************/ 868static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) 869{ 870 struct net_device *netdev = bus->priv; 871 struct ftgmac100 *priv = netdev_priv(netdev); 872 unsigned int phycr; 873 int i; 874 875 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 876 877 /* preserve MDC cycle threshold */ 878 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 879 880 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 881 FTGMAC100_PHYCR_REGAD(regnum) | 882 FTGMAC100_PHYCR_MIIRD; 883 884 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 885 886 for (i = 0; i < 10; i++) { 887 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 888 889 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { 890 int data; 891 892 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); 893 return FTGMAC100_PHYDATA_MIIRDATA(data); 894 } 895 896 udelay(100); 897 } 898 899 netdev_err(netdev, "mdio read timed out\n"); 900 return -EIO; 901} 902 903static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, 904 int regnum, u16 value) 905{ 906 struct net_device *netdev = bus->priv; 907 struct ftgmac100 *priv = netdev_priv(netdev); 908 unsigned int phycr; 909 int data; 910 int i; 911 912 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 913 914 /* preserve MDC cycle threshold */ 915 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; 916 917 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | 918 FTGMAC100_PHYCR_REGAD(regnum) | 919 FTGMAC100_PHYCR_MIIWR; 920 921 data = FTGMAC100_PHYDATA_MIIWDATA(value); 922 923 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); 924 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); 925 926 for (i = 0; i < 10; i++) { 927 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); 928 929 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) 930 return 0; 931 932 udelay(100); 933 } 934 935 netdev_err(netdev, "mdio write timed out\n"); 936 return -EIO; 937} 938 939static int ftgmac100_mdiobus_reset(struct mii_bus *bus) 940{ 941 return 0; 942} 943 944/****************************************************************************** 945 * struct ethtool_ops functions 946 *****************************************************************************/ 947static void ftgmac100_get_drvinfo(struct net_device *netdev, 948 struct ethtool_drvinfo *info) 949{ 950 strcpy(info->driver, DRV_NAME); 951 strcpy(info->version, DRV_VERSION); 952 strcpy(info->bus_info, dev_name(&netdev->dev)); 953} 954 955static int ftgmac100_get_settings(struct net_device *netdev, 956 struct ethtool_cmd *cmd) 957{ 958 struct ftgmac100 *priv = netdev_priv(netdev); 959 960 return phy_ethtool_gset(priv->phydev, cmd); 961} 962 963static int ftgmac100_set_settings(struct net_device *netdev, 964 struct ethtool_cmd *cmd) 965{ 966 struct ftgmac100 *priv = netdev_priv(netdev); 967 968 return phy_ethtool_sset(priv->phydev, cmd); 969} 970 971static const struct ethtool_ops ftgmac100_ethtool_ops = { 972 .set_settings = ftgmac100_set_settings, 973 .get_settings = ftgmac100_get_settings, 974 .get_drvinfo = ftgmac100_get_drvinfo, 975 .get_link = ethtool_op_get_link, 976}; 977 978/****************************************************************************** 979 * interrupt handler 980 *****************************************************************************/ 981static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) 982{ 983 struct net_device *netdev = dev_id; 984 struct ftgmac100 *priv = netdev_priv(netdev); 985 986 if (likely(netif_running(netdev))) { 987 /* Disable interrupts for polling */ 988 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 989 napi_schedule(&priv->napi); 990 } 991 992 return IRQ_HANDLED; 993} 994 995/****************************************************************************** 996 * struct napi_struct functions 997 *****************************************************************************/ 998static int ftgmac100_poll(struct napi_struct *napi, int budget) 999{ 1000 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); 1001 struct net_device *netdev = priv->netdev; 1002 unsigned int status; 1003 bool completed = true; 1004 int rx = 0; 1005 1006 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); 1007 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); 1008 1009 if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) { 1010 /* 1011 * FTGMAC100_INT_RPKT_BUF: 1012 * RX DMA has received packets into RX buffer successfully 1013 * 1014 * FTGMAC100_INT_NO_RXBUF: 1015 * RX buffer unavailable 1016 */ 1017 bool retry; 1018 1019 do { 1020 retry = ftgmac100_rx_packet(priv, &rx); 1021 } while (retry && rx < budget); 1022 1023 if (retry && rx == budget) 1024 completed = false; 1025 } 1026 1027 if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) { 1028 /* 1029 * FTGMAC100_INT_XPKT_ETH: 1030 * packet transmitted to ethernet successfully 1031 * 1032 * FTGMAC100_INT_XPKT_LOST: 1033 * packet transmitted to ethernet lost due to late 1034 * collision or excessive collision 1035 */ 1036 ftgmac100_tx_complete(priv); 1037 } 1038 1039 if (status & (FTGMAC100_INT_NO_RXBUF | FTGMAC100_INT_RPKT_LOST | 1040 FTGMAC100_INT_AHB_ERR | FTGMAC100_INT_PHYSTS_CHG)) { 1041 if (net_ratelimit()) 1042 netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status, 1043 status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "", 1044 status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "", 1045 status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : "", 1046 status & FTGMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : ""); 1047 1048 if (status & FTGMAC100_INT_NO_RXBUF) { 1049 /* RX buffer unavailable */ 1050 netdev->stats.rx_over_errors++; 1051 } 1052 1053 if (status & FTGMAC100_INT_RPKT_LOST) { 1054 /* received packet lost due to RX FIFO full */ 1055 netdev->stats.rx_fifo_errors++; 1056 } 1057 } 1058 1059 if (completed) { 1060 napi_complete(napi); 1061 1062 /* enable all interrupts */ 1063 iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER); 1064 } 1065 1066 return rx; 1067} 1068 1069/****************************************************************************** 1070 * struct net_device_ops functions 1071 *****************************************************************************/ 1072static int ftgmac100_open(struct net_device *netdev) 1073{ 1074 struct ftgmac100 *priv = netdev_priv(netdev); 1075 int err; 1076 1077 err = ftgmac100_alloc_buffers(priv); 1078 if (err) { 1079 netdev_err(netdev, "failed to allocate buffers\n"); 1080 goto err_alloc; 1081 } 1082 1083 err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev); 1084 if (err) { 1085 netdev_err(netdev, "failed to request irq %d\n", priv->irq); 1086 goto err_irq; 1087 } 1088 1089 priv->rx_pointer = 0; 1090 priv->tx_clean_pointer = 0; 1091 priv->tx_pointer = 0; 1092 priv->tx_pending = 0; 1093 1094 err = ftgmac100_reset_hw(priv); 1095 if (err) 1096 goto err_hw; 1097 1098 ftgmac100_init_hw(priv); 1099 ftgmac100_start_hw(priv, 10); 1100 1101 phy_start(priv->phydev); 1102 1103 napi_enable(&priv->napi); 1104 netif_start_queue(netdev); 1105 1106 /* enable all interrupts */ 1107 iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER); 1108 return 0; 1109 1110err_hw: 1111 free_irq(priv->irq, netdev); 1112err_irq: 1113 ftgmac100_free_buffers(priv); 1114err_alloc: 1115 return err; 1116} 1117 1118static int ftgmac100_stop(struct net_device *netdev) 1119{ 1120 struct ftgmac100 *priv = netdev_priv(netdev); 1121 1122 /* disable all interrupts */ 1123 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); 1124 1125 netif_stop_queue(netdev); 1126 napi_disable(&priv->napi); 1127 phy_stop(priv->phydev); 1128 1129 ftgmac100_stop_hw(priv); 1130 free_irq(priv->irq, netdev); 1131 ftgmac100_free_buffers(priv); 1132 1133 return 0; 1134} 1135 1136static int ftgmac100_hard_start_xmit(struct sk_buff *skb, 1137 struct net_device *netdev) 1138{ 1139 struct ftgmac100 *priv = netdev_priv(netdev); 1140 dma_addr_t map; 1141 1142 if (unlikely(skb->len > MAX_PKT_SIZE)) { 1143 if (net_ratelimit()) 1144 netdev_dbg(netdev, "tx packet too big\n"); 1145 1146 netdev->stats.tx_dropped++; 1147 dev_kfree_skb(skb); 1148 return NETDEV_TX_OK; 1149 } 1150 1151 map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); 1152 if (unlikely(dma_mapping_error(priv->dev, map))) { 1153 /* drop packet */ 1154 if (net_ratelimit()) 1155 netdev_err(netdev, "map socket buffer failed\n"); 1156 1157 netdev->stats.tx_dropped++; 1158 dev_kfree_skb(skb); 1159 return NETDEV_TX_OK; 1160 } 1161 1162 return ftgmac100_xmit(priv, skb, map); 1163} 1164 1165/* optional */ 1166static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 1167{ 1168 struct ftgmac100 *priv = netdev_priv(netdev); 1169 1170 return phy_mii_ioctl(priv->phydev, ifr, cmd); 1171} 1172 1173static const struct net_device_ops ftgmac100_netdev_ops = { 1174 .ndo_open = ftgmac100_open, 1175 .ndo_stop = ftgmac100_stop, 1176 .ndo_start_xmit = ftgmac100_hard_start_xmit, 1177 .ndo_set_mac_address = eth_mac_addr, 1178 .ndo_validate_addr = eth_validate_addr, 1179 .ndo_do_ioctl = ftgmac100_do_ioctl, 1180}; 1181 1182/****************************************************************************** 1183 * struct platform_driver functions 1184 *****************************************************************************/ 1185static int ftgmac100_probe(struct platform_device *pdev) 1186{ 1187 struct resource *res; 1188 int irq; 1189 struct net_device *netdev; 1190 struct ftgmac100 *priv; 1191 int err; 1192 int i; 1193 1194 if (!pdev) 1195 return -ENODEV; 1196 1197 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1198 if (!res) 1199 return -ENXIO; 1200 1201 irq = platform_get_irq(pdev, 0); 1202 if (irq < 0) 1203 return irq; 1204 1205 /* setup net_device */ 1206 netdev = alloc_etherdev(sizeof(*priv)); 1207 if (!netdev) { 1208 err = -ENOMEM; 1209 goto err_alloc_etherdev; 1210 } 1211 1212 SET_NETDEV_DEV(netdev, &pdev->dev); 1213 1214 SET_ETHTOOL_OPS(netdev, &ftgmac100_ethtool_ops); 1215 netdev->netdev_ops = &ftgmac100_netdev_ops; 1216 netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO; 1217 1218 platform_set_drvdata(pdev, netdev); 1219 1220 /* setup private data */ 1221 priv = netdev_priv(netdev); 1222 priv->netdev = netdev; 1223 priv->dev = &pdev->dev; 1224 1225 spin_lock_init(&priv->tx_lock); 1226 1227 /* initialize NAPI */ 1228 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64); 1229 1230 /* map io memory */ 1231 priv->res = request_mem_region(res->start, resource_size(res), 1232 dev_name(&pdev->dev)); 1233 if (!priv->res) { 1234 dev_err(&pdev->dev, "Could not reserve memory region\n"); 1235 err = -ENOMEM; 1236 goto err_req_mem; 1237 } 1238 1239 priv->base = ioremap(res->start, resource_size(res)); 1240 if (!priv->base) { 1241 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); 1242 err = -EIO; 1243 goto err_ioremap; 1244 } 1245 1246 priv->irq = irq; 1247 1248 /* initialize mdio bus */ 1249 priv->mii_bus = mdiobus_alloc(); 1250 if (!priv->mii_bus) { 1251 err = -EIO; 1252 goto err_alloc_mdiobus; 1253 } 1254 1255 priv->mii_bus->name = "ftgmac100_mdio"; 1256 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "ftgmac100_mii"); 1257 1258 priv->mii_bus->priv = netdev; 1259 priv->mii_bus->read = ftgmac100_mdiobus_read; 1260 priv->mii_bus->write = ftgmac100_mdiobus_write; 1261 priv->mii_bus->reset = ftgmac100_mdiobus_reset; 1262 priv->mii_bus->irq = priv->phy_irq; 1263 1264 for (i = 0; i < PHY_MAX_ADDR; i++) 1265 priv->mii_bus->irq[i] = PHY_POLL; 1266 1267 err = mdiobus_register(priv->mii_bus); 1268 if (err) { 1269 dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); 1270 goto err_register_mdiobus; 1271 } 1272 1273 err = ftgmac100_mii_probe(priv); 1274 if (err) { 1275 dev_err(&pdev->dev, "MII Probe failed!\n"); 1276 goto err_mii_probe; 1277 } 1278 1279 /* register network device */ 1280 err = register_netdev(netdev); 1281 if (err) { 1282 dev_err(&pdev->dev, "Failed to register netdev\n"); 1283 goto err_register_netdev; 1284 } 1285 1286 netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base); 1287 1288 if (!is_valid_ether_addr(netdev->dev_addr)) { 1289 random_ether_addr(netdev->dev_addr); 1290 netdev_info(netdev, "generated random MAC address %pM\n", 1291 netdev->dev_addr); 1292 } 1293 1294 return 0; 1295 1296err_register_netdev: 1297 phy_disconnect(priv->phydev); 1298err_mii_probe: 1299 mdiobus_unregister(priv->mii_bus); 1300err_register_mdiobus: 1301 mdiobus_free(priv->mii_bus); 1302err_alloc_mdiobus: 1303 iounmap(priv->base); 1304err_ioremap: 1305 release_resource(priv->res); 1306err_req_mem: 1307 netif_napi_del(&priv->napi); 1308 platform_set_drvdata(pdev, NULL); 1309 free_netdev(netdev); 1310err_alloc_etherdev: 1311 return err; 1312} 1313 1314static int __exit ftgmac100_remove(struct platform_device *pdev) 1315{ 1316 struct net_device *netdev; 1317 struct ftgmac100 *priv; 1318 1319 netdev = platform_get_drvdata(pdev); 1320 priv = netdev_priv(netdev); 1321 1322 unregister_netdev(netdev); 1323 1324 phy_disconnect(priv->phydev); 1325 mdiobus_unregister(priv->mii_bus); 1326 mdiobus_free(priv->mii_bus); 1327 1328 iounmap(priv->base); 1329 release_resource(priv->res); 1330 1331 netif_napi_del(&priv->napi); 1332 platform_set_drvdata(pdev, NULL); 1333 free_netdev(netdev); 1334 return 0; 1335} 1336 1337static struct platform_driver ftgmac100_driver = { 1338 .probe = ftgmac100_probe, 1339 .remove = __exit_p(ftgmac100_remove), 1340 .driver = { 1341 .name = DRV_NAME, 1342 .owner = THIS_MODULE, 1343 }, 1344}; 1345 1346/****************************************************************************** 1347 * initialization / finalization 1348 *****************************************************************************/ 1349static int __init ftgmac100_init(void) 1350{ 1351 pr_info("Loading version " DRV_VERSION " ...\n"); 1352 return platform_driver_register(&ftgmac100_driver); 1353} 1354 1355static void __exit ftgmac100_exit(void) 1356{ 1357 platform_driver_unregister(&ftgmac100_driver); 1358} 1359 1360module_init(ftgmac100_init); 1361module_exit(ftgmac100_exit); 1362 1363MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); 1364MODULE_DESCRIPTION("FTGMAC100 driver"); 1365MODULE_LICENSE("GPL");