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/drivers/net/bmac.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C Header | 164 lines | 134 code | 9 blank | 21 comment | 0 complexity | 115da2f2c27a13e2d30a25ea3d11bd56 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1/*
  2 * mace.h - definitions for the registers in the "Big Mac"
  3 *  Ethernet controller found in PowerMac G3 models.
  4 *
  5 * Copyright (C) 1998 Randy Gobbel.
  6 *
  7 * This program is free software; you can redistribute it and/or
  8 * modify it under the terms of the GNU General Public License
  9 * as published by the Free Software Foundation; either version
 10 * 2 of the License, or (at your option) any later version.
 11 */
 12
 13/* The "Big MAC" appears to have some parts in common with the Sun "Happy Meal"
 14 * (HME) controller.  See sunhme.h
 15 */
 16
 17
 18/* register offsets */
 19
 20/* global status and control */
 21#define	XIFC		0x000   /* low-level interface control */
 22#	define	TxOutputEnable	0x0001 /* output driver enable */
 23#	define	XIFLoopback	0x0002 /* Loopback-mode XIF enable */
 24#	define	MIILoopback	0x0004 /* Loopback-mode MII enable */
 25#	define	MIILoopbackBits	0x0006
 26#	define	MIIBuffDisable	0x0008 /* MII receive buffer disable */
 27#	define	SQETestEnable	0x0010 /* SQE test enable */
 28#	define	SQETimeWindow	0x03e0 /* SQE time window */
 29#	define	XIFLanceMode	0x0010 /* Lance mode enable */
 30#	define	XIFLanceIPG0	0x03e0 /* Lance mode IPG0 */
 31#define	TXFIFOCSR	0x100   /* transmit FIFO control */
 32#	define	TxFIFOEnable	0x0001
 33#define	TXTH		0x110   /* transmit threshold */
 34#	define	TxThreshold	0x0004
 35#define RXFIFOCSR	0x120   /* receive FIFO control */
 36#	define	RxFIFOEnable	0x0001
 37#define MEMADD		0x130   /* memory address, unknown function */
 38#define MEMDATAHI	0x140   /* memory data high, presently unused in driver */
 39#define MEMDATALO	0x150   /* memory data low, presently unused in driver */
 40#define XCVRIF		0x160   /* transceiver interface control */
 41#	define	COLActiveLow	0x0002
 42#	define	SerialMode	0x0004
 43#	define	ClkBit		0x0008
 44#	define	LinkStatus	0x0100
 45#define CHIPID          0x170   /* chip ID */
 46#define	MIFCSR		0x180   /* ??? */
 47#define	SROMCSR		0x190   /* SROM control */
 48#	define	ChipSelect	0x0001
 49#	define	Clk		0x0002
 50#define TXPNTR		0x1a0   /* transmit pointer */
 51#define	RXPNTR		0x1b0   /* receive pointer */
 52#define	STATUS		0x200   /* status--reading this clears it */
 53#define	INTDISABLE	0x210   /* interrupt enable/disable control */
 54/* bits below are the same in both STATUS and INTDISABLE registers */
 55#	define	FrameReceived	0x00000001 /* Received a frame */
 56#	define	RxFrameCntExp	0x00000002 /* Receive frame counter expired */
 57#	define	RxAlignCntExp	0x00000004 /* Align-error counter expired */
 58#	define	RxCRCCntExp	0x00000008 /* CRC-error counter expired */
 59#	define	RxLenCntExp	0x00000010 /* Length-error counter expired */
 60#	define	RxOverFlow	0x00000020 /* Receive FIFO overflow */
 61#	define	RxCodeViolation	0x00000040 /* Code-violation counter expired */
 62#	define	SQETestError	0x00000080 /* Test error in XIF for SQE */
 63#	define	FrameSent	0x00000100 /* Transmitted a frame */
 64#	define	TxUnderrun	0x00000200 /* Transmit FIFO underrun */
 65#	define	TxMaxSizeError	0x00000400 /* Max-packet size error */
 66#	define	TxNormalCollExp	0x00000800 /* Normal-collision counter expired */
 67#	define	TxExcessCollExp	0x00001000 /* Excess-collision counter expired */
 68#	define	TxLateCollExp	0x00002000 /* Late-collision counter expired */
 69#	define	TxNetworkCollExp 0x00004000 /* First-collision counter expired */
 70#	define	TxDeferTimerExp	0x00008000 /* Defer-timer expired */
 71#	define	RxFIFOToHost	0x00010000 /* Data moved from FIFO to host */
 72#	define	RxNoDescriptors	0x00020000 /* No more receive descriptors */
 73#	define	RxDMAError	0x00040000 /* Error during receive DMA */
 74#	define	RxDMALateErr	0x00080000 /* Receive DMA, data late */
 75#	define	RxParityErr	0x00100000 /* Parity error during receive DMA */
 76#	define	RxTagError	0x00200000 /* Tag error during receive DMA */
 77#	define	TxEOPError	0x00400000 /* Tx descriptor did not have EOP set */
 78#	define	MIFIntrEvent	0x00800000 /* MIF is signaling an interrupt */
 79#	define	TxHostToFIFO	0x01000000 /* Data moved from host to FIFO  */
 80#	define	TxFIFOAllSent	0x02000000 /* Transmitted all packets in FIFO */
 81#	define	TxDMAError	0x04000000 /* Error during transmit DMA */
 82#	define	TxDMALateError	0x08000000 /* Late error during transmit DMA */
 83#	define	TxParityError	0x10000000 /* Parity error during transmit DMA */
 84#	define	TxTagError	0x20000000 /* Tag error during transmit DMA */
 85#	define	PIOError	0x40000000 /* PIO access got an error */
 86#	define	PIOParityError	0x80000000 /* PIO access got a parity error  */
 87#	define	DisableAll	0xffffffff
 88#	define	EnableAll	0x00000000
 89/* #	define	NormalIntEvents	~(FrameReceived | FrameSent | TxUnderrun) */
 90#	define	EnableNormal	~(FrameReceived | FrameSent)
 91#	define	EnableErrors	(FrameReceived | FrameSent)
 92#	define	RxErrorMask	(RxFrameCntExp | RxAlignCntExp | RxCRCCntExp | \
 93				 RxLenCntExp | RxOverFlow | RxCodeViolation)
 94#	define	TxErrorMask	(TxUnderrun | TxMaxSizeError | TxExcessCollExp | \
 95				 TxLateCollExp | TxNetworkCollExp | TxDeferTimerExp)
 96
 97/* transmit control */
 98#define	TXRST		0x420   /* transmit reset */
 99#	define	TxResetBit	0x0001
100#define	TXCFG		0x430   /* transmit configuration control*/
101#	define	TxMACEnable	0x0001 /* output driver enable */
102#	define	TxSlowMode	0x0020 /* enable slow mode */
103#	define	TxIgnoreColl	0x0040 /* ignore transmit collisions */
104#	define	TxNoFCS		0x0080 /* do not emit FCS */
105#	define	TxNoBackoff	0x0100 /* no backoff in case of collisions */
106#	define	TxFullDuplex	0x0200 /* enable full-duplex */
107#	define	TxNeverGiveUp	0x0400 /* don't give up on transmits */
108#define IPG1		0x440   /* Inter-packet gap 1 */
109#define IPG2		0x450   /* Inter-packet gap 2 */
110#define ALIMIT		0x460   /* Transmit attempt limit */
111#define SLOT		0x470   /* Transmit slot time */
112#define PALEN		0x480   /* Size of transmit preamble */
113#define PAPAT		0x490   /* Pattern for transmit preamble */
114#define TXSFD		0x4a0   /* Transmit frame delimiter */
115#define JAM		0x4b0   /* Jam size */
116#define TXMAX		0x4c0   /* Transmit max pkt size */
117#define TXMIN		0x4d0   /* Transmit min pkt size */
118#define PAREG		0x4e0   /* Count of transmit peak attempts */
119#define DCNT		0x4f0   /* Transmit defer timer */
120#define NCCNT		0x500   /* Transmit normal-collision counter */
121#define NTCNT		0x510   /* Transmit first-collision counter */
122#define EXCNT		0x520   /* Transmit excess-collision counter */
123#define LTCNT		0x530   /* Transmit late-collision counter */
124#define RSEED		0x540   /* Transmit random number seed */
125#define TXSM		0x550   /* Transmit state machine */
126
127/* receive control */
128#define RXRST		0x620   /* receive reset */
129#	define	RxResetValue	0x0000
130#define RXCFG		0x630   /* receive configuration control */
131#	define	RxMACEnable	0x0001 /* receiver overall enable */
132#	define	RxCFGReserved	0x0004
133#	define	RxPadStripEnab	0x0020 /* enable pad byte stripping */
134#	define	RxPromiscEnable	0x0040 /* turn on promiscuous mode */
135#	define	RxNoErrCheck	0x0080 /* disable receive error checking */
136#	define	RxCRCNoStrip	0x0100 /* disable auto-CRC-stripping */
137#	define	RxRejectOwnPackets 0x0200 /* don't receive our own packets */
138#	define	RxGrpPromisck	0x0400 /* enable group promiscuous mode */
139#	define	RxHashFilterEnable 0x0800 /* enable hash filter */
140#	define	RxAddrFilterEnable 0x1000 /* enable address filter */
141#define RXMAX		0x640   /* Max receive packet size */
142#define RXMIN		0x650   /* Min receive packet size */
143#define MADD2		0x660   /* our enet address, high part */
144#define MADD1		0x670   /* our enet address, middle part */
145#define MADD0		0x680   /* our enet address, low part */
146#define FRCNT		0x690   /* receive frame counter */
147#define LECNT		0x6a0   /* Receive excess length error counter */
148#define AECNT		0x6b0   /* Receive misaligned error counter */
149#define FECNT		0x6c0   /* Receive CRC error counter */
150#define RXSM		0x6d0   /* Receive state machine */
151#define RXCV		0x6e0   /* Receive code violation */
152
153#define BHASH3		0x700   /* multicast hash register */
154#define BHASH2		0x710   /* multicast hash register */
155#define BHASH1		0x720   /* multicast hash register */
156#define BHASH0		0x730   /* multicast hash register */
157
158#define AFR2		0x740   /* address filtering setup? */
159#define AFR1		0x750   /* address filtering setup? */
160#define AFR0		0x760   /* address filtering setup? */
161#define AFCR		0x770   /* address filter compare register? */
162#	define	EnableAllCompares 0x0fff
163
164/* bits in XIFC */