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/drivers/net/wireless/adm8211.c

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C | 2007 lines | 1543 code | 346 blank | 118 comment | 205 complexity | 41b971452bc0e86e05b12019fe2c63f9 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0

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   1
   2/*
   3 * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
   4 *
   5 * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
   6 * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
   7 * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
   8 * and used with permission.
   9 *
  10 * Much thanks to Infineon-ADMtek for their support of this driver.
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License version 2 as
  14 * published by the Free Software Foundation. See README and COPYING for
  15 * more details.
  16 */
  17
  18#include <linux/init.h>
  19#include <linux/interrupt.h>
  20#include <linux/if.h>
  21#include <linux/skbuff.h>
  22#include <linux/slab.h>
  23#include <linux/etherdevice.h>
  24#include <linux/pci.h>
  25#include <linux/delay.h>
  26#include <linux/crc32.h>
  27#include <linux/eeprom_93cx6.h>
  28#include <net/mac80211.h>
  29
  30#include "adm8211.h"
  31
  32MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  33MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
  34MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
  35MODULE_SUPPORTED_DEVICE("ADM8211");
  36MODULE_LICENSE("GPL");
  37
  38static unsigned int tx_ring_size __read_mostly = 16;
  39static unsigned int rx_ring_size __read_mostly = 16;
  40
  41module_param(tx_ring_size, uint, 0);
  42module_param(rx_ring_size, uint, 0);
  43
  44static DEFINE_PCI_DEVICE_TABLE(adm8211_pci_id_table) = {
  45	/* ADMtek ADM8211 */
  46	{ PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
  47	{ PCI_DEVICE(0x1200, 0x8201) }, /* ? */
  48	{ PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
  49	{ PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
  50	{ 0 }
  51};
  52
  53static struct ieee80211_rate adm8211_rates[] = {
  54	{ .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  55	{ .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  56	{ .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  57	{ .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  58	{ .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
  59};
  60
  61static const struct ieee80211_channel adm8211_channels[] = {
  62	{ .center_freq = 2412},
  63	{ .center_freq = 2417},
  64	{ .center_freq = 2422},
  65	{ .center_freq = 2427},
  66	{ .center_freq = 2432},
  67	{ .center_freq = 2437},
  68	{ .center_freq = 2442},
  69	{ .center_freq = 2447},
  70	{ .center_freq = 2452},
  71	{ .center_freq = 2457},
  72	{ .center_freq = 2462},
  73	{ .center_freq = 2467},
  74	{ .center_freq = 2472},
  75	{ .center_freq = 2484},
  76};
  77
  78
  79static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
  80{
  81	struct adm8211_priv *priv = eeprom->data;
  82	u32 reg = ADM8211_CSR_READ(SPR);
  83
  84	eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
  85	eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
  86	eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
  87	eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
  88}
  89
  90static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
  91{
  92	struct adm8211_priv *priv = eeprom->data;
  93	u32 reg = 0x4000 | ADM8211_SPR_SRS;
  94
  95	if (eeprom->reg_data_in)
  96		reg |= ADM8211_SPR_SDI;
  97	if (eeprom->reg_data_out)
  98		reg |= ADM8211_SPR_SDO;
  99	if (eeprom->reg_data_clock)
 100		reg |= ADM8211_SPR_SCLK;
 101	if (eeprom->reg_chip_select)
 102		reg |= ADM8211_SPR_SCS;
 103
 104	ADM8211_CSR_WRITE(SPR, reg);
 105	ADM8211_CSR_READ(SPR);		/* eeprom_delay */
 106}
 107
 108static int adm8211_read_eeprom(struct ieee80211_hw *dev)
 109{
 110	struct adm8211_priv *priv = dev->priv;
 111	unsigned int words, i;
 112	struct ieee80211_chan_range chan_range;
 113	u16 cr49;
 114	struct eeprom_93cx6 eeprom = {
 115		.data		= priv,
 116		.register_read	= adm8211_eeprom_register_read,
 117		.register_write	= adm8211_eeprom_register_write
 118	};
 119
 120	if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
 121		/* 256 * 16-bit = 512 bytes */
 122		eeprom.width = PCI_EEPROM_WIDTH_93C66;
 123		words = 256;
 124	} else {
 125		/* 64 * 16-bit = 128 bytes */
 126		eeprom.width = PCI_EEPROM_WIDTH_93C46;
 127		words = 64;
 128	}
 129
 130	priv->eeprom_len = words * 2;
 131	priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
 132	if (!priv->eeprom)
 133		return -ENOMEM;
 134
 135	eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
 136
 137	cr49 = le16_to_cpu(priv->eeprom->cr49);
 138	priv->rf_type = (cr49 >> 3) & 0x7;
 139	switch (priv->rf_type) {
 140	case ADM8211_TYPE_INTERSIL:
 141	case ADM8211_TYPE_RFMD:
 142	case ADM8211_TYPE_MARVEL:
 143	case ADM8211_TYPE_AIROHA:
 144	case ADM8211_TYPE_ADMTEK:
 145		break;
 146
 147	default:
 148		if (priv->pdev->revision < ADM8211_REV_CA)
 149			priv->rf_type = ADM8211_TYPE_RFMD;
 150		else
 151			priv->rf_type = ADM8211_TYPE_AIROHA;
 152
 153		printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
 154		       pci_name(priv->pdev), (cr49 >> 3) & 0x7);
 155	}
 156
 157	priv->bbp_type = cr49 & 0x7;
 158	switch (priv->bbp_type) {
 159	case ADM8211_TYPE_INTERSIL:
 160	case ADM8211_TYPE_RFMD:
 161	case ADM8211_TYPE_MARVEL:
 162	case ADM8211_TYPE_AIROHA:
 163	case ADM8211_TYPE_ADMTEK:
 164		break;
 165	default:
 166		if (priv->pdev->revision < ADM8211_REV_CA)
 167			priv->bbp_type = ADM8211_TYPE_RFMD;
 168		else
 169			priv->bbp_type = ADM8211_TYPE_ADMTEK;
 170
 171		printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
 172		       pci_name(priv->pdev), cr49 >> 3);
 173	}
 174
 175	if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
 176		printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
 177		       pci_name(priv->pdev), priv->eeprom->country_code);
 178
 179		chan_range = cranges[2];
 180	} else
 181		chan_range = cranges[priv->eeprom->country_code];
 182
 183	printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
 184	       pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
 185
 186	BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
 187
 188	memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
 189	priv->band.channels = priv->channels;
 190	priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
 191	priv->band.bitrates = adm8211_rates;
 192	priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
 193
 194	for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
 195		if (i < chan_range.min || i > chan_range.max)
 196			priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
 197
 198	switch (priv->eeprom->specific_bbptype) {
 199	case ADM8211_BBP_RFMD3000:
 200	case ADM8211_BBP_RFMD3002:
 201	case ADM8211_BBP_ADM8011:
 202		priv->specific_bbptype = priv->eeprom->specific_bbptype;
 203		break;
 204
 205	default:
 206		if (priv->pdev->revision < ADM8211_REV_CA)
 207			priv->specific_bbptype = ADM8211_BBP_RFMD3000;
 208		else
 209			priv->specific_bbptype = ADM8211_BBP_ADM8011;
 210
 211		printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
 212		       pci_name(priv->pdev), priv->eeprom->specific_bbptype);
 213	}
 214
 215	switch (priv->eeprom->specific_rftype) {
 216	case ADM8211_RFMD2948:
 217	case ADM8211_RFMD2958:
 218	case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 219	case ADM8211_MAX2820:
 220	case ADM8211_AL2210L:
 221		priv->transceiver_type = priv->eeprom->specific_rftype;
 222		break;
 223
 224	default:
 225		if (priv->pdev->revision == ADM8211_REV_BA)
 226			priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
 227		else if (priv->pdev->revision == ADM8211_REV_CA)
 228			priv->transceiver_type = ADM8211_AL2210L;
 229		else if (priv->pdev->revision == ADM8211_REV_AB)
 230			priv->transceiver_type = ADM8211_RFMD2948;
 231
 232		printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
 233		       pci_name(priv->pdev), priv->eeprom->specific_rftype);
 234
 235		break;
 236	}
 237
 238	printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
 239               "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
 240	       priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
 241
 242	return 0;
 243}
 244
 245static inline void adm8211_write_sram(struct ieee80211_hw *dev,
 246				      u32 addr, u32 data)
 247{
 248	struct adm8211_priv *priv = dev->priv;
 249
 250	ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
 251			  (priv->pdev->revision < ADM8211_REV_BA ?
 252			   0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
 253	ADM8211_CSR_READ(WEPCTL);
 254	msleep(1);
 255
 256	ADM8211_CSR_WRITE(WESK, data);
 257	ADM8211_CSR_READ(WESK);
 258	msleep(1);
 259}
 260
 261static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
 262				     unsigned int addr, u8 *buf,
 263				     unsigned int len)
 264{
 265	struct adm8211_priv *priv = dev->priv;
 266	u32 reg = ADM8211_CSR_READ(WEPCTL);
 267	unsigned int i;
 268
 269	if (priv->pdev->revision < ADM8211_REV_BA) {
 270		for (i = 0; i < len; i += 2) {
 271			u16 val = buf[i] | (buf[i + 1] << 8);
 272			adm8211_write_sram(dev, addr + i / 2, val);
 273		}
 274	} else {
 275		for (i = 0; i < len; i += 4) {
 276			u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
 277				  (buf[i + 2] << 16) | (buf[i + 3] << 24);
 278			adm8211_write_sram(dev, addr + i / 4, val);
 279		}
 280	}
 281
 282	ADM8211_CSR_WRITE(WEPCTL, reg);
 283}
 284
 285static void adm8211_clear_sram(struct ieee80211_hw *dev)
 286{
 287	struct adm8211_priv *priv = dev->priv;
 288	u32 reg = ADM8211_CSR_READ(WEPCTL);
 289	unsigned int addr;
 290
 291	for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
 292		adm8211_write_sram(dev, addr, 0);
 293
 294	ADM8211_CSR_WRITE(WEPCTL, reg);
 295}
 296
 297static int adm8211_get_stats(struct ieee80211_hw *dev,
 298			     struct ieee80211_low_level_stats *stats)
 299{
 300	struct adm8211_priv *priv = dev->priv;
 301
 302	memcpy(stats, &priv->stats, sizeof(*stats));
 303
 304	return 0;
 305}
 306
 307static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
 308{
 309	struct adm8211_priv *priv = dev->priv;
 310	unsigned int dirty_tx;
 311
 312	spin_lock(&priv->lock);
 313
 314	for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
 315		unsigned int entry = dirty_tx % priv->tx_ring_size;
 316		u32 status = le32_to_cpu(priv->tx_ring[entry].status);
 317		struct ieee80211_tx_info *txi;
 318		struct adm8211_tx_ring_info *info;
 319		struct sk_buff *skb;
 320
 321		if (status & TDES0_CONTROL_OWN ||
 322		    !(status & TDES0_CONTROL_DONE))
 323			break;
 324
 325		info = &priv->tx_buffers[entry];
 326		skb = info->skb;
 327		txi = IEEE80211_SKB_CB(skb);
 328
 329		/* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
 330
 331		pci_unmap_single(priv->pdev, info->mapping,
 332				 info->skb->len, PCI_DMA_TODEVICE);
 333
 334		ieee80211_tx_info_clear_status(txi);
 335
 336		skb_pull(skb, sizeof(struct adm8211_tx_hdr));
 337		memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
 338		if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) &&
 339		    !(status & TDES0_STATUS_ES))
 340			txi->flags |= IEEE80211_TX_STAT_ACK;
 341
 342		ieee80211_tx_status_irqsafe(dev, skb);
 343
 344		info->skb = NULL;
 345	}
 346
 347	if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
 348		ieee80211_wake_queue(dev, 0);
 349
 350	priv->dirty_tx = dirty_tx;
 351	spin_unlock(&priv->lock);
 352}
 353
 354
 355static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
 356{
 357	struct adm8211_priv *priv = dev->priv;
 358	unsigned int entry = priv->cur_rx % priv->rx_ring_size;
 359	u32 status;
 360	unsigned int pktlen;
 361	struct sk_buff *skb, *newskb;
 362	unsigned int limit = priv->rx_ring_size;
 363	u8 rssi, rate;
 364
 365	while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
 366		if (!limit--)
 367			break;
 368
 369		status = le32_to_cpu(priv->rx_ring[entry].status);
 370		rate = (status & RDES0_STATUS_RXDR) >> 12;
 371		rssi = le32_to_cpu(priv->rx_ring[entry].length) &
 372			RDES1_STATUS_RSSI;
 373
 374		pktlen = status & RDES0_STATUS_FL;
 375		if (pktlen > RX_PKT_SIZE) {
 376			if (net_ratelimit())
 377				wiphy_debug(dev->wiphy, "frame too long (%d)\n",
 378					    pktlen);
 379			pktlen = RX_PKT_SIZE;
 380		}
 381
 382		if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
 383			skb = NULL; /* old buffer will be reused */
 384			/* TODO: update RX error stats */
 385			/* TODO: check RDES0_STATUS_CRC*E */
 386		} else if (pktlen < RX_COPY_BREAK) {
 387			skb = dev_alloc_skb(pktlen);
 388			if (skb) {
 389				pci_dma_sync_single_for_cpu(
 390					priv->pdev,
 391					priv->rx_buffers[entry].mapping,
 392					pktlen, PCI_DMA_FROMDEVICE);
 393				memcpy(skb_put(skb, pktlen),
 394				       skb_tail_pointer(priv->rx_buffers[entry].skb),
 395				       pktlen);
 396				pci_dma_sync_single_for_device(
 397					priv->pdev,
 398					priv->rx_buffers[entry].mapping,
 399					RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 400			}
 401		} else {
 402			newskb = dev_alloc_skb(RX_PKT_SIZE);
 403			if (newskb) {
 404				skb = priv->rx_buffers[entry].skb;
 405				skb_put(skb, pktlen);
 406				pci_unmap_single(
 407					priv->pdev,
 408					priv->rx_buffers[entry].mapping,
 409					RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 410				priv->rx_buffers[entry].skb = newskb;
 411				priv->rx_buffers[entry].mapping =
 412					pci_map_single(priv->pdev,
 413						       skb_tail_pointer(newskb),
 414						       RX_PKT_SIZE,
 415						       PCI_DMA_FROMDEVICE);
 416			} else {
 417				skb = NULL;
 418				/* TODO: update rx dropped stats */
 419			}
 420
 421			priv->rx_ring[entry].buffer1 =
 422				cpu_to_le32(priv->rx_buffers[entry].mapping);
 423		}
 424
 425		priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
 426							  RDES0_STATUS_SQL);
 427		priv->rx_ring[entry].length =
 428			cpu_to_le32(RX_PKT_SIZE |
 429				    (entry == priv->rx_ring_size - 1 ?
 430				     RDES1_CONTROL_RER : 0));
 431
 432		if (skb) {
 433			struct ieee80211_rx_status rx_status = {0};
 434
 435			if (priv->pdev->revision < ADM8211_REV_CA)
 436				rx_status.signal = rssi;
 437			else
 438				rx_status.signal = 100 - rssi;
 439
 440			rx_status.rate_idx = rate;
 441
 442			rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
 443			rx_status.band = IEEE80211_BAND_2GHZ;
 444
 445			memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
 446			ieee80211_rx_irqsafe(dev, skb);
 447		}
 448
 449		entry = (++priv->cur_rx) % priv->rx_ring_size;
 450	}
 451
 452	/* TODO: check LPC and update stats? */
 453}
 454
 455
 456static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
 457{
 458#define ADM8211_INT(x)						\
 459do {								\
 460	if (unlikely(stsr & ADM8211_STSR_ ## x))		\
 461		wiphy_debug(dev->wiphy, "%s\n", #x);		\
 462} while (0)
 463
 464	struct ieee80211_hw *dev = dev_id;
 465	struct adm8211_priv *priv = dev->priv;
 466	u32 stsr = ADM8211_CSR_READ(STSR);
 467	ADM8211_CSR_WRITE(STSR, stsr);
 468	if (stsr == 0xffffffff)
 469		return IRQ_HANDLED;
 470
 471	if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
 472		return IRQ_HANDLED;
 473
 474	if (stsr & ADM8211_STSR_RCI)
 475		adm8211_interrupt_rci(dev);
 476	if (stsr & ADM8211_STSR_TCI)
 477		adm8211_interrupt_tci(dev);
 478
 479	ADM8211_INT(PCF);
 480	ADM8211_INT(BCNTC);
 481	ADM8211_INT(GPINT);
 482	ADM8211_INT(ATIMTC);
 483	ADM8211_INT(TSFTF);
 484	ADM8211_INT(TSCZ);
 485	ADM8211_INT(SQL);
 486	ADM8211_INT(WEPTD);
 487	ADM8211_INT(ATIME);
 488	ADM8211_INT(TEIS);
 489	ADM8211_INT(FBE);
 490	ADM8211_INT(REIS);
 491	ADM8211_INT(GPTT);
 492	ADM8211_INT(RPS);
 493	ADM8211_INT(RDU);
 494	ADM8211_INT(TUF);
 495	ADM8211_INT(TPS);
 496
 497	return IRQ_HANDLED;
 498
 499#undef ADM8211_INT
 500}
 501
 502#define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
 503static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,	     \
 504					   u16 addr, u32 value) {	     \
 505	struct adm8211_priv *priv = dev->priv;				     \
 506	unsigned int i;							     \
 507	u32 reg, bitbuf;						     \
 508									     \
 509	value &= v_mask;						     \
 510	addr &= a_mask;							     \
 511	bitbuf = (value << v_shift) | (addr << a_shift);		     \
 512									     \
 513	ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);		     \
 514	ADM8211_CSR_READ(SYNRF);					     \
 515	ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);		     \
 516	ADM8211_CSR_READ(SYNRF);					     \
 517									     \
 518	if (prewrite) {							     \
 519		ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
 520		ADM8211_CSR_READ(SYNRF);				     \
 521	}								     \
 522									     \
 523	for (i = 0; i <= bits; i++) {					     \
 524		if (bitbuf & (1 << (bits - i)))				     \
 525			reg = ADM8211_SYNRF_WRITE_SYNDATA_1;		     \
 526		else							     \
 527			reg = ADM8211_SYNRF_WRITE_SYNDATA_0;		     \
 528									     \
 529		ADM8211_CSR_WRITE(SYNRF, reg);				     \
 530		ADM8211_CSR_READ(SYNRF);				     \
 531									     \
 532		ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
 533		ADM8211_CSR_READ(SYNRF);				     \
 534		ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
 535		ADM8211_CSR_READ(SYNRF);				     \
 536	}								     \
 537									     \
 538	if (postwrite == 1) {						     \
 539		ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
 540		ADM8211_CSR_READ(SYNRF);				     \
 541	}								     \
 542	if (postwrite == 2) {						     \
 543		ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
 544		ADM8211_CSR_READ(SYNRF);				     \
 545	}								     \
 546									     \
 547	ADM8211_CSR_WRITE(SYNRF, 0);					     \
 548	ADM8211_CSR_READ(SYNRF);					     \
 549}
 550
 551WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
 552WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
 553WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
 554WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
 555
 556#undef WRITE_SYN
 557
 558static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
 559{
 560	struct adm8211_priv *priv = dev->priv;
 561	unsigned int timeout;
 562	u32 reg;
 563
 564	timeout = 10;
 565	while (timeout > 0) {
 566		reg = ADM8211_CSR_READ(BBPCTL);
 567		if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
 568			break;
 569		timeout--;
 570		msleep(2);
 571	}
 572
 573	if (timeout == 0) {
 574		wiphy_debug(dev->wiphy,
 575			    "adm8211_write_bbp(%d,%d) failed prewrite (reg=0x%08x)\n",
 576			    addr, data, reg);
 577		return -ETIMEDOUT;
 578	}
 579
 580	switch (priv->bbp_type) {
 581	case ADM8211_TYPE_INTERSIL:
 582		reg = ADM8211_BBPCTL_MMISEL;	/* three wire interface */
 583		break;
 584	case ADM8211_TYPE_RFMD:
 585		reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 586		      (0x01 << 18);
 587		break;
 588	case ADM8211_TYPE_ADMTEK:
 589		reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 590		      (0x05 << 18);
 591		break;
 592	}
 593	reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
 594
 595	ADM8211_CSR_WRITE(BBPCTL, reg);
 596
 597	timeout = 10;
 598	while (timeout > 0) {
 599		reg = ADM8211_CSR_READ(BBPCTL);
 600		if (!(reg & ADM8211_BBPCTL_WR))
 601			break;
 602		timeout--;
 603		msleep(2);
 604	}
 605
 606	if (timeout == 0) {
 607		ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
 608				  ~ADM8211_BBPCTL_WR);
 609		wiphy_debug(dev->wiphy,
 610			    "adm8211_write_bbp(%d,%d) failed postwrite (reg=0x%08x)\n",
 611			    addr, data, reg);
 612		return -ETIMEDOUT;
 613	}
 614
 615	return 0;
 616}
 617
 618static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
 619{
 620	static const u32 adm8211_rfmd2958_reg5[] =
 621		{0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
 622		 0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
 623	static const u32 adm8211_rfmd2958_reg6[] =
 624		{0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
 625		 0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
 626
 627	struct adm8211_priv *priv = dev->priv;
 628	u8 ant_power = priv->ant_power > 0x3F ?
 629		priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
 630	u8 tx_power = priv->tx_power > 0x3F ?
 631		priv->eeprom->tx_power[chan - 1] : priv->tx_power;
 632	u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
 633		priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
 634	u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
 635		priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
 636	u32 reg;
 637
 638	ADM8211_IDLE();
 639
 640	/* Program synthesizer to new channel */
 641	switch (priv->transceiver_type) {
 642	case ADM8211_RFMD2958:
 643	case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 644		adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
 645		adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
 646
 647		adm8211_rf_write_syn_rfmd2958(dev, 0x05,
 648			adm8211_rfmd2958_reg5[chan - 1]);
 649		adm8211_rf_write_syn_rfmd2958(dev, 0x06,
 650			adm8211_rfmd2958_reg6[chan - 1]);
 651		break;
 652
 653	case ADM8211_RFMD2948:
 654		adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
 655					      SI4126_MAIN_XINDIV2);
 656		adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
 657					      SI4126_POWERDOWN_PDIB |
 658					      SI4126_POWERDOWN_PDRB);
 659		adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
 660		adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
 661					      (chan == 14 ?
 662					       2110 : (2033 + (chan * 5))));
 663		adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
 664		adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
 665		adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
 666		break;
 667
 668	case ADM8211_MAX2820:
 669		adm8211_rf_write_syn_max2820(dev, 0x3,
 670			(chan == 14 ? 0x054 : (0x7 + (chan * 5))));
 671		break;
 672
 673	case ADM8211_AL2210L:
 674		adm8211_rf_write_syn_al2210l(dev, 0x0,
 675			(chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
 676		break;
 677
 678	default:
 679		wiphy_debug(dev->wiphy, "unsupported transceiver type %d\n",
 680			    priv->transceiver_type);
 681		break;
 682	}
 683
 684	/* write BBP regs */
 685	if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 686
 687	/* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
 688	/* TODO: remove if SMC 2635W doesn't need this */
 689	if (priv->transceiver_type == ADM8211_RFMD2948) {
 690		reg = ADM8211_CSR_READ(GPIO);
 691		reg &= 0xfffc0000;
 692		reg |= ADM8211_CSR_GPIO_EN0;
 693		if (chan != 14)
 694			reg |= ADM8211_CSR_GPIO_O0;
 695		ADM8211_CSR_WRITE(GPIO, reg);
 696	}
 697
 698	if (priv->transceiver_type == ADM8211_RFMD2958) {
 699		/* set PCNT2 */
 700		adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
 701		/* set PCNT1 P_DESIRED/MID_BIAS */
 702		reg = le16_to_cpu(priv->eeprom->cr49);
 703		reg >>= 13;
 704		reg <<= 15;
 705		reg |= ant_power << 9;
 706		adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
 707		/* set TXRX TX_GAIN */
 708		adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
 709			(priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
 710	} else {
 711		reg = ADM8211_CSR_READ(PLCPHD);
 712		reg &= 0xff00ffff;
 713		reg |= tx_power << 18;
 714		ADM8211_CSR_WRITE(PLCPHD, reg);
 715	}
 716
 717	ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 718			  ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 719	ADM8211_CSR_READ(SYNRF);
 720	msleep(30);
 721
 722	/* RF3000 BBP */
 723	if (priv->transceiver_type != ADM8211_RFMD2958)
 724		adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
 725				  tx_power<<2);
 726	adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
 727	adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
 728	adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
 729				     priv->eeprom->cr28 : 0);
 730	adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 731
 732	ADM8211_CSR_WRITE(SYNRF, 0);
 733
 734	/* Nothing to do for ADMtek BBP */
 735	} else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
 736		wiphy_debug(dev->wiphy, "unsupported BBP type %d\n",
 737			    priv->bbp_type);
 738
 739	ADM8211_RESTORE();
 740
 741	/* update current channel for adhoc (and maybe AP mode) */
 742	reg = ADM8211_CSR_READ(CAP0);
 743	reg &= ~0xF;
 744	reg |= chan;
 745	ADM8211_CSR_WRITE(CAP0, reg);
 746
 747	return 0;
 748}
 749
 750static void adm8211_update_mode(struct ieee80211_hw *dev)
 751{
 752	struct adm8211_priv *priv = dev->priv;
 753
 754	ADM8211_IDLE();
 755
 756	priv->soft_rx_crc = 0;
 757	switch (priv->mode) {
 758	case NL80211_IFTYPE_STATION:
 759		priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
 760		priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
 761		break;
 762	case NL80211_IFTYPE_ADHOC:
 763		priv->nar &= ~ADM8211_NAR_PR;
 764		priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
 765
 766		/* don't trust the error bits on rev 0x20 and up in adhoc */
 767		if (priv->pdev->revision >= ADM8211_REV_BA)
 768			priv->soft_rx_crc = 1;
 769		break;
 770	case NL80211_IFTYPE_MONITOR:
 771		priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
 772		priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
 773		break;
 774	}
 775
 776	ADM8211_RESTORE();
 777}
 778
 779static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
 780{
 781	struct adm8211_priv *priv = dev->priv;
 782
 783	switch (priv->transceiver_type) {
 784	case ADM8211_RFMD2958:
 785	case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 786		/* comments taken from ADMtek vendor driver */
 787
 788		/* Reset RF2958 after power on */
 789		adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
 790		/* Initialize RF VCO Core Bias to maximum */
 791		adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
 792		/* Initialize IF PLL */
 793		adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
 794		/* Initialize IF PLL Coarse Tuning */
 795		adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
 796		/* Initialize RF PLL */
 797		adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
 798		/* Initialize RF PLL Coarse Tuning */
 799		adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
 800		/* Initialize TX gain and filter BW (R9) */
 801		adm8211_rf_write_syn_rfmd2958(dev, 0x09,
 802			(priv->transceiver_type == ADM8211_RFMD2958 ?
 803			 0x10050 : 0x00050));
 804		/* Initialize CAL register */
 805		adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
 806		break;
 807
 808	case ADM8211_MAX2820:
 809		adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
 810		adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
 811		adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
 812		adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
 813		adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
 814		break;
 815
 816	case ADM8211_AL2210L:
 817		adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
 818		adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
 819		adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
 820		adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
 821		adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
 822		adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
 823		adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
 824		adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
 825		adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
 826		adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
 827		adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
 828		adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
 829		break;
 830
 831	case ADM8211_RFMD2948:
 832	default:
 833		break;
 834	}
 835}
 836
 837static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
 838{
 839	struct adm8211_priv *priv = dev->priv;
 840	u32 reg;
 841
 842	/* write addresses */
 843	if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
 844		ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
 845		ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
 846		ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
 847	} else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
 848		   priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 849		/* check specific BBP type */
 850		switch (priv->specific_bbptype) {
 851		case ADM8211_BBP_RFMD3000:
 852		case ADM8211_BBP_RFMD3002:
 853			ADM8211_CSR_WRITE(MMIWA,  0x00009101);
 854			ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
 855			break;
 856
 857		case ADM8211_BBP_ADM8011:
 858			ADM8211_CSR_WRITE(MMIWA,  0x00008903);
 859			ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
 860
 861			reg = ADM8211_CSR_READ(BBPCTL);
 862			reg &= ~ADM8211_BBPCTL_TYPE;
 863			reg |= 0x5 << 18;
 864			ADM8211_CSR_WRITE(BBPCTL, reg);
 865			break;
 866		}
 867
 868		switch (priv->pdev->revision) {
 869		case ADM8211_REV_CA:
 870			if (priv->transceiver_type == ADM8211_RFMD2958 ||
 871			    priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
 872			    priv->transceiver_type == ADM8211_RFMD2948)
 873				ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
 874			else if (priv->transceiver_type == ADM8211_MAX2820 ||
 875				 priv->transceiver_type == ADM8211_AL2210L)
 876				ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
 877			break;
 878
 879		case ADM8211_REV_BA:
 880			reg  = ADM8211_CSR_READ(MMIRD1);
 881			reg &= 0x0000FFFF;
 882			reg |= 0x7e100000;
 883			ADM8211_CSR_WRITE(MMIRD1, reg);
 884			break;
 885
 886		case ADM8211_REV_AB:
 887		case ADM8211_REV_AF:
 888		default:
 889			ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
 890			break;
 891		}
 892
 893		/* For RFMD */
 894		ADM8211_CSR_WRITE(MACTEST, 0x800);
 895	}
 896
 897	adm8211_hw_init_syn(dev);
 898
 899	/* Set RF Power control IF pin to PE1+PHYRST# */
 900	ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 901			  ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 902	ADM8211_CSR_READ(SYNRF);
 903	msleep(20);
 904
 905	/* write BBP regs */
 906	if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 907		/* RF3000 BBP */
 908		/* another set:
 909		 * 11: c8
 910		 * 14: 14
 911		 * 15: 50 (chan 1..13; chan 14: d0)
 912		 * 1c: 00
 913		 * 1d: 84
 914		 */
 915		adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
 916		/* antenna selection: diversity */
 917		adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
 918		adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
 919		adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
 920		adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
 921
 922		if (priv->eeprom->major_version < 2) {
 923			adm8211_write_bbp(dev, 0x1c, 0x00);
 924			adm8211_write_bbp(dev, 0x1d, 0x80);
 925		} else {
 926			if (priv->pdev->revision == ADM8211_REV_BA)
 927				adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
 928			else
 929				adm8211_write_bbp(dev, 0x1c, 0x00);
 930
 931			adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 932		}
 933	} else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 934		/* reset baseband */
 935		adm8211_write_bbp(dev, 0x00, 0xFF);
 936		/* antenna selection: diversity */
 937		adm8211_write_bbp(dev, 0x07, 0x0A);
 938
 939		/* TODO: find documentation for this */
 940		switch (priv->transceiver_type) {
 941		case ADM8211_RFMD2958:
 942		case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 943			adm8211_write_bbp(dev, 0x00, 0x00);
 944			adm8211_write_bbp(dev, 0x01, 0x00);
 945			adm8211_write_bbp(dev, 0x02, 0x00);
 946			adm8211_write_bbp(dev, 0x03, 0x00);
 947			adm8211_write_bbp(dev, 0x06, 0x0f);
 948			adm8211_write_bbp(dev, 0x09, 0x00);
 949			adm8211_write_bbp(dev, 0x0a, 0x00);
 950			adm8211_write_bbp(dev, 0x0b, 0x00);
 951			adm8211_write_bbp(dev, 0x0c, 0x00);
 952			adm8211_write_bbp(dev, 0x0f, 0xAA);
 953			adm8211_write_bbp(dev, 0x10, 0x8c);
 954			adm8211_write_bbp(dev, 0x11, 0x43);
 955			adm8211_write_bbp(dev, 0x18, 0x40);
 956			adm8211_write_bbp(dev, 0x20, 0x23);
 957			adm8211_write_bbp(dev, 0x21, 0x02);
 958			adm8211_write_bbp(dev, 0x22, 0x28);
 959			adm8211_write_bbp(dev, 0x23, 0x30);
 960			adm8211_write_bbp(dev, 0x24, 0x2d);
 961			adm8211_write_bbp(dev, 0x28, 0x35);
 962			adm8211_write_bbp(dev, 0x2a, 0x8c);
 963			adm8211_write_bbp(dev, 0x2b, 0x81);
 964			adm8211_write_bbp(dev, 0x2c, 0x44);
 965			adm8211_write_bbp(dev, 0x2d, 0x0A);
 966			adm8211_write_bbp(dev, 0x29, 0x40);
 967			adm8211_write_bbp(dev, 0x60, 0x08);
 968			adm8211_write_bbp(dev, 0x64, 0x01);
 969			break;
 970
 971		case ADM8211_MAX2820:
 972			adm8211_write_bbp(dev, 0x00, 0x00);
 973			adm8211_write_bbp(dev, 0x01, 0x00);
 974			adm8211_write_bbp(dev, 0x02, 0x00);
 975			adm8211_write_bbp(dev, 0x03, 0x00);
 976			adm8211_write_bbp(dev, 0x06, 0x0f);
 977			adm8211_write_bbp(dev, 0x09, 0x05);
 978			adm8211_write_bbp(dev, 0x0a, 0x02);
 979			adm8211_write_bbp(dev, 0x0b, 0x00);
 980			adm8211_write_bbp(dev, 0x0c, 0x0f);
 981			adm8211_write_bbp(dev, 0x0f, 0x55);
 982			adm8211_write_bbp(dev, 0x10, 0x8d);
 983			adm8211_write_bbp(dev, 0x11, 0x43);
 984			adm8211_write_bbp(dev, 0x18, 0x4a);
 985			adm8211_write_bbp(dev, 0x20, 0x20);
 986			adm8211_write_bbp(dev, 0x21, 0x02);
 987			adm8211_write_bbp(dev, 0x22, 0x23);
 988			adm8211_write_bbp(dev, 0x23, 0x30);
 989			adm8211_write_bbp(dev, 0x24, 0x2d);
 990			adm8211_write_bbp(dev, 0x2a, 0x8c);
 991			adm8211_write_bbp(dev, 0x2b, 0x81);
 992			adm8211_write_bbp(dev, 0x2c, 0x44);
 993			adm8211_write_bbp(dev, 0x29, 0x4a);
 994			adm8211_write_bbp(dev, 0x60, 0x2b);
 995			adm8211_write_bbp(dev, 0x64, 0x01);
 996			break;
 997
 998		case ADM8211_AL2210L:
 999			adm8211_write_bbp(dev, 0x00, 0x00);
1000			adm8211_write_bbp(dev, 0x01, 0x00);
1001			adm8211_write_bbp(dev, 0x02, 0x00);
1002			adm8211_write_bbp(dev, 0x03, 0x00);
1003			adm8211_write_bbp(dev, 0x06, 0x0f);
1004			adm8211_write_bbp(dev, 0x07, 0x05);
1005			adm8211_write_bbp(dev, 0x08, 0x03);
1006			adm8211_write_bbp(dev, 0x09, 0x00);
1007			adm8211_write_bbp(dev, 0x0a, 0x00);
1008			adm8211_write_bbp(dev, 0x0b, 0x00);
1009			adm8211_write_bbp(dev, 0x0c, 0x10);
1010			adm8211_write_bbp(dev, 0x0f, 0x55);
1011			adm8211_write_bbp(dev, 0x10, 0x8d);
1012			adm8211_write_bbp(dev, 0x11, 0x43);
1013			adm8211_write_bbp(dev, 0x18, 0x4a);
1014			adm8211_write_bbp(dev, 0x20, 0x20);
1015			adm8211_write_bbp(dev, 0x21, 0x02);
1016			adm8211_write_bbp(dev, 0x22, 0x23);
1017			adm8211_write_bbp(dev, 0x23, 0x30);
1018			adm8211_write_bbp(dev, 0x24, 0x2d);
1019			adm8211_write_bbp(dev, 0x2a, 0xaa);
1020			adm8211_write_bbp(dev, 0x2b, 0x81);
1021			adm8211_write_bbp(dev, 0x2c, 0x44);
1022			adm8211_write_bbp(dev, 0x29, 0xfa);
1023			adm8211_write_bbp(dev, 0x60, 0x2d);
1024			adm8211_write_bbp(dev, 0x64, 0x01);
1025			break;
1026
1027		case ADM8211_RFMD2948:
1028			break;
1029
1030		default:
1031			wiphy_debug(dev->wiphy, "unsupported transceiver %d\n",
1032				    priv->transceiver_type);
1033			break;
1034		}
1035	} else
1036		wiphy_debug(dev->wiphy, "unsupported BBP %d\n", priv->bbp_type);
1037
1038	ADM8211_CSR_WRITE(SYNRF, 0);
1039
1040	/* Set RF CAL control source to MAC control */
1041	reg = ADM8211_CSR_READ(SYNCTL);
1042	reg |= ADM8211_SYNCTL_SELCAL;
1043	ADM8211_CSR_WRITE(SYNCTL, reg);
1044
1045	return 0;
1046}
1047
1048/* configures hw beacons/probe responses */
1049static int adm8211_set_rate(struct ieee80211_hw *dev)
1050{
1051	struct adm8211_priv *priv = dev->priv;
1052	u32 reg;
1053	int i = 0;
1054	u8 rate_buf[12] = {0};
1055
1056	/* write supported rates */
1057	if (priv->pdev->revision != ADM8211_REV_BA) {
1058		rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1059		for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1060			rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
1061	} else {
1062		/* workaround for rev BA specific bug */
1063		rate_buf[0] = 0x04;
1064		rate_buf[1] = 0x82;
1065		rate_buf[2] = 0x04;
1066		rate_buf[3] = 0x0b;
1067		rate_buf[4] = 0x16;
1068	}
1069
1070	adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1071				 ARRAY_SIZE(adm8211_rates) + 1);
1072
1073	reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1074	reg |= 1 << 15;	/* short preamble */
1075	reg |= 110 << 24;
1076	ADM8211_CSR_WRITE(PLCPHD, reg);
1077
1078	/* MTMLT   = 512 TU (max TX MSDU lifetime)
1079	 * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1080	 * SRTYLIM = 224 (short retry limit, TX header value is default) */
1081	ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1082
1083	return 0;
1084}
1085
1086static void adm8211_hw_init(struct ieee80211_hw *dev)
1087{
1088	struct adm8211_priv *priv = dev->priv;
1089	u32 reg;
1090	u8 cline;
1091
1092	reg = ADM8211_CSR_READ(PAR);
1093	reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1094	reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1095
1096	if (!pci_set_mwi(priv->pdev)) {
1097		reg |= 0x1 << 24;
1098		pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1099
1100		switch (cline) {
1101		case  0x8: reg |= (0x1 << 14);
1102			   break;
1103		case 0x16: reg |= (0x2 << 14);
1104			   break;
1105		case 0x32: reg |= (0x3 << 14);
1106			   break;
1107		  default: reg |= (0x0 << 14);
1108			   break;
1109		}
1110	}
1111
1112	ADM8211_CSR_WRITE(PAR, reg);
1113
1114	reg = ADM8211_CSR_READ(CSR_TEST1);
1115	reg &= ~(0xF << 28);
1116	reg |= (1 << 28) | (1 << 31);
1117	ADM8211_CSR_WRITE(CSR_TEST1, reg);
1118
1119	/* lose link after 4 lost beacons */
1120	reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1121	ADM8211_CSR_WRITE(WCSR, reg);
1122
1123	/* Disable APM, enable receive FIFO threshold, and set drain receive
1124	 * threshold to store-and-forward */
1125	reg = ADM8211_CSR_READ(CMDR);
1126	reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1127	reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1128	ADM8211_CSR_WRITE(CMDR, reg);
1129
1130	adm8211_set_rate(dev);
1131
1132	/* 4-bit values:
1133	 * PWR1UP   = 8 * 2 ms
1134	 * PWR0PAPE = 8 us or 5 us
1135	 * PWR1PAPE = 1 us or 3 us
1136	 * PWR0TRSW = 5 us
1137	 * PWR1TRSW = 12 us
1138	 * PWR0PE2  = 13 us
1139	 * PWR1PE2  = 1 us
1140	 * PWR0TXPE = 8 or 6 */
1141	if (priv->pdev->revision < ADM8211_REV_CA)
1142		ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1143	else
1144		ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1145
1146	/* Enable store and forward for transmit */
1147	priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1148	ADM8211_CSR_WRITE(NAR, priv->nar);
1149
1150	/* Reset RF */
1151	ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1152	ADM8211_CSR_READ(SYNRF);
1153	msleep(10);
1154	ADM8211_CSR_WRITE(SYNRF, 0);
1155	ADM8211_CSR_READ(SYNRF);
1156	msleep(5);
1157
1158	/* Set CFP Max Duration to 0x10 TU */
1159	reg = ADM8211_CSR_READ(CFPP);
1160	reg &= ~(0xffff << 8);
1161	reg |= 0x0010 << 8;
1162	ADM8211_CSR_WRITE(CFPP, reg);
1163
1164	/* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1165	 * TUCNT = 0x3ff - Tu counter 1024 us  */
1166	ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1167
1168	/* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1169	 * DIFS=50 us, EIFS=100 us */
1170	if (priv->pdev->revision < ADM8211_REV_CA)
1171		ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1172					(50 << 9)  | 100);
1173	else
1174		ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1175					(50 << 9)  | 100);
1176
1177	/* PCNT = 1 (MAC idle time awake/sleep, unit S)
1178	 * RMRD = 2346 * 8 + 1 us (max RX duration)  */
1179	ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1180
1181	/* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1182	ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1183
1184	/* Initialize BBP (and SYN) */
1185	adm8211_hw_init_bbp(dev);
1186
1187	/* make sure interrupts are off */
1188	ADM8211_CSR_WRITE(IER, 0);
1189
1190	/* ACK interrupts */
1191	ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1192
1193	/* Setup WEP (turns it off for now) */
1194	reg = ADM8211_CSR_READ(MACTEST);
1195	reg &= ~(7 << 20);
1196	ADM8211_CSR_WRITE(MACTEST, reg);
1197
1198	reg = ADM8211_CSR_READ(WEPCTL);
1199	reg &= ~ADM8211_WEPCTL_WEPENABLE;
1200	reg |= ADM8211_WEPCTL_WEPRXBYP;
1201	ADM8211_CSR_WRITE(WEPCTL, reg);
1202
1203	/* Clear the missed-packet counter. */
1204	ADM8211_CSR_READ(LPC);
1205}
1206
1207static int adm8211_hw_reset(struct ieee80211_hw *dev)
1208{
1209	struct adm8211_priv *priv = dev->priv;
1210	u32 reg, tmp;
1211	int timeout = 100;
1212
1213	/* Power-on issue */
1214	/* TODO: check if this is necessary */
1215	ADM8211_CSR_WRITE(FRCTL, 0);
1216
1217	/* Reset the chip */
1218	tmp = ADM8211_CSR_READ(PAR);
1219	ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1220
1221	while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1222		msleep(50);
1223
1224	if (timeout <= 0)
1225		return -ETIMEDOUT;
1226
1227	ADM8211_CSR_WRITE(PAR, tmp);
1228
1229	if (priv->pdev->revision == ADM8211_REV_BA &&
1230	    (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1231	     priv->transceiver_type == ADM8211_RFMD2958)) {
1232		reg = ADM8211_CSR_READ(CSR_TEST1);
1233		reg |= (1 << 4) | (1 << 5);
1234		ADM8211_CSR_WRITE(CSR_TEST1, reg);
1235	} else if (priv->pdev->revision == ADM8211_REV_CA) {
1236		reg = ADM8211_CSR_READ(CSR_TEST1);
1237		reg &= ~((1 << 4) | (1 << 5));
1238		ADM8211_CSR_WRITE(CSR_TEST1, reg);
1239	}
1240
1241	ADM8211_CSR_WRITE(FRCTL, 0);
1242
1243	reg = ADM8211_CSR_READ(CSR_TEST0);
1244	reg |= ADM8211_CSR_TEST0_EPRLD;	/* EEPROM Recall */
1245	ADM8211_CSR_WRITE(CSR_TEST0, reg);
1246
1247	adm8211_clear_sram(dev);
1248
1249	return 0;
1250}
1251
1252static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1253{
1254	struct adm8211_priv *priv = dev->priv;
1255	u32 tsftl;
1256	u64 tsft;
1257
1258	tsftl = ADM8211_CSR_READ(TSFTL);
1259	tsft = ADM8211_CSR_READ(TSFTH);
1260	tsft <<= 32;
1261	tsft |= tsftl;
1262
1263	return tsft;
1264}
1265
1266static void adm8211_set_interval(struct ieee80211_hw *dev,
1267				 unsigned short bi, unsigned short li)
1268{
1269	struct adm8211_priv *priv = dev->priv;
1270	u32 reg;
1271
1272	/* BP (beacon interval) = data->beacon_interval
1273	 * LI (listen interval) = data->listen_interval (in beacon intervals) */
1274	reg = (bi << 16) | li;
1275	ADM8211_CSR_WRITE(BPLI, reg);
1276}
1277
1278static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1279{
1280	struct adm8211_priv *priv = dev->priv;
1281	u32 reg;
1282
1283	ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1284	reg = ADM8211_CSR_READ(ABDA1);
1285	reg &= 0x0000ffff;
1286	reg |= (bssid[4] << 16) | (bssid[5] << 24);
1287	ADM8211_CSR_WRITE(ABDA1, reg);
1288}
1289
1290static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
1291{
1292	struct adm8211_priv *priv = dev->priv;
1293	struct ieee80211_conf *conf = &dev->conf;
1294	int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
1295
1296	if (channel != priv->channel) {
1297		priv->channel = channel;
1298		adm8211_rf_set_channel(dev, priv->channel);
1299	}
1300
1301	return 0;
1302}
1303
1304static void adm8211_bss_info_changed(struct ieee80211_hw *dev,
1305				     struct ieee80211_vif *vif,
1306				     struct ieee80211_bss_conf *conf,
1307				     u32 changes)
1308{
1309	struct adm8211_priv *priv = dev->priv;
1310
1311	if (!(changes & BSS_CHANGED_BSSID))
1312		return;
1313
1314	if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1315		adm8211_set_bssid(dev, conf->bssid);
1316		memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1317	}
1318}
1319
1320static u64 adm8211_prepare_multicast(struct ieee80211_hw *hw,
1321				     struct netdev_hw_addr_list *mc_list)
1322{
1323	unsigned int bit_nr;
1324	u32 mc_filter[2];
1325	struct netdev_hw_addr *ha;
1326
1327	mc_filter[1] = mc_filter[0] = 0;
1328
1329	netdev_hw_addr_list_for_each(ha, mc_list) {
1330		bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1331
1332		bit_nr &= 0x3F;
1333		mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1334	}
1335
1336	return mc_filter[0] | ((u64)(mc_filter[1]) << 32);
1337}
1338
1339static void adm8211_configure_filter(struct ieee80211_hw *dev,
1340				     unsigned int changed_flags,
1341				     unsigned int *total_flags,
1342				     u64 multicast)
1343{
1344	static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1345	struct adm8211_priv *priv = dev->priv;
1346	unsigned int new_flags;
1347	u32 mc_filter[2];
1348
1349	mc_filter[0] = multicast;
1350	mc_filter[1] = multicast >> 32;
1351
1352	new_flags = 0;
1353
1354	if (*total_flags & FIF_PROMISC_IN_BSS) {
1355		new_flags |= FIF_PROMISC_IN_BSS;
1356		priv->nar |= ADM8211_NAR_PR;
1357		priv->nar &= ~ADM8211_NAR_MM;
1358		mc_filter[1] = mc_filter[0] = ~0;
1359	} else if (*total_flags & FIF_ALLMULTI || multicast == ~(0ULL)) {
1360		new_flags |= FIF_ALLMULTI;
1361		priv->nar &= ~ADM8211_NAR_PR;
1362		priv->nar |= ADM8211_NAR_MM;
1363		mc_filter[1] = mc_filter[0] = ~0;
1364	} else {
1365		priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1366	}
1367
1368	ADM8211_IDLE_RX();
1369
1370	ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1371	ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1372	ADM8211_CSR_READ(NAR);
1373
1374	if (priv->nar & ADM8211_NAR_PR)
1375		dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1376	else
1377		dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1378
1379	if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1380		adm8211_set_bssid(dev, bcast);
1381	else
1382		adm8211_set_bssid(dev, priv->bssid);
1383
1384	ADM8211_RESTORE();
1385
1386	*total_flags = new_flags;
1387}
1388
1389static int adm8211_add_interface(struct ieee80211_hw *dev,
1390				 struct ieee80211_vif *vif)
1391{
1392	struct adm8211_priv *priv = dev->priv;
1393	if (priv->mode != NL80211_IFTYPE_MONITOR)
1394		return -EOPNOTSUPP;
1395
1396	switch (vif->type) {
1397	case NL80211_IFTYPE_STATION:
1398		priv->mode = vif->type;
1399		break;
1400	default:
1401		return -EOPNOTSUPP;
1402	}
1403
1404	ADM8211_IDLE();
1405
1406	ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)vif->addr));
1407	ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(vif->addr + 4)));
1408
1409	adm8211_update_mode(dev);
1410
1411	ADM8211_RESTORE();
1412
1413	return 0;
1414}
1415
1416static void adm8211_remove_interface(struct ieee80211_hw *dev,
1417				     struct ieee80211_vif *vif)
1418{
1419	struct adm8211_priv *priv = dev->priv;
1420	priv->mode = NL80211_IFTYPE_MONITOR;
1421}
1422
1423static int adm8211_init_rings(struct ieee80211_hw *dev)
1424{
1425	struct adm8211_priv *priv = dev->priv;
1426	struct adm8211_desc *desc = NULL;
1427	struct adm8211_rx_ring_info *rx_info;
1428	struct adm8211_tx_ring_info *tx_info;
1429	unsigned int i;
1430
1431	for (i = 0; i < priv->rx_ring_size; i++) {
1432		desc = &priv->rx_ring[i];
1433		desc->status = 0;
1434		desc->length = cpu_to_le32(RX_PKT_SIZE);
1435		priv->rx_buffers[i].skb = NULL;
1436	}
1437	/* Mark the end of RX ring; hw returns to base address after this
1438	 * descriptor */
1439	desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1440
1441	for (i = 0; i < priv->rx_ring_size; i++) {
1442		desc = &priv->rx_ring[i];
1443		rx_info = &priv->rx_buffers[i];
1444
1445		rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1446		if (rx_info->skb == NULL)
1447			break;
1448		rx_info->mapping = pci_map_single(priv->pdev,
1449						  skb_tail_pointer(rx_info->skb),
1450						  RX_PKT_SIZE,
1451						  PCI_DMA_FROMDEVICE);
1452		desc->buffer1 = cpu_to_le32(rx_info->mapping);
1453		desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1454	}
1455
1456	/* Setup TX ring. TX buffers descriptors will be filled in as needed */
1457	for (i = 0; i < priv->tx_ring_size; i++) {
1458		desc = &priv->tx_ring[i];
1459		tx_info = &priv->tx_buffers[i];
1460
1461		tx_info->skb = NULL;
1462		tx_info->mapping = 0;
1463		desc->status = 0;
1464	}
1465	desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1466
1467	priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1468	ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1469	ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1470
1471	return 0;
1472}
1473
1474static void adm8211_free_rings(struct ieee80211_hw *dev)
1475{
1476	struct adm8211_priv *priv = dev->priv;
1477	unsigned int i;
1478
1479	for (i = 0; i < priv->rx_ring_size; i++) {
1480		if (!priv->rx_buffers[i].skb)
1481			continue;
1482
1483		pci_unmap_single(
1484			priv->pdev,
1485			priv->rx_buffers[i].mapping,
1486			RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1487
1488		dev_kfree_skb(priv->rx_buffers[i].skb);
1489	}
1490
1491	for (i = 0; i < priv->tx_ring_size; i++) {
1492		if (!priv->tx_buffers[i].skb)
1493			continue;
1494
1495		pci_unmap_single(priv->pdev,
1496				 priv->tx_buffers[i].mapping,
1497				 priv->tx_buffers[i].skb->len,
1498				 PCI_DMA_TODEVICE);
1499
1500		dev_kfree_skb(priv->tx_buffers[i].skb);
1501	}
1502}
1503
1504static int adm8211_start(struct ieee80211_hw *dev)
1505{
1506	struct adm8211_priv *priv = dev->priv;
1507	int retval;
1508
1509	/* Power up MAC and RF chips */
1510	retval = adm8211_hw_reset(dev);
1511	if (retval) {
1512		wiphy_err(dev->wiphy, "hardware reset failed\n");
1513		goto fail;
1514	}
1515
1516	retval = adm8211_init_rings(dev);
1517	if (retval) {
1518		wiphy_err(dev->wiphy, "failed to initialize rings\n");
1519		goto fail;
1520	}
1521
1522	/* Init hardware */
1523	adm8211_hw_init(dev);
1524	adm8211_rf_set_channel(dev, priv->channel);
1525
1526	retval = request_irq(priv->pdev->irq, adm8211_interrupt,
1527			     IRQF_SHARED, "adm8211", dev);
1528	if (retval) {
1529		wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
1530		goto fail;
1531	}
1532
1533	ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1534			       ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1535			       ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1536	priv->mode = NL80211_IFTYPE_MONITOR;
1537	adm8211_update_mode(dev);
1538	ADM8211_CSR_WRITE(RDR, 0);
1539
1540	adm8211_set_interval(dev, 100, 10);
1541	return 0;
1542
1543fail:
1544	return retval;
1545}
1546
1547static void adm8211_stop(struct ieee80211_hw *dev)
1548{
1549	struct adm8211_priv *priv = dev->priv;
1550
1551	priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1552	priv->nar = 0;
1553	ADM8211_CSR_WRITE(NAR, 0);
1554	ADM8211_CSR_WRITE(IER, 0);
1555	ADM8211_CSR_READ(NAR);
1556
1557	free_irq(priv->pdev->irq, dev);
1558
1559	adm8211_free_rings(dev);
1560}
1561
1562static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1563				   int plcp_signal, int short_preamble)
1564{
1565	/* Alternative calculation from NetBSD: */
1566
1567/* IEEE 802.11b durations for DSSS PHY in microseconds */
1568#define IEEE80211_DUR_DS_LONG_PREAMBLE	144
1569#define IEEE80211_DUR_DS_SHORT_PREAMBLE	72
1570#define IEEE80211_DUR_DS_FAST_PLCPHDR	24
1571#define IEEE80211_DUR_DS_SLOW_PLCPHDR	48
1572#define IEEE80211_DUR_DS_SLOW_ACK	112
1573#define IEEE80211_DUR_DS_FAST_ACK	56
1574#define IEEE80211_DUR_DS_SLOW_CTS	112
1575#define IEEE80211_DUR_DS_FAST_CTS	56
1576#define IEEE80211_DUR_DS_SLOT		20
1577#define IEEE80211_DUR_DS_SIFS		10
1578
1579	int remainder;
1580
1581	*dur = (80 * (24 + payload_len) + plcp_signal - 1)
1582		/ plcp_signal;
1583
1584	if (plcp_signal <= PLCP_SIGNAL_2M)
1585		/* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1586		*dur += 3 * (IEEE80211_DUR_DS_SIFS +
1587			     IEEE80211_DUR_DS_SHORT_PREAMBLE +
1588			     IEEE80211_DUR_DS_FAST_PLCPHDR) +
1589			     IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1590	else
1591		/* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1592		*dur += 3 * (IEEE80211_DUR_DS_SIFS +
1593			     IEEE80211_DUR_DS_SHORT_PREAMBLE +
1594			     IEEE80211_DUR_DS_FAST_PLCPHDR) +
1595			     IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1596
1597	/* lengthen duration if long preamble */
1598	if (!short_preamble)
1599		*dur +=	3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1600			     IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1601			3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1602			     IEEE80211_DUR_DS_FAST_PLCPHDR);
1603
1604
1605	*plcp = (80 * len) / plcp_signal;
1606	remainder = (80 * len) % plcp_signal;
1607	if (plcp_signal == PLCP_SIGNAL_11M &&
1608	    remainder <= 30 && remainder > 0)
1609		*plcp = (*plcp | 0x8000) + 1;
1610	else if (remainder)
1611		(*plcp)++;
1612}
1613
1614/* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1615static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1616			   u16 plcp_signal,
1617			   size_t hdrlen)
1618{
1619	struct adm8211_priv *priv = dev->priv;
1620	unsigned long flags;
1621	dma_addr_t mapping;
1622	unsigned int entry;
1623	u32 flag;
1624
1625	mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1626				 PCI_DMA_TODEVICE);
1627
1628	spin_lock_irqsave(&priv->lock, flags);
1629
1630	if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1631		flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1632	else
1633		flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1634
1635	if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1636		ieee80211_stop_queue(dev, 0);
1637
1638	entry = priv->cur_tx % priv->tx_ring_size;
1639
1640	priv->tx_buffers[entry].skb = skb;
1641	priv->tx_buffers[entry].mapping = mapping;
1642	priv->tx_buffers[entry].hdrlen = hdrlen;
1643	priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1644
1645	if (entry == priv->tx_ring_size - 1)
1646		flag |= TDES1_CONTROL_TER;
1647	priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1648
1649	/* Set TX rate (SIGNAL field in PLCP PPDU format) */
1650	flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1651	priv->tx_ring[entry].status = cpu_to_le32(flag);
1652
1653	priv->cur_tx++;
1654
1655	spin_unlock_irqrestore(&priv->lock, flags);
1656
1657	/* Trigger transmit poll */
1658	ADM8211_CSR_WRITE(TDR, 0);
1659}
1660
1661/* Put adm8211_tx_hdr on skb and transmit */
1662static void adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
1663{
1664	struct adm8211_tx_hdr *txhdr;
1665	size_t payload_len, hdrlen;
1666	int plcp, dur, len, plcp_signal, short_preamble;
1667	struct ieee80211_hdr *hdr;
1668	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1669	struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
1670	u8 rc_flags;
1671
1672	rc_flags = info->control.rates[0].flags;
1673	short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1674	plcp_signal = txrate->bitrate;
1675
1676	hdr = (struct ieee80211_hdr *)skb->data;
1677	hdrlen = ieee80211_hdrlen(hdr->frame_control);
1678	memcpy(skb->cb, skb->data, hdrlen);
1679	hdr = (struct ieee80211_hdr *)skb->cb;
1680	skb_pull(skb, hdrlen);
1681	payload_len = skb->len;
1682
1683	txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1684	memset(txhdr, 0, sizeof(*txhdr));
1685	memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1686	txhdr->signal = plcp_signal;
1687	txhdr->frame_body_size = cpu_to_le16(payload_len);
1688	txhdr->frame_control = hdr->frame_control;
1689
1690	len = hdrlen + payload_len + FCS_LEN;
1691
1692	txhdr->frag = cpu_to_le16(0x0FFF);
1693	adm8211_calc_durations(&dur, &plcp, payload_len,
1694			       len, plcp_signal, short_preamble);
1695	txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1696	txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1697	txhdr->dur_frag_head = cpu_to_le16(dur);
1698	txhdr->dur_frag_tail = cpu_to_le16(dur);
1699
1700	txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1701
1702	if (short_preamble)
1703		txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1704
1705	if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1706		txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1707
1708	txhdr->retry_limit = info->control.rates[0].count;
1709
1710	adm8211_tx_raw(dev, skb, plcp_signal, hdrlen);
1711}
1712
1713static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1714{
1715	struct adm8211_priv *priv = dev->priv;
1716	unsigned int ring_size;
1717
1718	priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1719				   sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1720	if (!priv->rx_buffers)
1721		return -ENOMEM;
1722
1723	priv->tx_buffers = (void *)priv->rx_buffers +
1724			   sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1725
1726	/* Allocate TX/RX descriptors */
1727	ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1728		    sizeof(struct adm8211_desc) * priv->tx_ring_size;
1729	priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1730					     &priv->rx_ring_dma);
1731
1732	if (!priv->rx_ring) {
1733		kfree(priv->rx_buffers);
1734		priv->rx_buffers = NULL;
1735		priv->tx_buffers = NULL;
1736		return -ENOMEM;
1737	}
1738
1739	priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1740						priv->rx_ring_size);
1741	priv->tx_ring_dma = priv->rx_ring_dma +
1742			    sizeof(struct adm8211_desc) * priv->rx_ring_size;
1743
1744	return 0;
1745}
1746
1747static const struct ieee80211_ops adm8211_ops = {
1748	.tx			= adm8211_tx,
1749	.start			= adm8211_start,
1750	.stop			= adm8211_stop,
1751	.add_interface		= adm8211_add_interface,
1752	.remove_interface	= adm8211_remove_interface,
1753	.config			= adm8211_config,
1754	.bss_info_changed	= adm8211_bss_info_changed,
1755	.prepare_multicast	= adm8211_prepare_multicast,
1756	.configure_filter	= adm8211_configure_filter,
1757	.get_stats		= adm8211_get_stats,
1758	.get_tsf		= adm8211_get_tsft
1759};
1760
1761static int __devinit adm8211_probe(struct pci_dev *pdev,
1762				   const struct pci_device_id *id)
1763{
1764	struct ieee80211_hw *dev;
1765	struct adm8211_priv *priv;
1766	unsigned long mem_addr, mem_len;
1767	unsigned int io_addr, io_len;
1768	int err;
1769	u32 reg;
1770	u8 perm_addr[ETH_ALEN];
1771
1772	err = pci_enable_device(pdev);
1773	if (err) {
1774		printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1775		       pci_name(pdev));
1776		return err;
1777	}
1778
1779	io_addr = pci_resource_start(pdev, 0);
1780	io

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