/drivers/net/wireless/rtlwifi/rtl8192ce/def.h
C Header | 374 lines | 308 code | 35 blank | 31 comment | 6 complexity | 70ea811f811ca300c348f2cba2fe0ca2 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#ifndef __RTL92C_DEF_H__ 31#define __RTL92C_DEF_H__ 32 33#define HAL_RETRY_LIMIT_INFRA 48 34#define HAL_RETRY_LIMIT_AP_ADHOC 7 35 36#define PHY_RSSI_SLID_WIN_MAX 100 37#define PHY_LINKQUALITY_SLID_WIN_MAX 20 38#define PHY_BEACON_RSSI_SLID_WIN_MAX 10 39 40#define RESET_DELAY_8185 20 41 42#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER) 43#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK) 44 45#define NUM_OF_FIRMWARE_QUEUE 10 46#define NUM_OF_PAGES_IN_FW 0x100 47#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07 48#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07 49#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07 50#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07 51#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0 52#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0 53#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02 54#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02 55#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2 56#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1 57 58#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026 59#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048 60#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048 61#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026 62#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00 63 64#define MAX_LINES_HWCONFIG_TXT 1000 65#define MAX_BYTES_LINE_HWCONFIG_TXT 256 66 67#define SW_THREE_WIRE 0 68#define HW_THREE_WIRE 2 69 70#define BT_DEMO_BOARD 0 71#define BT_QA_BOARD 1 72#define BT_FPGA 2 73 74#define RX_SMOOTH_FACTOR 20 75 76#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 77#define HAL_PRIME_CHNL_OFFSET_LOWER 1 78#define HAL_PRIME_CHNL_OFFSET_UPPER 2 79 80#define MAX_H2C_QUEUE_NUM 10 81 82#define RX_MPDU_QUEUE 0 83#define RX_CMD_QUEUE 1 84#define RX_MAX_QUEUE 2 85#define AC2QUEUEID(_AC) (_AC) 86 87#define C2H_RX_CMD_HDR_LEN 8 88#define GET_C2H_CMD_CMD_LEN(__prxhdr) \ 89 LE_BITS_TO_4BYTE((__prxhdr), 0, 16) 90#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \ 91 LE_BITS_TO_4BYTE((__prxhdr), 16, 8) 92#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \ 93 LE_BITS_TO_4BYTE((__prxhdr), 24, 7) 94#define GET_C2H_CMD_CONTINUE(__prxhdr) \ 95 LE_BITS_TO_4BYTE((__prxhdr), 31, 1) 96#define GET_C2H_CMD_CONTENT(__prxhdr) \ 97 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN) 98 99#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \ 100 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8) 101#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \ 102 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8) 103#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \ 104 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16) 105#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \ 106 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5) 107#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \ 108 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1) 109#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \ 110 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5) 111#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \ 112 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1) 113#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \ 114 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4) 115#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \ 116 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12) 117 118#define CHIP_VER_B BIT(4) 119#define CHIP_92C_BITMASK BIT(0) 120#define CHIP_92C_1T2R 0x03 121#define CHIP_92C 0x01 122#define CHIP_88C 0x00 123 124enum version_8192c { 125 VERSION_A_CHIP_92C = 0x01, 126 VERSION_A_CHIP_88C = 0x00, 127 VERSION_B_CHIP_92C = 0x11, 128 VERSION_B_CHIP_88C = 0x10, 129 VERSION_TEST_CHIP_88C = 0x00, 130 VERSION_TEST_CHIP_92C = 0x01, 131 VERSION_NORMAL_TSMC_CHIP_88C = 0x10, 132 VERSION_NORMAL_TSMC_CHIP_92C = 0x11, 133 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13, 134 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30, 135 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31, 136 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33, 137 VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34, 138 VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c, 139 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70, 140 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71, 141 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73, 142 VERSION_UNKNOWN = 0x88, 143}; 144 145#define IS_CHIP_VER_B(version) ((version & CHIP_VER_B) ? true : false) 146#define IS_92C_SERIAL(version) ((version & CHIP_92C_BITMASK) ? true : false) 147 148enum rtl819x_loopback_e { 149 RTL819X_NO_LOOPBACK = 0, 150 RTL819X_MAC_LOOPBACK = 1, 151 RTL819X_DMA_LOOPBACK = 2, 152 RTL819X_CCK_LOOPBACK = 3, 153}; 154 155enum rf_optype { 156 RF_OP_BY_SW_3WIRE = 0, 157 RF_OP_BY_FW, 158 RF_OP_MAX 159}; 160 161enum rf_power_state { 162 RF_ON, 163 RF_OFF, 164 RF_SLEEP, 165 RF_SHUT_DOWN, 166}; 167 168enum power_save_mode { 169 POWER_SAVE_MODE_ACTIVE, 170 POWER_SAVE_MODE_SAVE, 171}; 172 173enum power_polocy_config { 174 POWERCFG_MAX_POWER_SAVINGS, 175 POWERCFG_GLOBAL_POWER_SAVINGS, 176 POWERCFG_LOCAL_POWER_SAVINGS, 177 POWERCFG_LENOVO, 178}; 179 180enum interface_select_pci { 181 INTF_SEL1_MINICARD = 0, 182 INTF_SEL0_PCIE = 1, 183 INTF_SEL2_RSV = 2, 184 INTF_SEL3_RSV = 3, 185}; 186 187enum hal_fw_c2h_cmd_id { 188 HAL_FW_C2H_CMD_Read_MACREG = 0, 189 HAL_FW_C2H_CMD_Read_BBREG = 1, 190 HAL_FW_C2H_CMD_Read_RFREG = 2, 191 HAL_FW_C2H_CMD_Read_EEPROM = 3, 192 HAL_FW_C2H_CMD_Read_EFUSE = 4, 193 HAL_FW_C2H_CMD_Read_CAM = 5, 194 HAL_FW_C2H_CMD_Get_BasicRate = 6, 195 HAL_FW_C2H_CMD_Get_DataRate = 7, 196 HAL_FW_C2H_CMD_Survey = 8, 197 HAL_FW_C2H_CMD_SurveyDone = 9, 198 HAL_FW_C2H_CMD_JoinBss = 10, 199 HAL_FW_C2H_CMD_AddSTA = 11, 200 HAL_FW_C2H_CMD_DelSTA = 12, 201 HAL_FW_C2H_CMD_AtimDone = 13, 202 HAL_FW_C2H_CMD_TX_Report = 14, 203 HAL_FW_C2H_CMD_CCX_Report = 15, 204 HAL_FW_C2H_CMD_DTM_Report = 16, 205 HAL_FW_C2H_CMD_TX_Rate_Statistics = 17, 206 HAL_FW_C2H_CMD_C2HLBK = 18, 207 HAL_FW_C2H_CMD_C2HDBG = 19, 208 HAL_FW_C2H_CMD_C2HFEEDBACK = 20, 209 HAL_FW_C2H_CMD_MAX 210}; 211 212enum rtl_desc_qsel { 213 QSLT_BK = 0x2, 214 QSLT_BE = 0x0, 215 QSLT_VI = 0x5, 216 QSLT_VO = 0x7, 217 QSLT_BEACON = 0x10, 218 QSLT_HIGH = 0x11, 219 QSLT_MGNT = 0x12, 220 QSLT_CMD = 0x13, 221}; 222 223enum rtl_desc92c_rate { 224 DESC92C_RATE1M = 0x00, 225 DESC92C_RATE2M = 0x01, 226 DESC92C_RATE5_5M = 0x02, 227 DESC92C_RATE11M = 0x03, 228 229 DESC92C_RATE6M = 0x04, 230 DESC92C_RATE9M = 0x05, 231 DESC92C_RATE12M = 0x06, 232 DESC92C_RATE18M = 0x07, 233 DESC92C_RATE24M = 0x08, 234 DESC92C_RATE36M = 0x09, 235 DESC92C_RATE48M = 0x0a, 236 DESC92C_RATE54M = 0x0b, 237 238 DESC92C_RATEMCS0 = 0x0c, 239 DESC92C_RATEMCS1 = 0x0d, 240 DESC92C_RATEMCS2 = 0x0e, 241 DESC92C_RATEMCS3 = 0x0f, 242 DESC92C_RATEMCS4 = 0x10, 243 DESC92C_RATEMCS5 = 0x11, 244 DESC92C_RATEMCS6 = 0x12, 245 DESC92C_RATEMCS7 = 0x13, 246 DESC92C_RATEMCS8 = 0x14, 247 DESC92C_RATEMCS9 = 0x15, 248 DESC92C_RATEMCS10 = 0x16, 249 DESC92C_RATEMCS11 = 0x17, 250 DESC92C_RATEMCS12 = 0x18, 251 DESC92C_RATEMCS13 = 0x19, 252 DESC92C_RATEMCS14 = 0x1a, 253 DESC92C_RATEMCS15 = 0x1b, 254 DESC92C_RATEMCS15_SG = 0x1c, 255 DESC92C_RATEMCS32 = 0x20, 256}; 257 258struct phy_sts_cck_8192s_t { 259 u8 adc_pwdb_X[4]; 260 u8 sq_rpt; 261 u8 cck_agc_rpt; 262}; 263 264struct h2c_cmd_8192c { 265 u8 element_id; 266 u32 cmd_len; 267 u8 *p_cmdbuffer; 268}; 269 270/* NOTE: reference to rtl8192c_rates struct */ 271static inline int _rtl92c_rate_mapping(struct ieee80211_hw *hw, bool isHT, 272 u8 desc_rate, bool first_ampdu) 273{ 274 struct rtl_priv *rtlpriv = rtl_priv(hw); 275 int rate_idx = 0; 276 277 if (first_ampdu) { 278 if (false == isHT) { 279 switch (desc_rate) { 280 case DESC92C_RATE1M: 281 rate_idx = 0; 282 break; 283 case DESC92C_RATE2M: 284 rate_idx = 1; 285 break; 286 case DESC92C_RATE5_5M: 287 rate_idx = 2; 288 break; 289 case DESC92C_RATE11M: 290 rate_idx = 3; 291 break; 292 case DESC92C_RATE6M: 293 rate_idx = 4; 294 break; 295 case DESC92C_RATE9M: 296 rate_idx = 5; 297 break; 298 case DESC92C_RATE12M: 299 rate_idx = 6; 300 break; 301 case DESC92C_RATE18M: 302 rate_idx = 7; 303 break; 304 case DESC92C_RATE24M: 305 rate_idx = 8; 306 break; 307 case DESC92C_RATE36M: 308 rate_idx = 9; 309 break; 310 case DESC92C_RATE48M: 311 rate_idx = 10; 312 break; 313 case DESC92C_RATE54M: 314 rate_idx = 11; 315 break; 316 default: 317 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 318 ("Rate %d is not support, set to " 319 "1M rate.\n", desc_rate)); 320 rate_idx = 0; 321 break; 322 } 323 } else { 324 rate_idx = 11; 325 } 326 return rate_idx; 327 } 328 switch (desc_rate) { 329 case DESC92C_RATE1M: 330 rate_idx = 0; 331 break; 332 case DESC92C_RATE2M: 333 rate_idx = 1; 334 break; 335 case DESC92C_RATE5_5M: 336 rate_idx = 2; 337 break; 338 case DESC92C_RATE11M: 339 rate_idx = 3; 340 break; 341 case DESC92C_RATE6M: 342 rate_idx = 4; 343 break; 344 case DESC92C_RATE9M: 345 rate_idx = 5; 346 break; 347 case DESC92C_RATE12M: 348 rate_idx = 6; 349 break; 350 case DESC92C_RATE18M: 351 rate_idx = 7; 352 break; 353 case DESC92C_RATE24M: 354 rate_idx = 8; 355 break; 356 case DESC92C_RATE36M: 357 rate_idx = 9; 358 break; 359 case DESC92C_RATE48M: 360 rate_idx = 10; 361 break; 362 case DESC92C_RATE54M: 363 rate_idx = 11; 364 break; 365 /* TODO: How to mapping MCS rate? */ 366 /* NOTE: referenc to __ieee80211_rx */ 367 default: 368 rate_idx = 11; 369 break; 370 } 371 return rate_idx; 372} 373 374#endif