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/drivers/net/wireless/iwlwifi/iwl-eeprom.c

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C | 856 lines | 559 code | 96 blank | 201 comment | 66 complexity | 8ef8c925eb2923115c06a8c769ad4b0b MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1/******************************************************************************
  2 *
  3 * This file is provided under a dual BSD/GPLv2 license.  When using or
  4 * redistributing this file, you may do so under either license.
  5 *
  6 * GPL LICENSE SUMMARY
  7 *
  8 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  9 *
 10 * This program is free software; you can redistribute it and/or modify
 11 * it under the terms of version 2 of the GNU General Public License as
 12 * published by the Free Software Foundation.
 13 *
 14 * This program is distributed in the hope that it will be useful, but
 15 * WITHOUT ANY WARRANTY; without even the implied warranty of
 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 17 * General Public License for more details.
 18 *
 19 * You should have received a copy of the GNU General Public License
 20 * along with this program; if not, write to the Free Software
 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 22 * USA
 23 *
 24 * The full GNU General Public License is included in this distribution
 25 * in the file called LICENSE.GPL.
 26 *
 27 * Contact Information:
 28 *  Intel Linux Wireless <ilw@linux.intel.com>
 29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 30 *
 31 * BSD LICENSE
 32 *
 33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
 34 * All rights reserved.
 35 *
 36 * Redistribution and use in source and binary forms, with or without
 37 * modification, are permitted provided that the following conditions
 38 * are met:
 39 *
 40 *  * Redistributions of source code must retain the above copyright
 41 *    notice, this list of conditions and the following disclaimer.
 42 *  * Redistributions in binary form must reproduce the above copyright
 43 *    notice, this list of conditions and the following disclaimer in
 44 *    the documentation and/or other materials provided with the
 45 *    distribution.
 46 *  * Neither the name Intel Corporation nor the names of its
 47 *    contributors may be used to endorse or promote products derived
 48 *    from this software without specific prior written permission.
 49 *
 50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 61 *****************************************************************************/
 62
 63
 64#include <linux/kernel.h>
 65#include <linux/module.h>
 66#include <linux/slab.h>
 67#include <linux/init.h>
 68
 69#include <net/mac80211.h>
 70
 71#include "iwl-commands.h"
 72#include "iwl-dev.h"
 73#include "iwl-core.h"
 74#include "iwl-debug.h"
 75#include "iwl-eeprom.h"
 76#include "iwl-io.h"
 77
 78/************************** EEPROM BANDS ****************************
 79 *
 80 * The iwl_eeprom_band definitions below provide the mapping from the
 81 * EEPROM contents to the specific channel number supported for each
 82 * band.
 83 *
 84 * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
 85 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
 86 * The specific geography and calibration information for that channel
 87 * is contained in the eeprom map itself.
 88 *
 89 * During init, we copy the eeprom information and channel map
 90 * information into priv->channel_info_24/52 and priv->channel_map_24/52
 91 *
 92 * channel_map_24/52 provides the index in the channel_info array for a
 93 * given channel.  We have to have two separate maps as there is channel
 94 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
 95 * band_2
 96 *
 97 * A value of 0xff stored in the channel_map indicates that the channel
 98 * is not supported by the hardware at all.
 99 *
100 * A value of 0xfe in the channel_map indicates that the channel is not
101 * valid for Tx with the current hardware.  This means that
102 * while the system can tune and receive on a given channel, it may not
103 * be able to associate or transmit any frames on that
104 * channel.  There is no corresponding channel information for that
105 * entry.
106 *
107 *********************************************************************/
108
109/* 2.4 GHz */
110const u8 iwl_eeprom_band_1[14] = {
111	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
112};
113
114/* 5.2 GHz bands */
115static const u8 iwl_eeprom_band_2[] = {	/* 4915-5080MHz */
116	183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
117};
118
119static const u8 iwl_eeprom_band_3[] = {	/* 5170-5320MHz */
120	34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
121};
122
123static const u8 iwl_eeprom_band_4[] = {	/* 5500-5700MHz */
124	100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
125};
126
127static const u8 iwl_eeprom_band_5[] = {	/* 5725-5825MHz */
128	145, 149, 153, 157, 161, 165
129};
130
131static const u8 iwl_eeprom_band_6[] = {       /* 2.4 ht40 channel */
132	1, 2, 3, 4, 5, 6, 7
133};
134
135static const u8 iwl_eeprom_band_7[] = {       /* 5.2 ht40 channel */
136	36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
137};
138
139/******************************************************************************
140 *
141 * EEPROM related functions
142 *
143******************************************************************************/
144
145/*
146 * The device's EEPROM semaphore prevents conflicts between driver and uCode
147 * when accessing the EEPROM; each access is a series of pulses to/from the
148 * EEPROM chip, not a single event, so even reads could conflict if they
149 * weren't arbitrated by the semaphore.
150 */
151static int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv)
152{
153	u16 count;
154	int ret;
155
156	for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
157		/* Request semaphore */
158		iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
159			    CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
160
161		/* See if we got it */
162		ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
163				CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
164				CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
165				EEPROM_SEM_TIMEOUT);
166		if (ret >= 0) {
167			IWL_DEBUG_EEPROM(priv,
168				"Acquired semaphore after %d tries.\n",
169				count+1);
170			return ret;
171		}
172	}
173
174	return ret;
175}
176
177static void iwl_eeprom_release_semaphore(struct iwl_priv *priv)
178{
179	iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
180		CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
181
182}
183
184static int iwl_eeprom_verify_signature(struct iwl_priv *priv)
185{
186	u32 gp = iwl_read32(priv, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
187	int ret = 0;
188
189	IWL_DEBUG_EEPROM(priv, "EEPROM signature=0x%08x\n", gp);
190	switch (gp) {
191	case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
192		if (priv->nvm_device_type != NVM_DEVICE_TYPE_OTP) {
193			IWL_ERR(priv, "EEPROM with bad signature: 0x%08x\n",
194				gp);
195			ret = -ENOENT;
196		}
197		break;
198	case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
199	case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
200		if (priv->nvm_device_type != NVM_DEVICE_TYPE_EEPROM) {
201			IWL_ERR(priv, "OTP with bad signature: 0x%08x\n", gp);
202			ret = -ENOENT;
203		}
204		break;
205	case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
206	default:
207		IWL_ERR(priv, "bad EEPROM/OTP signature, type=%s, "
208			"EEPROM_GP=0x%08x\n",
209			(priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
210			? "OTP" : "EEPROM", gp);
211		ret = -ENOENT;
212		break;
213	}
214	return ret;
215}
216
217static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode)
218{
219	iwl_read32(priv, CSR_OTP_GP_REG);
220
221	if (mode == IWL_OTP_ACCESS_ABSOLUTE)
222		iwl_clear_bit(priv, CSR_OTP_GP_REG,
223			      CSR_OTP_GP_REG_OTP_ACCESS_MODE);
224	else
225		iwl_set_bit(priv, CSR_OTP_GP_REG,
226			    CSR_OTP_GP_REG_OTP_ACCESS_MODE);
227}
228
229static int iwlcore_get_nvm_type(struct iwl_priv *priv, u32 hw_rev)
230{
231	u32 otpgp;
232	int nvm_type;
233
234	/* OTP only valid for CP/PP and after */
235	switch (hw_rev & CSR_HW_REV_TYPE_MSK) {
236	case CSR_HW_REV_TYPE_NONE:
237		IWL_ERR(priv, "Unknown hardware type\n");
238		return -ENOENT;
239	case CSR_HW_REV_TYPE_5300:
240	case CSR_HW_REV_TYPE_5350:
241	case CSR_HW_REV_TYPE_5100:
242	case CSR_HW_REV_TYPE_5150:
243		nvm_type = NVM_DEVICE_TYPE_EEPROM;
244		break;
245	default:
246		otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
247		if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
248			nvm_type = NVM_DEVICE_TYPE_OTP;
249		else
250			nvm_type = NVM_DEVICE_TYPE_EEPROM;
251		break;
252	}
253	return  nvm_type;
254}
255
256static int iwl_init_otp_access(struct iwl_priv *priv)
257{
258	int ret;
259
260	/* Enable 40MHz radio clock */
261	iwl_write32(priv, CSR_GP_CNTRL,
262		    iwl_read32(priv, CSR_GP_CNTRL) |
263		    CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
264
265	/* wait for clock to be ready */
266	ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
267				 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
268				 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
269				 25000);
270	if (ret < 0)
271		IWL_ERR(priv, "Time out access OTP\n");
272	else {
273		iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
274				  APMG_PS_CTRL_VAL_RESET_REQ);
275		udelay(5);
276		iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
277				    APMG_PS_CTRL_VAL_RESET_REQ);
278
279		/*
280		 * CSR auto clock gate disable bit -
281		 * this is only applicable for HW with OTP shadow RAM
282		 */
283		if (priv->cfg->base_params->shadow_ram_support)
284			iwl_set_bit(priv, CSR_DBG_LINK_PWR_MGMT_REG,
285				CSR_RESET_LINK_PWR_MGMT_DISABLED);
286	}
287	return ret;
288}
289
290static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_data)
291{
292	int ret = 0;
293	u32 r;
294	u32 otpgp;
295
296	iwl_write32(priv, CSR_EEPROM_REG,
297		    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
298	ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
299				 CSR_EEPROM_REG_READ_VALID_MSK,
300				 CSR_EEPROM_REG_READ_VALID_MSK,
301				 IWL_EEPROM_ACCESS_TIMEOUT);
302	if (ret < 0) {
303		IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
304		return ret;
305	}
306	r = iwl_read32(priv, CSR_EEPROM_REG);
307	/* check for ECC errors: */
308	otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
309	if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
310		/* stop in this case */
311		/* set the uncorrectable OTP ECC bit for acknowledgement */
312		iwl_set_bit(priv, CSR_OTP_GP_REG,
313			CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
314		IWL_ERR(priv, "Uncorrectable OTP ECC error, abort OTP read\n");
315		return -EINVAL;
316	}
317	if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
318		/* continue in this case */
319		/* set the correctable OTP ECC bit for acknowledgement */
320		iwl_set_bit(priv, CSR_OTP_GP_REG,
321				CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
322		IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
323	}
324	*eeprom_data = cpu_to_le16(r >> 16);
325	return 0;
326}
327
328/*
329 * iwl_is_otp_empty: check for empty OTP
330 */
331static bool iwl_is_otp_empty(struct iwl_priv *priv)
332{
333	u16 next_link_addr = 0;
334	__le16 link_value;
335	bool is_empty = false;
336
337	/* locate the beginning of OTP link list */
338	if (!iwl_read_otp_word(priv, next_link_addr, &link_value)) {
339		if (!link_value) {
340			IWL_ERR(priv, "OTP is empty\n");
341			is_empty = true;
342		}
343	} else {
344		IWL_ERR(priv, "Unable to read first block of OTP list.\n");
345		is_empty = true;
346	}
347
348	return is_empty;
349}
350
351
352/*
353 * iwl_find_otp_image: find EEPROM image in OTP
354 *   finding the OTP block that contains the EEPROM image.
355 *   the last valid block on the link list (the block _before_ the last block)
356 *   is the block we should read and used to configure the device.
357 *   If all the available OTP blocks are full, the last block will be the block
358 *   we should read and used to configure the device.
359 *   only perform this operation if shadow RAM is disabled
360 */
361static int iwl_find_otp_image(struct iwl_priv *priv,
362					u16 *validblockaddr)
363{
364	u16 next_link_addr = 0, valid_addr;
365	__le16 link_value = 0;
366	int usedblocks = 0;
367
368	/* set addressing mode to absolute to traverse the link list */
369	iwl_set_otp_access(priv, IWL_OTP_ACCESS_ABSOLUTE);
370
371	/* checking for empty OTP or error */
372	if (iwl_is_otp_empty(priv))
373		return -EINVAL;
374
375	/*
376	 * start traverse link list
377	 * until reach the max number of OTP blocks
378	 * different devices have different number of OTP blocks
379	 */
380	do {
381		/* save current valid block address
382		 * check for more block on the link list
383		 */
384		valid_addr = next_link_addr;
385		next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
386		IWL_DEBUG_EEPROM(priv, "OTP blocks %d addr 0x%x\n",
387			       usedblocks, next_link_addr);
388		if (iwl_read_otp_word(priv, next_link_addr, &link_value))
389			return -EINVAL;
390		if (!link_value) {
391			/*
392			 * reach the end of link list, return success and
393			 * set address point to the starting address
394			 * of the image
395			 */
396			*validblockaddr = valid_addr;
397			/* skip first 2 bytes (link list pointer) */
398			*validblockaddr += 2;
399			return 0;
400		}
401		/* more in the link list, continue */
402		usedblocks++;
403	} while (usedblocks <= priv->cfg->base_params->max_ll_items);
404
405	/* OTP has no valid blocks */
406	IWL_DEBUG_EEPROM(priv, "OTP has no valid blocks\n");
407	return -EINVAL;
408}
409
410u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
411{
412	if (!priv->eeprom)
413		return 0;
414	return (u16)priv->eeprom[offset] | ((u16)priv->eeprom[offset + 1] << 8);
415}
416
417/**
418 * iwl_eeprom_init - read EEPROM contents
419 *
420 * Load the EEPROM contents from adapter into priv->eeprom
421 *
422 * NOTE:  This routine uses the non-debug IO access functions.
423 */
424int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
425{
426	__le16 *e;
427	u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
428	int sz;
429	int ret;
430	u16 addr;
431	u16 validblockaddr = 0;
432	u16 cache_addr = 0;
433
434	priv->nvm_device_type = iwlcore_get_nvm_type(priv, hw_rev);
435	if (priv->nvm_device_type == -ENOENT)
436		return -ENOENT;
437	/* allocate eeprom */
438	sz = priv->cfg->base_params->eeprom_size;
439	IWL_DEBUG_EEPROM(priv, "NVM size = %d\n", sz);
440	priv->eeprom = kzalloc(sz, GFP_KERNEL);
441	if (!priv->eeprom) {
442		ret = -ENOMEM;
443		goto alloc_err;
444	}
445	e = (__le16 *)priv->eeprom;
446
447	iwl_apm_init(priv);
448
449	ret = iwl_eeprom_verify_signature(priv);
450	if (ret < 0) {
451		IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
452		ret = -ENOENT;
453		goto err;
454	}
455
456	/* Make sure driver (instead of uCode) is allowed to read EEPROM */
457	ret = iwl_eeprom_acquire_semaphore(priv);
458	if (ret < 0) {
459		IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
460		ret = -ENOENT;
461		goto err;
462	}
463
464	if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
465
466		ret = iwl_init_otp_access(priv);
467		if (ret) {
468			IWL_ERR(priv, "Failed to initialize OTP access.\n");
469			ret = -ENOENT;
470			goto done;
471		}
472		iwl_write32(priv, CSR_EEPROM_GP,
473			    iwl_read32(priv, CSR_EEPROM_GP) &
474			    ~CSR_EEPROM_GP_IF_OWNER_MSK);
475
476		iwl_set_bit(priv, CSR_OTP_GP_REG,
477			     CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
478			     CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
479		/* traversing the linked list if no shadow ram supported */
480		if (!priv->cfg->base_params->shadow_ram_support) {
481			if (iwl_find_otp_image(priv, &validblockaddr)) {
482				ret = -ENOENT;
483				goto done;
484			}
485		}
486		for (addr = validblockaddr; addr < validblockaddr + sz;
487		     addr += sizeof(u16)) {
488			__le16 eeprom_data;
489
490			ret = iwl_read_otp_word(priv, addr, &eeprom_data);
491			if (ret)
492				goto done;
493			e[cache_addr / 2] = eeprom_data;
494			cache_addr += sizeof(u16);
495		}
496	} else {
497		/* eeprom is an array of 16bit values */
498		for (addr = 0; addr < sz; addr += sizeof(u16)) {
499			u32 r;
500
501			iwl_write32(priv, CSR_EEPROM_REG,
502				    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
503
504			ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
505						  CSR_EEPROM_REG_READ_VALID_MSK,
506						  CSR_EEPROM_REG_READ_VALID_MSK,
507						  IWL_EEPROM_ACCESS_TIMEOUT);
508			if (ret < 0) {
509				IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
510				goto done;
511			}
512			r = iwl_read32(priv, CSR_EEPROM_REG);
513			e[addr / 2] = cpu_to_le16(r >> 16);
514		}
515	}
516
517	IWL_DEBUG_EEPROM(priv, "NVM Type: %s, version: 0x%x\n",
518		       (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
519		       ? "OTP" : "EEPROM",
520		       iwl_eeprom_query16(priv, EEPROM_VERSION));
521
522	ret = 0;
523done:
524	iwl_eeprom_release_semaphore(priv);
525
526err:
527	if (ret)
528		iwl_eeprom_free(priv);
529	/* Reset chip to save power until we load uCode during "up". */
530	iwl_apm_stop(priv);
531alloc_err:
532	return ret;
533}
534
535void iwl_eeprom_free(struct iwl_priv *priv)
536{
537	kfree(priv->eeprom);
538	priv->eeprom = NULL;
539}
540
541static void iwl_init_band_reference(const struct iwl_priv *priv,
542			int eep_band, int *eeprom_ch_count,
543			const struct iwl_eeprom_channel **eeprom_ch_info,
544			const u8 **eeprom_ch_index)
545{
546	u32 offset = priv->cfg->lib->
547			eeprom_ops.regulatory_bands[eep_band - 1];
548	switch (eep_band) {
549	case 1:		/* 2.4GHz band */
550		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
551		*eeprom_ch_info = (struct iwl_eeprom_channel *)
552				iwl_eeprom_query_addr(priv, offset);
553		*eeprom_ch_index = iwl_eeprom_band_1;
554		break;
555	case 2:		/* 4.9GHz band */
556		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
557		*eeprom_ch_info = (struct iwl_eeprom_channel *)
558				iwl_eeprom_query_addr(priv, offset);
559		*eeprom_ch_index = iwl_eeprom_band_2;
560		break;
561	case 3:		/* 5.2GHz band */
562		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
563		*eeprom_ch_info = (struct iwl_eeprom_channel *)
564				iwl_eeprom_query_addr(priv, offset);
565		*eeprom_ch_index = iwl_eeprom_band_3;
566		break;
567	case 4:		/* 5.5GHz band */
568		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
569		*eeprom_ch_info = (struct iwl_eeprom_channel *)
570				iwl_eeprom_query_addr(priv, offset);
571		*eeprom_ch_index = iwl_eeprom_band_4;
572		break;
573	case 5:		/* 5.7GHz band */
574		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
575		*eeprom_ch_info = (struct iwl_eeprom_channel *)
576				iwl_eeprom_query_addr(priv, offset);
577		*eeprom_ch_index = iwl_eeprom_band_5;
578		break;
579	case 6:		/* 2.4GHz ht40 channels */
580		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
581		*eeprom_ch_info = (struct iwl_eeprom_channel *)
582				iwl_eeprom_query_addr(priv, offset);
583		*eeprom_ch_index = iwl_eeprom_band_6;
584		break;
585	case 7:		/* 5 GHz ht40 channels */
586		*eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
587		*eeprom_ch_info = (struct iwl_eeprom_channel *)
588				iwl_eeprom_query_addr(priv, offset);
589		*eeprom_ch_index = iwl_eeprom_band_7;
590		break;
591	default:
592		BUG();
593		return;
594	}
595}
596
597#define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
598			    ? # x " " : "")
599/**
600 * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv.
601 *
602 * Does not set up a command, or touch hardware.
603 */
604static int iwl_mod_ht40_chan_info(struct iwl_priv *priv,
605			      enum ieee80211_band band, u16 channel,
606			      const struct iwl_eeprom_channel *eeprom_ch,
607			      u8 clear_ht40_extension_channel)
608{
609	struct iwl_channel_info *ch_info;
610
611	ch_info = (struct iwl_channel_info *)
612			iwl_get_channel_info(priv, band, channel);
613
614	if (!is_channel_valid(ch_info))
615		return -1;
616
617	IWL_DEBUG_EEPROM(priv, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
618			" Ad-Hoc %ssupported\n",
619			ch_info->channel,
620			is_channel_a_band(ch_info) ?
621			"5.2" : "2.4",
622			CHECK_AND_PRINT(IBSS),
623			CHECK_AND_PRINT(ACTIVE),
624			CHECK_AND_PRINT(RADAR),
625			CHECK_AND_PRINT(WIDE),
626			CHECK_AND_PRINT(DFS),
627			eeprom_ch->flags,
628			eeprom_ch->max_power_avg,
629			((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
630			 && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
631			"" : "not ");
632
633	ch_info->ht40_eeprom = *eeprom_ch;
634	ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
635	ch_info->ht40_flags = eeprom_ch->flags;
636	if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
637		ch_info->ht40_extension_channel &= ~clear_ht40_extension_channel;
638
639	return 0;
640}
641
642#define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
643			    ? # x " " : "")
644
645/**
646 * iwl_init_channel_map - Set up driver's info for all possible channels
647 */
648int iwl_init_channel_map(struct iwl_priv *priv)
649{
650	int eeprom_ch_count = 0;
651	const u8 *eeprom_ch_index = NULL;
652	const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
653	int band, ch;
654	struct iwl_channel_info *ch_info;
655
656	if (priv->channel_count) {
657		IWL_DEBUG_EEPROM(priv, "Channel map already initialized.\n");
658		return 0;
659	}
660
661	IWL_DEBUG_EEPROM(priv, "Initializing regulatory info from EEPROM\n");
662
663	priv->channel_count =
664	    ARRAY_SIZE(iwl_eeprom_band_1) +
665	    ARRAY_SIZE(iwl_eeprom_band_2) +
666	    ARRAY_SIZE(iwl_eeprom_band_3) +
667	    ARRAY_SIZE(iwl_eeprom_band_4) +
668	    ARRAY_SIZE(iwl_eeprom_band_5);
669
670	IWL_DEBUG_EEPROM(priv, "Parsing data for %d channels.\n",
671			priv->channel_count);
672
673	priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
674				     priv->channel_count, GFP_KERNEL);
675	if (!priv->channel_info) {
676		IWL_ERR(priv, "Could not allocate channel_info\n");
677		priv->channel_count = 0;
678		return -ENOMEM;
679	}
680
681	ch_info = priv->channel_info;
682
683	/* Loop through the 5 EEPROM bands adding them in order to the
684	 * channel map we maintain (that contains additional information than
685	 * what just in the EEPROM) */
686	for (band = 1; band <= 5; band++) {
687
688		iwl_init_band_reference(priv, band, &eeprom_ch_count,
689					&eeprom_ch_info, &eeprom_ch_index);
690
691		/* Loop through each band adding each of the channels */
692		for (ch = 0; ch < eeprom_ch_count; ch++) {
693			ch_info->channel = eeprom_ch_index[ch];
694			ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
695			    IEEE80211_BAND_5GHZ;
696
697			/* permanently store EEPROM's channel regulatory flags
698			 *   and max power in channel info database. */
699			ch_info->eeprom = eeprom_ch_info[ch];
700
701			/* Copy the run-time flags so they are there even on
702			 * invalid channels */
703			ch_info->flags = eeprom_ch_info[ch].flags;
704			/* First write that ht40 is not enabled, and then enable
705			 * one by one */
706			ch_info->ht40_extension_channel =
707					IEEE80211_CHAN_NO_HT40;
708
709			if (!(is_channel_valid(ch_info))) {
710				IWL_DEBUG_EEPROM(priv,
711					       "Ch. %d Flags %x [%sGHz] - "
712					       "No traffic\n",
713					       ch_info->channel,
714					       ch_info->flags,
715					       is_channel_a_band(ch_info) ?
716					       "5.2" : "2.4");
717				ch_info++;
718				continue;
719			}
720
721			/* Initialize regulatory-based run-time data */
722			ch_info->max_power_avg = ch_info->curr_txpow =
723			    eeprom_ch_info[ch].max_power_avg;
724			ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
725			ch_info->min_power = 0;
726
727			IWL_DEBUG_EEPROM(priv, "Ch. %d [%sGHz] "
728				       "%s%s%s%s%s%s(0x%02x %ddBm):"
729				       " Ad-Hoc %ssupported\n",
730				       ch_info->channel,
731				       is_channel_a_band(ch_info) ?
732				       "5.2" : "2.4",
733				       CHECK_AND_PRINT_I(VALID),
734				       CHECK_AND_PRINT_I(IBSS),
735				       CHECK_AND_PRINT_I(ACTIVE),
736				       CHECK_AND_PRINT_I(RADAR),
737				       CHECK_AND_PRINT_I(WIDE),
738				       CHECK_AND_PRINT_I(DFS),
739				       eeprom_ch_info[ch].flags,
740				       eeprom_ch_info[ch].max_power_avg,
741				       ((eeprom_ch_info[ch].
742					 flags & EEPROM_CHANNEL_IBSS)
743					&& !(eeprom_ch_info[ch].
744					     flags & EEPROM_CHANNEL_RADAR))
745				       ? "" : "not ");
746
747			ch_info++;
748		}
749	}
750
751	/* Check if we do have HT40 channels */
752	if (priv->cfg->lib->eeprom_ops.regulatory_bands[5] ==
753	    EEPROM_REGULATORY_BAND_NO_HT40 &&
754	    priv->cfg->lib->eeprom_ops.regulatory_bands[6] ==
755	    EEPROM_REGULATORY_BAND_NO_HT40)
756		return 0;
757
758	/* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
759	for (band = 6; band <= 7; band++) {
760		enum ieee80211_band ieeeband;
761
762		iwl_init_band_reference(priv, band, &eeprom_ch_count,
763					&eeprom_ch_info, &eeprom_ch_index);
764
765		/* EEPROM band 6 is 2.4, band 7 is 5 GHz */
766		ieeeband =
767			(band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
768
769		/* Loop through each band adding each of the channels */
770		for (ch = 0; ch < eeprom_ch_count; ch++) {
771			/* Set up driver's info for lower half */
772			iwl_mod_ht40_chan_info(priv, ieeeband,
773						eeprom_ch_index[ch],
774						&eeprom_ch_info[ch],
775						IEEE80211_CHAN_NO_HT40PLUS);
776
777			/* Set up driver's info for upper half */
778			iwl_mod_ht40_chan_info(priv, ieeeband,
779						eeprom_ch_index[ch] + 4,
780						&eeprom_ch_info[ch],
781						IEEE80211_CHAN_NO_HT40MINUS);
782		}
783	}
784
785	/* for newer device (6000 series and up)
786	 * EEPROM contain enhanced tx power information
787	 * driver need to process addition information
788	 * to determine the max channel tx power limits
789	 */
790	if (priv->cfg->lib->eeprom_ops.update_enhanced_txpower)
791		priv->cfg->lib->eeprom_ops.update_enhanced_txpower(priv);
792
793	return 0;
794}
795
796/*
797 * iwl_free_channel_map - undo allocations in iwl_init_channel_map
798 */
799void iwl_free_channel_map(struct iwl_priv *priv)
800{
801	kfree(priv->channel_info);
802	priv->channel_count = 0;
803}
804
805/**
806 * iwl_get_channel_info - Find driver's private channel info
807 *
808 * Based on band and channel number.
809 */
810const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
811					enum ieee80211_band band, u16 channel)
812{
813	int i;
814
815	switch (band) {
816	case IEEE80211_BAND_5GHZ:
817		for (i = 14; i < priv->channel_count; i++) {
818			if (priv->channel_info[i].channel == channel)
819				return &priv->channel_info[i];
820		}
821		break;
822	case IEEE80211_BAND_2GHZ:
823		if (channel >= 1 && channel <= 14)
824			return &priv->channel_info[channel - 1];
825		break;
826	default:
827		BUG();
828	}
829
830	return NULL;
831}
832
833void iwl_rf_config(struct iwl_priv *priv)
834{
835	u16 radio_cfg;
836
837	radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
838
839	/* write radio config values to register */
840	if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) {
841		iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
842			    EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
843			    EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
844			    EEPROM_RF_CFG_DASH_MSK(radio_cfg));
845		IWL_INFO(priv, "Radio type=0x%x-0x%x-0x%x\n",
846			 EEPROM_RF_CFG_TYPE_MSK(radio_cfg),
847			 EEPROM_RF_CFG_STEP_MSK(radio_cfg),
848			 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
849	} else
850		WARN_ON(1);
851
852	/* set CSR_HW_CONFIG_REG for uCode use */
853	iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
854		    CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
855		    CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
856}