PageRenderTime 28ms CodeModel.GetById 18ms app.highlight 8ms RepoModel.GetById 0ms app.codeStats 0ms

/drivers/net/wireless/bcmdhd/siutils_priv.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C Header | 235 lines | 156 code | 40 blank | 39 comment | 40 complexity | b152461644b043965a23914f989194d6 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1/*
  2 * Include file private to the SOC Interconnect support files.
  3 *
  4 * Copyright (C) 1999-2011, Broadcom Corporation
  5 * 
  6 *         Unless you and Broadcom execute a separate written software license
  7 * agreement governing use of this software, this software is licensed to you
  8 * under the terms of the GNU General Public License version 2 (the "GPL"),
  9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
 10 * following added to such license:
 11 * 
 12 *      As a special exception, the copyright holders of this software give you
 13 * permission to link this software with independent modules, and to copy and
 14 * distribute the resulting executable under terms of your choice, provided that
 15 * you also meet, for each linked independent module, the terms and conditions of
 16 * the license of that module.  An independent module is a module which is not
 17 * derived from this software.  The special exception does not apply to any
 18 * modifications of the software.
 19 * 
 20 *      Notwithstanding the above, under no circumstances may you combine this
 21 * software in any way with any other Broadcom software provided under a license
 22 * other than the GPL, without Broadcom's express prior written consent.
 23 *
 24 * $Id: siutils_priv.h,v 1.17.4.3 2010-10-25 16:56:56 Exp $
 25 */
 26
 27#ifndef	_siutils_priv_h_
 28#define	_siutils_priv_h_
 29
 30#define	SI_ERROR(args)
 31
 32#define	SI_MSG(args)
 33
 34/* Define SI_VMSG to printf for verbose debugging, but don't check it in */
 35#define	SI_VMSG(args)
 36
 37#define	IS_SIM(chippkg)	((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
 38
 39typedef uint32 (*si_intrsoff_t)(void *intr_arg);
 40typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
 41typedef bool (*si_intrsenabled_t)(void *intr_arg);
 42
 43typedef struct gpioh_item {
 44	void			*arg;
 45	bool			level;
 46	gpio_handler_t		handler;
 47	uint32			event;
 48	struct gpioh_item	*next;
 49} gpioh_item_t;
 50
 51/* misc si info needed by some of the routines */
 52typedef struct si_info {
 53	struct si_pub pub;		/* back plane public state (must be first field) */
 54
 55	void	*osh;			/* osl os handle */
 56	void	*sdh;			/* bcmsdh handle */
 57
 58	uint	dev_coreid;		/* the core provides driver functions */
 59	void	*intr_arg;		/* interrupt callback function arg */
 60	si_intrsoff_t intrsoff_fn;	/* turns chip interrupts off */
 61	si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
 62	si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
 63
 64	void *pch;			/* PCI/E core handle */
 65
 66	gpioh_item_t *gpioh_head; 	/* GPIO event handlers list */
 67
 68	bool	memseg;			/* flag to toggle MEM_SEG register */
 69
 70	char *vars;
 71	uint varsz;
 72
 73	void	*curmap;		/* current regs va */
 74	void	*regs[SI_MAXCORES];	/* other regs va */
 75
 76	uint	curidx;			/* current core index */
 77	uint	numcores;		/* # discovered cores */
 78	uint	coreid[SI_MAXCORES];	/* id of each core */
 79	uint32	coresba[SI_MAXCORES];	/* backplane address of each core */
 80	void	*regs2[SI_MAXCORES];	/* va of each core second register set (usbh20) */
 81	uint32	coresba2[SI_MAXCORES];	/* address of each core second register set (usbh20) */
 82	uint32	coresba_size[SI_MAXCORES]; /* backplane address space size */
 83	uint32	coresba2_size[SI_MAXCORES]; /* second address space size */
 84
 85	void	*curwrap;		/* current wrapper va */
 86	void	*wrappers[SI_MAXCORES];	/* other cores wrapper va */
 87	uint32	wrapba[SI_MAXCORES];	/* address of controlling wrapper */
 88
 89	uint32	cia[SI_MAXCORES];	/* erom cia entry for each core */
 90	uint32	cib[SI_MAXCORES];	/* erom cia entry for each core */
 91	uint32	oob_router;		/* oob router registers for axi */
 92} si_info_t;
 93
 94#define	SI_INFO(sih)	(si_info_t *)(uintptr)sih
 95
 96#define	GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
 97		ISALIGNED((x), SI_CORE_SIZE))
 98#define	GOODREGS(regs)	((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
 99#define BADCOREADDR	0
100#define	GOODIDX(idx)	(((uint)idx) < SI_MAXCORES)
101#define	NOREV		-1		/* Invalid rev */
102
103#define PCI(si)		((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&	\
104			 ((si)->pub.buscoretype == PCI_CORE_ID))
105#define PCIE(si)	((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&	\
106			 ((si)->pub.buscoretype == PCIE_CORE_ID))
107#define PCMCIA(si)	((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
108
109/* Newer chips can access PCI/PCIE and CC core without requiring to change
110 * PCI BAR0 WIN
111 */
112#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) ||	\
113		     (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
114
115#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
116#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
117
118/*
119 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
120 * after core switching to avoid invalid register accesss inside ISR.
121 */
122#define INTR_OFF(si, intr_val) \
123	if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) {	\
124		intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
125#define INTR_RESTORE(si, intr_val) \
126	if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) {	\
127		(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
128
129/* dynamic clock control defines */
130#define	LPOMINFREQ		25000		/* low power oscillator min */
131#define	LPOMAXFREQ		43000		/* low power oscillator max */
132#define	XTALMINFREQ		19800000	/* 20 MHz - 1% */
133#define	XTALMAXFREQ		20200000	/* 20 MHz + 1% */
134#define	PCIMINFREQ		25000000	/* 25 MHz */
135#define	PCIMAXFREQ		34000000	/* 33 MHz + fudge */
136
137#define	ILP_DIV_5MHZ		0		/* ILP = 5 MHz */
138#define	ILP_DIV_1MHZ		4		/* ILP = 1 MHz */
139
140#define PCI_FORCEHT(si)	\
141	(((PCIE(si)) && (si->pub.chip == BCM4311_CHIP_ID) && ((si->pub.chiprev <= 1))) || \
142	((PCI(si) || PCIE(si)) && (si->pub.chip == BCM4321_CHIP_ID)) || \
143	(PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID)))
144
145/* GPIO Based LED powersave defines */
146#define DEFAULT_GPIO_ONTIME	10		/* Default: 10% on */
147#define DEFAULT_GPIO_OFFTIME	90		/* Default: 10% on */
148
149#ifndef DEFAULT_GPIOTIMERVAL
150#define DEFAULT_GPIOTIMERVAL  ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
151#endif
152
153/* Silicon Backplane externs */
154extern void sb_scan(si_t *sih, void *regs, uint devid);
155extern uint sb_coreid(si_t *sih);
156extern uint sb_intflag(si_t *sih);
157extern uint sb_flag(si_t *sih);
158extern void sb_setint(si_t *sih, int siflag);
159extern uint sb_corevendor(si_t *sih);
160extern uint sb_corerev(si_t *sih);
161extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
162extern bool sb_iscoreup(si_t *sih);
163extern void *sb_setcoreidx(si_t *sih, uint coreidx);
164extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val);
165extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
166extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val);
167extern void sb_commit(si_t *sih);
168extern uint32 sb_base(uint32 admatch);
169extern uint32 sb_size(uint32 admatch);
170extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
171extern void sb_core_disable(si_t *sih, uint32 bits);
172extern uint32 sb_addrspace(si_t *sih, uint asidx);
173extern uint32 sb_addrspacesize(si_t *sih, uint asidx);
174extern int sb_numaddrspaces(si_t *sih);
175
176extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx);
177
178extern bool sb_taclear(si_t *sih, bool details);
179
180
181/* Wake-on-wireless-LAN (WOWL) */
182extern bool sb_pci_pmecap(si_t *sih);
183struct osl_info;
184extern bool sb_pci_fastpmecap(struct osl_info *osh);
185extern bool sb_pci_pmeclr(si_t *sih);
186extern void sb_pci_pmeen(si_t *sih);
187extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset);
188
189/* AMBA Interconnect exported externs */
190extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
191                       void *sdh, char **vars, uint *varsz);
192extern si_t *ai_kattach(osl_t *osh);
193extern void ai_scan(si_t *sih, void *regs, uint devid);
194
195extern uint ai_flag(si_t *sih);
196extern void ai_setint(si_t *sih, int siflag);
197extern uint ai_coreidx(si_t *sih);
198extern uint ai_corevendor(si_t *sih);
199extern uint ai_corerev(si_t *sih);
200extern bool ai_iscoreup(si_t *sih);
201extern void *ai_setcoreidx(si_t *sih, uint coreidx);
202extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
203extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
204extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
205extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
206extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
207extern void ai_core_disable(si_t *sih, uint32 bits);
208extern int ai_numaddrspaces(si_t *sih);
209extern uint32 ai_addrspace(si_t *sih, uint asidx);
210extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
211extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
212
213
214
215#define ub_scan(a, b, c) do {} while (0)
216#define ub_flag(a) (0)
217#define ub_setint(a, b) do {} while (0)
218#define ub_coreidx(a) (0)
219#define ub_corevendor(a) (0)
220#define ub_corerev(a) (0)
221#define ub_iscoreup(a) (0)
222#define ub_setcoreidx(a, b) (0)
223#define ub_core_cflags(a, b, c) (0)
224#define ub_core_cflags_wo(a, b, c) do {} while (0)
225#define ub_core_sflags(a, b, c) (0)
226#define ub_corereg(a, b, c, d, e) (0)
227#define ub_core_reset(a, b, c) do {} while (0)
228#define ub_core_disable(a, b) do {} while (0)
229#define ub_numaddrspaces(a) (0)
230#define ub_addrspace(a, b)  (0)
231#define ub_addrspacesize(a, b) (0)
232#define ub_view(a, b) do {} while (0)
233#define ub_dumpregs(a, b) do {} while (0)
234
235#endif	/* _siutils_priv_h_ */