/drivers/net/wireless/bcmdhd/siutils_priv.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t · C Header · 235 lines · 156 code · 40 blank · 39 comment · 40 complexity · b152461644b043965a23914f989194d6 MD5 · raw file

  1. /*
  2. * Include file private to the SOC Interconnect support files.
  3. *
  4. * Copyright (C) 1999-2011, Broadcom Corporation
  5. *
  6. * Unless you and Broadcom execute a separate written software license
  7. * agreement governing use of this software, this software is licensed to you
  8. * under the terms of the GNU General Public License version 2 (the "GPL"),
  9. * available at http://www.broadcom.com/licenses/GPLv2.php, with the
  10. * following added to such license:
  11. *
  12. * As a special exception, the copyright holders of this software give you
  13. * permission to link this software with independent modules, and to copy and
  14. * distribute the resulting executable under terms of your choice, provided that
  15. * you also meet, for each linked independent module, the terms and conditions of
  16. * the license of that module. An independent module is a module which is not
  17. * derived from this software. The special exception does not apply to any
  18. * modifications of the software.
  19. *
  20. * Notwithstanding the above, under no circumstances may you combine this
  21. * software in any way with any other Broadcom software provided under a license
  22. * other than the GPL, without Broadcom's express prior written consent.
  23. *
  24. * $Id: siutils_priv.h,v 1.17.4.3 2010-10-25 16:56:56 Exp $
  25. */
  26. #ifndef _siutils_priv_h_
  27. #define _siutils_priv_h_
  28. #define SI_ERROR(args)
  29. #define SI_MSG(args)
  30. /* Define SI_VMSG to printf for verbose debugging, but don't check it in */
  31. #define SI_VMSG(args)
  32. #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
  33. typedef uint32 (*si_intrsoff_t)(void *intr_arg);
  34. typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
  35. typedef bool (*si_intrsenabled_t)(void *intr_arg);
  36. typedef struct gpioh_item {
  37. void *arg;
  38. bool level;
  39. gpio_handler_t handler;
  40. uint32 event;
  41. struct gpioh_item *next;
  42. } gpioh_item_t;
  43. /* misc si info needed by some of the routines */
  44. typedef struct si_info {
  45. struct si_pub pub; /* back plane public state (must be first field) */
  46. void *osh; /* osl os handle */
  47. void *sdh; /* bcmsdh handle */
  48. uint dev_coreid; /* the core provides driver functions */
  49. void *intr_arg; /* interrupt callback function arg */
  50. si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
  51. si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
  52. si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
  53. void *pch; /* PCI/E core handle */
  54. gpioh_item_t *gpioh_head; /* GPIO event handlers list */
  55. bool memseg; /* flag to toggle MEM_SEG register */
  56. char *vars;
  57. uint varsz;
  58. void *curmap; /* current regs va */
  59. void *regs[SI_MAXCORES]; /* other regs va */
  60. uint curidx; /* current core index */
  61. uint numcores; /* # discovered cores */
  62. uint coreid[SI_MAXCORES]; /* id of each core */
  63. uint32 coresba[SI_MAXCORES]; /* backplane address of each core */
  64. void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */
  65. uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
  66. uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */
  67. uint32 coresba2_size[SI_MAXCORES]; /* second address space size */
  68. void *curwrap; /* current wrapper va */
  69. void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
  70. uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
  71. uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */
  72. uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */
  73. uint32 oob_router; /* oob router registers for axi */
  74. } si_info_t;
  75. #define SI_INFO(sih) (si_info_t *)(uintptr)sih
  76. #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
  77. ISALIGNED((x), SI_CORE_SIZE))
  78. #define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
  79. #define BADCOREADDR 0
  80. #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
  81. #define NOREV -1 /* Invalid rev */
  82. #define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
  83. ((si)->pub.buscoretype == PCI_CORE_ID))
  84. #define PCIE(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
  85. ((si)->pub.buscoretype == PCIE_CORE_ID))
  86. #define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
  87. /* Newer chips can access PCI/PCIE and CC core without requiring to change
  88. * PCI BAR0 WIN
  89. */
  90. #define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
  91. (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
  92. #define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
  93. #define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
  94. /*
  95. * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
  96. * after core switching to avoid invalid register accesss inside ISR.
  97. */
  98. #define INTR_OFF(si, intr_val) \
  99. if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
  100. intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
  101. #define INTR_RESTORE(si, intr_val) \
  102. if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
  103. (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
  104. /* dynamic clock control defines */
  105. #define LPOMINFREQ 25000 /* low power oscillator min */
  106. #define LPOMAXFREQ 43000 /* low power oscillator max */
  107. #define XTALMINFREQ 19800000 /* 20 MHz - 1% */
  108. #define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
  109. #define PCIMINFREQ 25000000 /* 25 MHz */
  110. #define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
  111. #define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
  112. #define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
  113. #define PCI_FORCEHT(si) \
  114. (((PCIE(si)) && (si->pub.chip == BCM4311_CHIP_ID) && ((si->pub.chiprev <= 1))) || \
  115. ((PCI(si) || PCIE(si)) && (si->pub.chip == BCM4321_CHIP_ID)) || \
  116. (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID)))
  117. /* GPIO Based LED powersave defines */
  118. #define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
  119. #define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
  120. #ifndef DEFAULT_GPIOTIMERVAL
  121. #define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
  122. #endif
  123. /* Silicon Backplane externs */
  124. extern void sb_scan(si_t *sih, void *regs, uint devid);
  125. extern uint sb_coreid(si_t *sih);
  126. extern uint sb_intflag(si_t *sih);
  127. extern uint sb_flag(si_t *sih);
  128. extern void sb_setint(si_t *sih, int siflag);
  129. extern uint sb_corevendor(si_t *sih);
  130. extern uint sb_corerev(si_t *sih);
  131. extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
  132. extern bool sb_iscoreup(si_t *sih);
  133. extern void *sb_setcoreidx(si_t *sih, uint coreidx);
  134. extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val);
  135. extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
  136. extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val);
  137. extern void sb_commit(si_t *sih);
  138. extern uint32 sb_base(uint32 admatch);
  139. extern uint32 sb_size(uint32 admatch);
  140. extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
  141. extern void sb_core_disable(si_t *sih, uint32 bits);
  142. extern uint32 sb_addrspace(si_t *sih, uint asidx);
  143. extern uint32 sb_addrspacesize(si_t *sih, uint asidx);
  144. extern int sb_numaddrspaces(si_t *sih);
  145. extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx);
  146. extern bool sb_taclear(si_t *sih, bool details);
  147. /* Wake-on-wireless-LAN (WOWL) */
  148. extern bool sb_pci_pmecap(si_t *sih);
  149. struct osl_info;
  150. extern bool sb_pci_fastpmecap(struct osl_info *osh);
  151. extern bool sb_pci_pmeclr(si_t *sih);
  152. extern void sb_pci_pmeen(si_t *sih);
  153. extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset);
  154. /* AMBA Interconnect exported externs */
  155. extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
  156. void *sdh, char **vars, uint *varsz);
  157. extern si_t *ai_kattach(osl_t *osh);
  158. extern void ai_scan(si_t *sih, void *regs, uint devid);
  159. extern uint ai_flag(si_t *sih);
  160. extern void ai_setint(si_t *sih, int siflag);
  161. extern uint ai_coreidx(si_t *sih);
  162. extern uint ai_corevendor(si_t *sih);
  163. extern uint ai_corerev(si_t *sih);
  164. extern bool ai_iscoreup(si_t *sih);
  165. extern void *ai_setcoreidx(si_t *sih, uint coreidx);
  166. extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
  167. extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
  168. extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
  169. extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
  170. extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
  171. extern void ai_core_disable(si_t *sih, uint32 bits);
  172. extern int ai_numaddrspaces(si_t *sih);
  173. extern uint32 ai_addrspace(si_t *sih, uint asidx);
  174. extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
  175. extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
  176. #define ub_scan(a, b, c) do {} while (0)
  177. #define ub_flag(a) (0)
  178. #define ub_setint(a, b) do {} while (0)
  179. #define ub_coreidx(a) (0)
  180. #define ub_corevendor(a) (0)
  181. #define ub_corerev(a) (0)
  182. #define ub_iscoreup(a) (0)
  183. #define ub_setcoreidx(a, b) (0)
  184. #define ub_core_cflags(a, b, c) (0)
  185. #define ub_core_cflags_wo(a, b, c) do {} while (0)
  186. #define ub_core_sflags(a, b, c) (0)
  187. #define ub_corereg(a, b, c, d, e) (0)
  188. #define ub_core_reset(a, b, c) do {} while (0)
  189. #define ub_core_disable(a, b) do {} while (0)
  190. #define ub_numaddrspaces(a) (0)
  191. #define ub_addrspace(a, b) (0)
  192. #define ub_addrspacesize(a, b) (0)
  193. #define ub_view(a, b) do {} while (0)
  194. #define ub_dumpregs(a, b) do {} while (0)
  195. #endif /* _siutils_priv_h_ */