/drivers/net/wireless/bcm4329/include/sbsdio.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t · C Header · 166 lines · 81 code · 22 blank · 63 comment · 3 complexity · 571d8ba6ae5c8d6a88677f3541ab881e MD5 · raw file

  1. /*
  2. * SDIO device core hardware definitions.
  3. * sdio is a portion of the pcmcia core in core rev 3 - rev 8
  4. *
  5. * SDIO core support 1bit, 4 bit SDIO mode as well as SPI mode.
  6. *
  7. * Copyright (C) 1999-2010, Broadcom Corporation
  8. *
  9. * Unless you and Broadcom execute a separate written software license
  10. * agreement governing use of this software, this software is licensed to you
  11. * under the terms of the GNU General Public License version 2 (the "GPL"),
  12. * available at http://www.broadcom.com/licenses/GPLv2.php, with the
  13. * following added to such license:
  14. *
  15. * As a special exception, the copyright holders of this software give you
  16. * permission to link this software with independent modules, and to copy and
  17. * distribute the resulting executable under terms of your choice, provided that
  18. * you also meet, for each linked independent module, the terms and conditions of
  19. * the license of that module. An independent module is a module which is not
  20. * derived from this software. The special exception does not apply to any
  21. * modifications of the software.
  22. *
  23. * Notwithstanding the above, under no circumstances may you combine this
  24. * software in any way with any other Broadcom software provided under a license
  25. * other than the GPL, without Broadcom's express prior written consent.
  26. *
  27. * $Id: sbsdio.h,v 13.29.4.1.22.3 2009/03/11 20:26:57 Exp $
  28. */
  29. #ifndef _SBSDIO_H
  30. #define _SBSDIO_H
  31. #define SBSDIO_NUM_FUNCTION 3 /* as of sdiod rev 0, supports 3 functions */
  32. /* function 1 miscellaneous registers */
  33. #define SBSDIO_SPROM_CS 0x10000 /* sprom command and status */
  34. #define SBSDIO_SPROM_INFO 0x10001 /* sprom info register */
  35. #define SBSDIO_SPROM_DATA_LOW 0x10002 /* sprom indirect access data byte 0 */
  36. #define SBSDIO_SPROM_DATA_HIGH 0x10003 /* sprom indirect access data byte 1 */
  37. #define SBSDIO_SPROM_ADDR_LOW 0x10004 /* sprom indirect access addr byte 0 */
  38. #define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* sprom indirect access addr byte 0 */
  39. #define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu (gpio) output */
  40. #define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu (gpio) enable */
  41. #define SBSDIO_WATERMARK 0x10008 /* rev < 7, watermark for sdio device */
  42. #define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */
  43. /* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */
  44. #define SBSDIO_FUNC1_SBADDRLOW 0x1000A /* SB Address Window Low (b15) */
  45. #define SBSDIO_FUNC1_SBADDRMID 0x1000B /* SB Address Window Mid (b23:b16) */
  46. #define SBSDIO_FUNC1_SBADDRHIGH 0x1000C /* SB Address Window High (b31:b24) */
  47. #define SBSDIO_FUNC1_FRAMECTRL 0x1000D /* Frame Control (frame term/abort) */
  48. #define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E /* ChipClockCSR (ALP/HT ctl/status) */
  49. #define SBSDIO_FUNC1_SDIOPULLUP 0x1000F /* SdioPullUp (on cmd, d0-d2) */
  50. #define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 /* Write Frame Byte Count Low */
  51. #define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A /* Write Frame Byte Count High */
  52. #define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B /* Read Frame Byte Count Low */
  53. #define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C /* Read Frame Byte Count High */
  54. #define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
  55. #define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */
  56. /* SBSDIO_SPROM_CS */
  57. #define SBSDIO_SPROM_IDLE 0
  58. #define SBSDIO_SPROM_WRITE 1
  59. #define SBSDIO_SPROM_READ 2
  60. #define SBSDIO_SPROM_WEN 4
  61. #define SBSDIO_SPROM_WDS 7
  62. #define SBSDIO_SPROM_DONE 8
  63. /* SBSDIO_SPROM_INFO */
  64. #define SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */
  65. #define SROM_BLANK 0x04 /* depreciated in corerev 6 */
  66. #define SROM_OTP 0x80 /* OTP present */
  67. /* SBSDIO_CHIP_CTRL */
  68. #define SBSDIO_CHIP_CTRL_XTAL 0x01 /* or'd with onchip xtal_pu,
  69. * 1: power on oscillator
  70. * (for 4318 only)
  71. */
  72. /* SBSDIO_WATERMARK */
  73. #define SBSDIO_WATERMARK_MASK 0x7f /* number of words - 1 for sd device
  74. * to wait before sending data to host
  75. */
  76. /* SBSDIO_DEVICE_CTL */
  77. #define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when
  78. * receiving CMD53
  79. */
  80. #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is
  81. * synchronous to the sdio clock
  82. */
  83. #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host
  84. * except the chipActive (rev 8)
  85. */
  86. #define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put
  87. * external pads in tri-state; requires
  88. * sdio bus power cycle to clear (rev 9)
  89. */
  90. #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */
  91. #define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */
  92. #define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */
  93. #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */
  94. /* SBSDIO_FUNC1_CHIPCLKCSR */
  95. #define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */
  96. #define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */
  97. #define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */
  98. #define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */
  99. #define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */
  100. #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */
  101. #define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */
  102. #define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */
  103. /* In rev8, actual avail bits followed original docs */
  104. #define SBSDIO_Rev8_HT_AVAIL 0x40
  105. #define SBSDIO_Rev8_ALP_AVAIL 0x80
  106. #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
  107. #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
  108. #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
  109. #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
  110. #define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \
  111. (alponly ? 1 : SBSDIO_HTAV(regval)))
  112. /* SBSDIO_FUNC1_SDIOPULLUP */
  113. #define SBSDIO_PULLUP_D0 0x01 /* Enable D0/MISO pullup */
  114. #define SBSDIO_PULLUP_D1 0x02 /* Enable D1/INT# pullup */
  115. #define SBSDIO_PULLUP_D2 0x04 /* Enable D2 pullup */
  116. #define SBSDIO_PULLUP_CMD 0x08 /* Enable CMD/MOSI pullup */
  117. #define SBSDIO_PULLUP_ALL 0x0f /* All valid bits */
  118. /* function 1 OCP space */
  119. #define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF /* sb offset addr is <= 15 bits, 32k */
  120. #define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
  121. #define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 /* with b15, maps to 32-bit SB access */
  122. /* some duplication with sbsdpcmdev.h here */
  123. /* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
  124. #define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
  125. #define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
  126. #define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
  127. #define SBSDIO_SBWINDOW_MASK 0xffff8000 /* Address bits from SBADDR regs */
  128. /* direct(mapped) cis space */
  129. #define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */
  130. #define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */
  131. #define SBSDIO_OTP_CIS_SIZE_LIMIT 0x078 /* maximum bytes OTP CIS */
  132. #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */
  133. #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple,
  134. * link bytes
  135. */
  136. /* indirect cis access (in sprom) */
  137. #define SBSDIO_SPROM_CIS_OFFSET 0x8 /* 8 control bytes first, CIS starts from
  138. * 8th byte
  139. */
  140. #define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* sdio byte mode: maximum length of one
  141. * data comamnd
  142. */
  143. #define SBSDIO_CORE_ADDR_MASK 0x1FFFF /* sdio core function one address mask */
  144. #endif /* _SBSDIO_H */