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/drivers/net/wireless/bcm4329/include/bcmpcispi.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C Header | 205 lines | 118 code | 23 blank | 64 comment | 0 complexity | 60549812f25ec600ca5dcda687f6397f MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1/*
  2 * Broadcom PCI-SPI Host Controller Register Definitions
  3 *
  4 * Copyright (C) 1999-2010, Broadcom Corporation
  5 * 
  6 *      Unless you and Broadcom execute a separate written software license
  7 * agreement governing use of this software, this software is licensed to you
  8 * under the terms of the GNU General Public License version 2 (the "GPL"),
  9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
 10 * following added to such license:
 11 * 
 12 *      As a special exception, the copyright holders of this software give you
 13 * permission to link this software with independent modules, and to copy and
 14 * distribute the resulting executable under terms of your choice, provided that
 15 * you also meet, for each linked independent module, the terms and conditions of
 16 * the license of that module.  An independent module is a module which is not
 17 * derived from this software.  The special exception does not apply to any
 18 * modifications of the software.
 19 * 
 20 *      Notwithstanding the above, under no circumstances may you combine this
 21 * software in any way with any other Broadcom software provided under a license
 22 * other than the GPL, without Broadcom's express prior written consent.
 23 *
 24 * $Id: bcmpcispi.h,v 13.11.8.3 2008/07/09 21:23:29 Exp $
 25 */
 26
 27/* cpp contortions to concatenate w/arg prescan */
 28#ifndef PAD
 29#define	_PADLINE(line)	pad ## line
 30#define	_XSTR(line)	_PADLINE(line)
 31#define	PAD		_XSTR(__LINE__)
 32#endif	/* PAD */
 33
 34/*
 35+---------------------------------------------------------------------------+
 36|                                                                           |
 37|                     7     6     5     4     3     2     1       0         |
 38| 0x0000  SPI_CTRL    SPIE  SPE   0     MSTR  CPOL  CPHA  SPR1    SPR0      |
 39| 0x0004  SPI_STAT    SPIF  WCOL  ST1   ST0   WFFUL WFEMP RFFUL   RFEMP     |
 40| 0x0008  SPI_DATA    Bits 31:0, data to send out on MOSI                   |
 41| 0x000C  SPI_EXT     ICNT1 ICNT0 BSWAP *HSMODE           ESPR1   ESPR0     |
 42| 0x0020  GPIO_OE     0=input, 1=output                   PWR_OE  CS_OE     |
 43| 0x0024  GPIO_DATA   CARD:1=missing, 0=present     CARD  PWR_DAT CS_DAT    |
 44| 0x0040  INT_EDGE    0=level, 1=edge                     DEV_E   SPI_E     |
 45| 0x0044  INT_POL     1=active high, 0=active low         DEV_P   SPI_P     |
 46| 0x0048  INTMASK                                         DEV     SPI       |
 47| 0x004C  INTSTATUS                                       DEV     SPI       |
 48| 0x0060  HEXDISP     Reset value: 0x14e443f5.  In hexdisp mode, value      |
 49|                     shows on the Raggedstone1 4-digit 7-segment display.  |
 50| 0x0064  CURRENT_MA  Low 16 bits indicate card current consumption in mA   |
 51| 0x006C  DISP_SEL    Display mode (0=hexdisp, 1=current)         DSP       |
 52| 0x00C0  PLL_CTL  bit31=ext_clk, remainder unused.                         |
 53| 0x00C4  PLL_STAT                            LOCK                          |
 54| 0x00C8  CLK_FREQ                                                          |
 55| 0x00CC  CLK_CNT                                                           |
 56|                                                                           |
 57| *Notes: HSMODE is not implemented, never set this bit!                    |
 58| BSWAP is available in rev >= 8                                            |
 59|                                                                           |
 60+---------------------------------------------------------------------------+
 61*/
 62
 63typedef volatile struct {
 64	uint32 spih_ctrl;		/* 0x00 SPI Control Register */
 65	uint32 spih_stat;		/* 0x04 SPI Status Register */
 66	uint32 spih_data;		/* 0x08 SPI Data Register, 32-bits wide */
 67	uint32 spih_ext;		/* 0x0C SPI Extension Register */
 68	uint32 PAD[4];			/* 0x10-0x1F PADDING */
 69
 70	uint32 spih_gpio_ctrl;		/* 0x20 SPI GPIO Control Register */
 71	uint32 spih_gpio_data;		/* 0x24 SPI GPIO Data Register */
 72	uint32 PAD[6];			/* 0x28-0x3F PADDING */
 73
 74	uint32 spih_int_edge;		/* 0x40 SPI Interrupt Edge Register (0=Level, 1=Edge) */
 75	uint32 spih_int_pol;		/* 0x44 SPI Interrupt Polarity Register (0=Active Low, */
 76							/* 1=Active High) */
 77	uint32 spih_int_mask;		/* 0x48 SPI Interrupt Mask */
 78	uint32 spih_int_status;		/* 0x4C SPI Interrupt Status */
 79	uint32 PAD[4];			/* 0x50-0x5F PADDING */
 80
 81	uint32 spih_hex_disp;		/* 0x60 SPI 4-digit hex display value */
 82	uint32 spih_current_ma;		/* 0x64 SPI SD card current consumption in mA */
 83	uint32 PAD[1];			/* 0x68 PADDING */
 84	uint32 spih_disp_sel;		/* 0x6c SPI 4-digit hex display mode select (1=current) */
 85	uint32 PAD[4];			/* 0x70-0x7F PADDING */
 86	uint32 PAD[8];			/* 0x80-0x9F PADDING */
 87	uint32 PAD[8];			/* 0xA0-0xBF PADDING */
 88	uint32 spih_pll_ctrl;	/* 0xC0 PLL Control Register */
 89	uint32 spih_pll_status;	/* 0xC4 PLL Status Register */
 90	uint32 spih_xtal_freq;	/* 0xC8 External Clock Frequency in units of 10000Hz */
 91	uint32 spih_clk_count;	/* 0xCC External Clock Count Register */
 92
 93} spih_regs_t;
 94
 95typedef volatile struct {
 96	uint32 cfg_space[0x40];		/* 0x000-0x0FF PCI Configuration Space (Read Only) */
 97	uint32 P_IMG_CTRL0;		/* 0x100 PCI Image0 Control Register */
 98
 99	uint32 P_BA0;			/* 0x104 32 R/W PCI Image0 Base Address register */
100	uint32 P_AM0;			/* 0x108 32 R/W PCI Image0 Address Mask register */
101	uint32 P_TA0;			/* 0x10C 32 R/W PCI Image0 Translation Address register */
102	uint32 P_IMG_CTRL1;		/* 0x110 32 R/W PCI Image1 Control register */
103	uint32 P_BA1;			/* 0x114 32 R/W PCI Image1 Base Address register */
104	uint32 P_AM1;			/* 0x118 32 R/W PCI Image1 Address Mask register */
105	uint32 P_TA1;			/* 0x11C 32 R/W PCI Image1 Translation Address register */
106	uint32 P_IMG_CTRL2;		/* 0x120 32 R/W PCI Image2 Control register */
107	uint32 P_BA2;			/* 0x124 32 R/W PCI Image2 Base Address register */
108	uint32 P_AM2;			/* 0x128 32 R/W PCI Image2 Address Mask register */
109	uint32 P_TA2;			/* 0x12C 32 R/W PCI Image2 Translation Address register */
110	uint32 P_IMG_CTRL3;		/* 0x130 32 R/W PCI Image3 Control register */
111	uint32 P_BA3;			/* 0x134 32 R/W PCI Image3 Base Address register */
112	uint32 P_AM3;			/* 0x138 32 R/W PCI Image3 Address Mask register */
113	uint32 P_TA3;			/* 0x13C 32 R/W PCI Image3 Translation Address register */
114	uint32 P_IMG_CTRL4;		/* 0x140 32 R/W PCI Image4 Control register */
115	uint32 P_BA4;			/* 0x144 32 R/W PCI Image4 Base Address register */
116	uint32 P_AM4;			/* 0x148 32 R/W PCI Image4 Address Mask register */
117	uint32 P_TA4;			/* 0x14C 32 R/W PCI Image4 Translation Address register */
118	uint32 P_IMG_CTRL5;		/* 0x150 32 R/W PCI Image5 Control register */
119	uint32 P_BA5;			/* 0x154 32 R/W PCI Image5 Base Address register */
120	uint32 P_AM5;			/* 0x158 32 R/W PCI Image5 Address Mask register */
121	uint32 P_TA5;			/* 0x15C 32 R/W PCI Image5 Translation Address register */
122	uint32 P_ERR_CS;		/* 0x160 32 R/W PCI Error Control and Status register */
123	uint32 P_ERR_ADDR;		/* 0x164 32 R PCI Erroneous Address register */
124	uint32 P_ERR_DATA;		/* 0x168 32 R PCI Erroneous Data register */
125
126	uint32 PAD[5];			/* 0x16C-0x17F PADDING */
127
128	uint32 WB_CONF_SPC_BAR;		/* 0x180 32 R WISHBONE Configuration Space Base Address */
129	uint32 W_IMG_CTRL1;		/* 0x184 32 R/W WISHBONE Image1 Control register */
130	uint32 W_BA1;			/* 0x188 32 R/W WISHBONE Image1 Base Address register */
131	uint32 W_AM1;			/* 0x18C 32 R/W WISHBONE Image1 Address Mask register */
132	uint32 W_TA1;			/* 0x190 32 R/W WISHBONE Image1 Translation Address reg */
133	uint32 W_IMG_CTRL2;		/* 0x194 32 R/W WISHBONE Image2 Control register */
134	uint32 W_BA2;			/* 0x198 32 R/W WISHBONE Image2 Base Address register */
135	uint32 W_AM2;			/* 0x19C 32 R/W WISHBONE Image2 Address Mask register */
136	uint32 W_TA2;			/* 0x1A0 32 R/W WISHBONE Image2 Translation Address reg */
137	uint32 W_IMG_CTRL3;		/* 0x1A4 32 R/W WISHBONE Image3 Control register */
138	uint32 W_BA3;			/* 0x1A8 32 R/W WISHBONE Image3 Base Address register */
139	uint32 W_AM3;			/* 0x1AC 32 R/W WISHBONE Image3 Address Mask register */
140	uint32 W_TA3;			/* 0x1B0 32 R/W WISHBONE Image3 Translation Address reg */
141	uint32 W_IMG_CTRL4;		/* 0x1B4 32 R/W WISHBONE Image4 Control register */
142	uint32 W_BA4;			/* 0x1B8 32 R/W WISHBONE Image4 Base Address register */
143	uint32 W_AM4;			/* 0x1BC 32 R/W WISHBONE Image4 Address Mask register */
144	uint32 W_TA4;			/* 0x1C0 32 R/W WISHBONE Image4 Translation Address reg */
145	uint32 W_IMG_CTRL5;		/* 0x1C4 32 R/W WISHBONE Image5 Control register */
146	uint32 W_BA5;			/* 0x1C8 32 R/W WISHBONE Image5 Base Address register */
147	uint32 W_AM5;			/* 0x1CC 32 R/W WISHBONE Image5 Address Mask register */
148	uint32 W_TA5;			/* 0x1D0 32 R/W WISHBONE Image5 Translation Address reg */
149	uint32 W_ERR_CS;		/* 0x1D4 32 R/W WISHBONE Error Control and Status reg */
150	uint32 W_ERR_ADDR;		/* 0x1D8 32 R WISHBONE Erroneous Address register */
151	uint32 W_ERR_DATA;		/* 0x1DC 32 R WISHBONE Erroneous Data register */
152	uint32 CNF_ADDR;		/* 0x1E0 32 R/W Configuration Cycle register */
153	uint32 CNF_DATA;		/* 0x1E4 32 R/W Configuration Cycle Generation Data reg */
154
155	uint32 INT_ACK;			/* 0x1E8 32 R Interrupt Acknowledge register */
156	uint32 ICR;			/* 0x1EC 32 R/W Interrupt Control register */
157	uint32 ISR;			/* 0x1F0 32 R/W Interrupt Status register */
158} spih_pciregs_t;
159
160/*
161 * PCI Core interrupt enable and status bit definitions.
162 */
163
164/* PCI Core ICR Register bit definitions */
165#define PCI_INT_PROP_EN		(1 << 0)	/* Interrupt Propagation Enable */
166#define PCI_WB_ERR_INT_EN	(1 << 1)	/* Wishbone Error Interrupt Enable */
167#define PCI_PCI_ERR_INT_EN	(1 << 2)	/* PCI Error Interrupt Enable */
168#define PCI_PAR_ERR_INT_EN	(1 << 3)	/* Parity Error Interrupt Enable */
169#define PCI_SYS_ERR_INT_EN	(1 << 4)	/* System Error Interrupt Enable */
170#define PCI_SOFTWARE_RESET	(1U << 31)	/* Software reset of the PCI Core. */
171
172
173/* PCI Core ISR Register bit definitions */
174#define PCI_INT_PROP_ST		(1 << 0)	/* Interrupt Propagation Status */
175#define PCI_WB_ERR_INT_ST	(1 << 1)	/* Wishbone Error Interrupt Status */
176#define PCI_PCI_ERR_INT_ST	(1 << 2)	/* PCI Error Interrupt Status */
177#define PCI_PAR_ERR_INT_ST	(1 << 3)	/* Parity Error Interrupt Status */
178#define PCI_SYS_ERR_INT_ST	(1 << 4)	/* System Error Interrupt Status */
179
180
181/* Registers on the Wishbone bus */
182#define SPIH_CTLR_INTR		(1 << 0)	/* SPI Host Controller Core Interrupt */
183#define SPIH_DEV_INTR		(1 << 1)	/* SPI Device Interrupt */
184#define SPIH_WFIFO_INTR		(1 << 2)	/* SPI Tx FIFO Empty Intr (FPGA Rev >= 8) */
185
186/* GPIO Bit definitions */
187#define SPIH_CS				(1 << 0)	/* SPI Chip Select (active low) */
188#define SPIH_SLOT_POWER		(1 << 1)	/* SD Card Slot Power Enable */
189#define SPIH_CARD_DETECT	(1 << 2)	/* SD Card Detect */
190
191/* SPI Status Register Bit definitions */
192#define SPIH_STATE_MASK		0x30		/* SPI Transfer State Machine state mask */
193#define SPIH_STATE_SHIFT	4		/* SPI Transfer State Machine state shift */
194#define SPIH_WFFULL			(1 << 3)	/* SPI Write FIFO Full */
195#define SPIH_WFEMPTY		(1 << 2)	/* SPI Write FIFO Empty */
196#define SPIH_RFFULL			(1 << 1)	/* SPI Read FIFO Full */
197#define SPIH_RFEMPTY		(1 << 0)	/* SPI Read FIFO Empty */
198
199#define SPIH_EXT_CLK		(1U << 31)	/* Use External Clock as PLL Clock source. */
200
201#define SPIH_PLL_NO_CLK		(1 << 1)	/* Set to 1 if the PLL's input clock is lost. */
202#define SPIH_PLL_LOCKED		(1 << 3)	/* Set to 1 when the PLL is locked. */
203
204/* Spin bit loop bound check */
205#define SPI_SPIN_BOUND		0xf4240		/* 1 million */