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/drivers/net/wireless/ath/ath5k/reg.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
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   1/*
   2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
   3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
   5 *
   6 * Permission to use, copy, modify, and distribute this software for any
   7 * purpose with or without fee is hereby granted, provided that the above
   8 * copyright notice and this permission notice appear in all copies.
   9 *
  10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17 *
  18 */
  19
  20/*
  21 * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k
  22 * maintained by Reyk Floeter
  23 *
  24 * I tried to document those registers by looking at ar5k code, some
  25 * 802.11 (802.11e mostly) papers and by reading various public available
  26 * Atheros presentations and papers like these:
  27 *
  28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
  29 *
  30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
  31 *
  32 * This file also contains register values found on a memory dump of
  33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
  34 * released by Atheros and on various debug messages found on the net.
  35 */
  36
  37#include "../reg.h"
  38
  39/*====MAC DMA REGISTERS====*/
  40
  41/*
  42 * AR5210-Specific TXDP registers
  43 * 5210 has only 2 transmit queues so no DCU/QCU, just
  44 * 2 transmit descriptor pointers...
  45 */
  46#define AR5K_NOQCU_TXDP0	0x0000		/* Queue 0 - data */
  47#define AR5K_NOQCU_TXDP1	0x0004		/* Queue 1 - beacons */
  48
  49/*
  50 * Mac Control Register
  51 */
  52#define	AR5K_CR		0x0008			/* Register Address */
  53#define AR5K_CR_TXE0	0x00000001	/* TX Enable for queue 0 on 5210 */
  54#define AR5K_CR_TXE1	0x00000002	/* TX Enable for queue 1 on 5210 */
  55#define	AR5K_CR_RXE	0x00000004	/* RX Enable */
  56#define AR5K_CR_TXD0	0x00000008	/* TX Disable for queue 0 on 5210 */
  57#define AR5K_CR_TXD1	0x00000010	/* TX Disable for queue 1 on 5210 */
  58#define	AR5K_CR_RXD	0x00000020	/* RX Disable */
  59#define	AR5K_CR_SWI	0x00000040	/* Software Interrupt */
  60
  61/*
  62 * RX Descriptor Pointer register
  63 */
  64#define	AR5K_RXDP	0x000c
  65
  66/*
  67 * Configuration and status register
  68 */
  69#define	AR5K_CFG		0x0014			/* Register Address */
  70#define	AR5K_CFG_SWTD		0x00000001	/* Byte-swap TX descriptor (for big endian archs) */
  71#define	AR5K_CFG_SWTB		0x00000002	/* Byte-swap TX buffer */
  72#define	AR5K_CFG_SWRD		0x00000004	/* Byte-swap RX descriptor */
  73#define	AR5K_CFG_SWRB		0x00000008	/* Byte-swap RX buffer */
  74#define	AR5K_CFG_SWRG		0x00000010	/* Byte-swap Register access */
  75#define AR5K_CFG_IBSS		0x00000020	/* 0-BSS, 1-IBSS [5211+] */
  76#define AR5K_CFG_PHY_OK		0x00000100	/* [5211+] */
  77#define AR5K_CFG_EEBS		0x00000200	/* EEPROM is busy */
  78#define	AR5K_CFG_CLKGD		0x00000400	/* Clock gated (Disable dynamic clock) */
  79#define AR5K_CFG_TXCNT		0x00007800	/* Tx frame count (?) [5210] */
  80#define AR5K_CFG_TXCNT_S	11
  81#define AR5K_CFG_TXFSTAT	0x00008000	/* Tx frame status (?) [5210] */
  82#define AR5K_CFG_TXFSTRT	0x00010000	/* [5210] */
  83#define	AR5K_CFG_PCI_THRES	0x00060000	/* PCI Master req q threshold [5211+] */
  84#define	AR5K_CFG_PCI_THRES_S	17
  85
  86/*
  87 * Interrupt enable register
  88 */
  89#define AR5K_IER		0x0024		/* Register Address */
  90#define AR5K_IER_DISABLE	0x00000000	/* Disable card interrupts */
  91#define AR5K_IER_ENABLE		0x00000001	/* Enable card interrupts */
  92
  93
  94/*
  95 * 0x0028 is Beacon Control Register on 5210
  96 * and first RTS duration register on 5211
  97 */
  98
  99/*
 100 * Beacon control register [5210]
 101 */
 102#define AR5K_BCR		0x0028		/* Register Address */
 103#define AR5K_BCR_AP		0x00000000	/* AP mode */
 104#define AR5K_BCR_ADHOC		0x00000001	/* Ad-Hoc mode */
 105#define AR5K_BCR_BDMAE		0x00000002	/* DMA enable */
 106#define AR5K_BCR_TQ1FV		0x00000004	/* Use Queue1 for CAB traffic */
 107#define AR5K_BCR_TQ1V		0x00000008	/* Use Queue1 for Beacon traffic */
 108#define AR5K_BCR_BCGET		0x00000010
 109
 110/*
 111 * First RTS duration register [5211]
 112 */
 113#define AR5K_RTSD0		0x0028		/* Register Address */
 114#define	AR5K_RTSD0_6		0x000000ff	/* 6Mb RTS duration mask (?) */
 115#define	AR5K_RTSD0_6_S		0		/* 6Mb RTS duration shift (?) */
 116#define	AR5K_RTSD0_9		0x0000ff00	/* 9Mb*/
 117#define	AR5K_RTSD0_9_S		8
 118#define	AR5K_RTSD0_12		0x00ff0000	/* 12Mb*/
 119#define	AR5K_RTSD0_12_S		16
 120#define	AR5K_RTSD0_18		0xff000000	/* 16Mb*/
 121#define	AR5K_RTSD0_18_S		24
 122
 123
 124/*
 125 * 0x002c is Beacon Status Register on 5210
 126 * and second RTS duration register on 5211
 127 */
 128
 129/*
 130 * Beacon status register [5210]
 131 *
 132 * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR
 133 * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning
 134 * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR).
 135 * So SNAPPEDBCRVALID should also stand for "snapped BCR -values- valid", so i
 136 * renamed it to SNAPSHOTSVALID to make more sense. I really have no idea what
 137 * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR.
 138 */
 139#define AR5K_BSR		0x002c			/* Register Address */
 140#define AR5K_BSR_BDLYSW		0x00000001	/* SW Beacon delay (?) */
 141#define AR5K_BSR_BDLYDMA	0x00000002	/* DMA Beacon delay (?) */
 142#define AR5K_BSR_TXQ1F		0x00000004	/* Beacon queue (1) finished */
 143#define AR5K_BSR_ATIMDLY	0x00000008	/* ATIM delay (?) */
 144#define AR5K_BSR_SNPADHOC	0x00000100	/* Ad-hoc mode set (?) */
 145#define AR5K_BSR_SNPBDMAE	0x00000200	/* Beacon DMA enabled (?) */
 146#define AR5K_BSR_SNPTQ1FV	0x00000400	/* Queue1 is used for CAB traffic (?) */
 147#define AR5K_BSR_SNPTQ1V	0x00000800	/* Queue1 is used for Beacon traffic (?) */
 148#define AR5K_BSR_SNAPSHOTSVALID	0x00001000	/* BCR snapshots are valid (?) */
 149#define AR5K_BSR_SWBA_CNT	0x00ff0000
 150
 151/*
 152 * Second RTS duration register [5211]
 153 */
 154#define AR5K_RTSD1		0x002c			/* Register Address */
 155#define	AR5K_RTSD1_24		0x000000ff	/* 24Mb */
 156#define	AR5K_RTSD1_24_S		0
 157#define	AR5K_RTSD1_36		0x0000ff00	/* 36Mb */
 158#define	AR5K_RTSD1_36_S		8
 159#define	AR5K_RTSD1_48		0x00ff0000	/* 48Mb */
 160#define	AR5K_RTSD1_48_S		16
 161#define	AR5K_RTSD1_54		0xff000000	/* 54Mb */
 162#define	AR5K_RTSD1_54_S		24
 163
 164
 165/*
 166 * Transmit configuration register
 167 */
 168#define AR5K_TXCFG			0x0030			/* Register Address */
 169#define AR5K_TXCFG_SDMAMR		0x00000007	/* DMA size (read) */
 170#define AR5K_TXCFG_SDMAMR_S		0
 171#define AR5K_TXCFG_B_MODE		0x00000008	/* Set b mode for 5111 (enable 2111) */
 172#define AR5K_TXCFG_TXFSTP		0x00000008	/* TX DMA full Stop [5210] */
 173#define AR5K_TXCFG_TXFULL		0x000003f0	/* TX Trigger level mask */
 174#define AR5K_TXCFG_TXFULL_S		4
 175#define AR5K_TXCFG_TXFULL_0B		0x00000000
 176#define AR5K_TXCFG_TXFULL_64B		0x00000010
 177#define AR5K_TXCFG_TXFULL_128B		0x00000020
 178#define AR5K_TXCFG_TXFULL_192B		0x00000030
 179#define AR5K_TXCFG_TXFULL_256B		0x00000040
 180#define AR5K_TXCFG_TXCONT_EN		0x00000080
 181#define AR5K_TXCFG_DMASIZE		0x00000100	/* Flag for passing DMA size [5210] */
 182#define AR5K_TXCFG_JUMBO_DESC_EN	0x00000400	/* Enable jumbo tx descriptors [5211+] */
 183#define AR5K_TXCFG_ADHOC_BCN_ATIM	0x00000800	/* Adhoc Beacon ATIM Policy */
 184#define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS	0x00001000	/* Disable ATIM window defer [5211+] */
 185#define AR5K_TXCFG_RTSRND		0x00001000	/* [5211+] */
 186#define AR5K_TXCFG_FRMPAD_DIS		0x00002000	/* [5211+] */
 187#define AR5K_TXCFG_RDY_CBR_DIS		0x00004000	/* Ready time CBR disable [5211+] */
 188#define AR5K_TXCFG_JUMBO_FRM_MODE	0x00008000	/* Jumbo frame mode [5211+] */
 189#define	AR5K_TXCFG_DCU_DBL_BUF_DIS	0x00008000	/* Disable double buffering on DCU */
 190#define AR5K_TXCFG_DCU_CACHING_DIS	0x00010000	/* Disable DCU caching */
 191
 192/*
 193 * Receive configuration register
 194 */
 195#define AR5K_RXCFG		0x0034			/* Register Address */
 196#define AR5K_RXCFG_SDMAMW	0x00000007	/* DMA size (write) */
 197#define AR5K_RXCFG_SDMAMW_S	0
 198#define AR5K_RXCFG_ZLFDMA	0x00000008	/* Enable Zero-length frame DMA */
 199#define	AR5K_RXCFG_DEF_ANTENNA	0x00000010	/* Default antenna (?) */
 200#define AR5K_RXCFG_JUMBO_RXE	0x00000020	/* Enable jumbo rx descriptors [5211+] */
 201#define AR5K_RXCFG_JUMBO_WRAP	0x00000040	/* Wrap jumbo frames [5211+] */
 202#define AR5K_RXCFG_SLE_ENTRY	0x00000080	/* Sleep entry policy */
 203
 204/*
 205 * Receive jumbo descriptor last address register
 206 * Only found in 5211 (?)
 207 */
 208#define AR5K_RXJLA		0x0038
 209
 210/*
 211 * MIB control register
 212 */
 213#define AR5K_MIBC		0x0040			/* Register Address */
 214#define AR5K_MIBC_COW		0x00000001	/* Counter Overflow Warning */
 215#define AR5K_MIBC_FMC		0x00000002	/* Freeze MIB Counters  */
 216#define AR5K_MIBC_CMC		0x00000004	/* Clear MIB Counters  */
 217#define AR5K_MIBC_MCS		0x00000008	/* MIB counter strobe, increment all */
 218
 219/*
 220 * Timeout prescale register
 221 */
 222#define AR5K_TOPS		0x0044
 223#define	AR5K_TOPS_M		0x0000ffff
 224
 225/*
 226 * Receive timeout register (no frame received)
 227 */
 228#define AR5K_RXNOFRM		0x0048
 229#define	AR5K_RXNOFRM_M		0x000003ff
 230
 231/*
 232 * Transmit timeout register (no frame sent)
 233 */
 234#define AR5K_TXNOFRM		0x004c
 235#define	AR5K_TXNOFRM_M		0x000003ff
 236#define	AR5K_TXNOFRM_QCU	0x000ffc00
 237#define	AR5K_TXNOFRM_QCU_S	10
 238
 239/*
 240 * Receive frame gap timeout register
 241 */
 242#define AR5K_RPGTO		0x0050
 243#define AR5K_RPGTO_M		0x000003ff
 244
 245/*
 246 * Receive frame count limit register
 247 */
 248#define AR5K_RFCNT		0x0054
 249#define AR5K_RFCNT_M		0x0000001f	/* [5211+] (?) */
 250#define AR5K_RFCNT_RFCL		0x0000000f	/* [5210] */
 251
 252/*
 253 * Misc settings register
 254 * (reserved0-3)
 255 */
 256#define AR5K_MISC		0x0058			/* Register Address */
 257#define	AR5K_MISC_DMA_OBS_M	0x000001e0
 258#define	AR5K_MISC_DMA_OBS_S	5
 259#define	AR5K_MISC_MISC_OBS_M	0x00000e00
 260#define	AR5K_MISC_MISC_OBS_S	9
 261#define	AR5K_MISC_MAC_OBS_LSB_M	0x00007000
 262#define	AR5K_MISC_MAC_OBS_LSB_S	12
 263#define	AR5K_MISC_MAC_OBS_MSB_M	0x00038000
 264#define	AR5K_MISC_MAC_OBS_MSB_S	15
 265#define AR5K_MISC_LED_DECAY	0x001c0000	/* [5210] */
 266#define AR5K_MISC_LED_BLINK	0x00e00000	/* [5210] */
 267
 268/*
 269 * QCU/DCU clock gating register (5311)
 270 * (reserved4-5)
 271 */
 272#define	AR5K_QCUDCU_CLKGT	0x005c			/* Register Address (?) */
 273#define	AR5K_QCUDCU_CLKGT_QCU	0x0000ffff	/* Mask for QCU clock */
 274#define	AR5K_QCUDCU_CLKGT_DCU	0x07ff0000	/* Mask for DCU clock */
 275
 276/*
 277 * Interrupt Status Registers
 278 *
 279 * For 5210 there is only one status register but for
 280 * 5211/5212 we have one primary and 4 secondary registers.
 281 * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212.
 282 * Most of these bits are common for all chipsets.
 283 */
 284#define AR5K_ISR		0x001c			/* Register Address [5210] */
 285#define AR5K_PISR		0x0080			/* Register Address [5211+] */
 286#define AR5K_ISR_RXOK		0x00000001	/* Frame successfully received */
 287#define AR5K_ISR_RXDESC		0x00000002	/* RX descriptor request */
 288#define AR5K_ISR_RXERR		0x00000004	/* Receive error */
 289#define AR5K_ISR_RXNOFRM	0x00000008	/* No frame received (receive timeout) */
 290#define AR5K_ISR_RXEOL		0x00000010	/* Empty RX descriptor */
 291#define AR5K_ISR_RXORN		0x00000020	/* Receive FIFO overrun */
 292#define AR5K_ISR_TXOK		0x00000040	/* Frame successfully transmitted */
 293#define AR5K_ISR_TXDESC		0x00000080	/* TX descriptor request */
 294#define AR5K_ISR_TXERR		0x00000100	/* Transmit error */
 295#define AR5K_ISR_TXNOFRM	0x00000200	/* No frame transmitted (transmit timeout) */
 296#define AR5K_ISR_TXEOL		0x00000400	/* Empty TX descriptor */
 297#define AR5K_ISR_TXURN		0x00000800	/* Transmit FIFO underrun */
 298#define AR5K_ISR_MIB		0x00001000	/* Update MIB counters */
 299#define AR5K_ISR_SWI		0x00002000	/* Software interrupt */
 300#define AR5K_ISR_RXPHY		0x00004000	/* PHY error */
 301#define AR5K_ISR_RXKCM		0x00008000	/* RX Key cache miss */
 302#define AR5K_ISR_SWBA		0x00010000	/* Software beacon alert */
 303#define AR5K_ISR_BRSSI		0x00020000	/* Beacon rssi below threshold (?) */
 304#define AR5K_ISR_BMISS		0x00040000	/* Beacon missed */
 305#define AR5K_ISR_HIUERR		0x00080000	/* Host Interface Unit error [5211+] */
 306#define AR5K_ISR_BNR		0x00100000	/* Beacon not ready [5211+] */
 307#define AR5K_ISR_MCABT		0x00100000	/* Master Cycle Abort [5210] */
 308#define AR5K_ISR_RXCHIRP	0x00200000	/* CHIRP Received [5212+] */
 309#define AR5K_ISR_SSERR		0x00200000	/* Signaled System Error [5210] */
 310#define AR5K_ISR_DPERR		0x00400000	/* Det par Error (?) [5210] */
 311#define AR5K_ISR_RXDOPPLER	0x00400000	/* Doppler chirp received [5212+] */
 312#define AR5K_ISR_TIM		0x00800000	/* [5211+] */
 313#define AR5K_ISR_BCNMISC	0x00800000	/* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
 314						CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
 315#define AR5K_ISR_GPIO		0x01000000	/* GPIO (rf kill) */
 316#define AR5K_ISR_QCBRORN	0x02000000	/* QCU CBR overrun [5211+] */
 317#define AR5K_ISR_QCBRURN	0x04000000	/* QCU CBR underrun [5211+] */
 318#define AR5K_ISR_QTRIG		0x08000000	/* QCU scheduling trigger [5211+] */
 319
 320/*
 321 * Secondary status registers [5211+] (0 - 4)
 322 *
 323 * These give the status for each QCU, only QCUs 0-9 are
 324 * represented.
 325 */
 326#define AR5K_SISR0		0x0084			/* Register Address [5211+] */
 327#define AR5K_SISR0_QCU_TXOK	0x000003ff	/* Mask for QCU_TXOK */
 328#define AR5K_SISR0_QCU_TXOK_S	0
 329#define AR5K_SISR0_QCU_TXDESC	0x03ff0000	/* Mask for QCU_TXDESC */
 330#define AR5K_SISR0_QCU_TXDESC_S	16
 331
 332#define AR5K_SISR1		0x0088			/* Register Address [5211+] */
 333#define AR5K_SISR1_QCU_TXERR	0x000003ff	/* Mask for QCU_TXERR */
 334#define AR5K_SISR1_QCU_TXERR_S	0
 335#define AR5K_SISR1_QCU_TXEOL	0x03ff0000	/* Mask for QCU_TXEOL */
 336#define AR5K_SISR1_QCU_TXEOL_S	16
 337
 338#define AR5K_SISR2		0x008c			/* Register Address [5211+] */
 339#define AR5K_SISR2_QCU_TXURN	0x000003ff	/* Mask for QCU_TXURN */
 340#define	AR5K_SISR2_QCU_TXURN_S	0
 341#define	AR5K_SISR2_MCABT	0x00010000	/* Master Cycle Abort */
 342#define	AR5K_SISR2_SSERR	0x00020000	/* Signaled System Error */
 343#define	AR5K_SISR2_DPERR	0x00040000	/* Bus parity error */
 344#define	AR5K_SISR2_TIM		0x01000000	/* [5212+] */
 345#define	AR5K_SISR2_CAB_END	0x02000000	/* [5212+] */
 346#define	AR5K_SISR2_DTIM_SYNC	0x04000000	/* DTIM sync lost [5212+] */
 347#define	AR5K_SISR2_BCN_TIMEOUT	0x08000000	/* Beacon Timeout [5212+] */
 348#define	AR5K_SISR2_CAB_TIMEOUT	0x10000000	/* CAB Timeout [5212+] */
 349#define	AR5K_SISR2_DTIM		0x20000000	/* [5212+] */
 350#define	AR5K_SISR2_TSFOOR	0x80000000	/* TSF OOR (?) */
 351
 352#define AR5K_SISR3		0x0090			/* Register Address [5211+] */
 353#define AR5K_SISR3_QCBRORN	0x000003ff	/* Mask for QCBRORN */
 354#define AR5K_SISR3_QCBRORN_S	0
 355#define AR5K_SISR3_QCBRURN	0x03ff0000	/* Mask for QCBRURN */
 356#define AR5K_SISR3_QCBRURN_S	16
 357
 358#define AR5K_SISR4		0x0094			/* Register Address [5211+] */
 359#define AR5K_SISR4_QTRIG	0x000003ff	/* Mask for QTRIG */
 360#define AR5K_SISR4_QTRIG_S	0
 361
 362/*
 363 * Shadow read-and-clear interrupt status registers [5211+]
 364 */
 365#define AR5K_RAC_PISR		0x00c0		/* Read and clear PISR */
 366#define AR5K_RAC_SISR0		0x00c4		/* Read and clear SISR0 */
 367#define AR5K_RAC_SISR1		0x00c8		/* Read and clear SISR1 */
 368#define AR5K_RAC_SISR2		0x00cc		/* Read and clear SISR2 */
 369#define AR5K_RAC_SISR3		0x00d0		/* Read and clear SISR3 */
 370#define AR5K_RAC_SISR4		0x00d4		/* Read and clear SISR4 */
 371
 372/*
 373 * Interrupt Mask Registers
 374 *
 375 * As with ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary
 376 * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match.
 377 */
 378#define	AR5K_IMR		0x0020			/* Register Address [5210] */
 379#define AR5K_PIMR		0x00a0			/* Register Address [5211+] */
 380#define AR5K_IMR_RXOK		0x00000001	/* Frame successfully received*/
 381#define AR5K_IMR_RXDESC		0x00000002	/* RX descriptor request*/
 382#define AR5K_IMR_RXERR		0x00000004	/* Receive error*/
 383#define AR5K_IMR_RXNOFRM	0x00000008	/* No frame received (receive timeout)*/
 384#define AR5K_IMR_RXEOL		0x00000010	/* Empty RX descriptor*/
 385#define AR5K_IMR_RXORN		0x00000020	/* Receive FIFO overrun*/
 386#define AR5K_IMR_TXOK		0x00000040	/* Frame successfully transmitted*/
 387#define AR5K_IMR_TXDESC		0x00000080	/* TX descriptor request*/
 388#define AR5K_IMR_TXERR		0x00000100	/* Transmit error*/
 389#define AR5K_IMR_TXNOFRM	0x00000200	/* No frame transmitted (transmit timeout)*/
 390#define AR5K_IMR_TXEOL		0x00000400	/* Empty TX descriptor*/
 391#define AR5K_IMR_TXURN		0x00000800	/* Transmit FIFO underrun*/
 392#define AR5K_IMR_MIB		0x00001000	/* Update MIB counters*/
 393#define AR5K_IMR_SWI		0x00002000	/* Software interrupt */
 394#define AR5K_IMR_RXPHY		0x00004000	/* PHY error*/
 395#define AR5K_IMR_RXKCM		0x00008000	/* RX Key cache miss */
 396#define AR5K_IMR_SWBA		0x00010000	/* Software beacon alert*/
 397#define AR5K_IMR_BRSSI		0x00020000	/* Beacon rssi below threshold (?) */
 398#define AR5K_IMR_BMISS		0x00040000	/* Beacon missed*/
 399#define AR5K_IMR_HIUERR		0x00080000	/* Host Interface Unit error [5211+] */
 400#define AR5K_IMR_BNR		0x00100000	/* Beacon not ready [5211+] */
 401#define AR5K_IMR_MCABT		0x00100000	/* Master Cycle Abort [5210] */
 402#define AR5K_IMR_RXCHIRP	0x00200000	/* CHIRP Received [5212+]*/
 403#define AR5K_IMR_SSERR		0x00200000	/* Signaled System Error [5210] */
 404#define AR5K_IMR_DPERR		0x00400000	/* Det par Error (?) [5210] */
 405#define AR5K_IMR_RXDOPPLER	0x00400000	/* Doppler chirp received [5212+] */
 406#define AR5K_IMR_TIM		0x00800000	/* [5211+] */
 407#define AR5K_IMR_BCNMISC	0x00800000	/* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
 408						CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
 409#define AR5K_IMR_GPIO		0x01000000	/* GPIO (rf kill)*/
 410#define AR5K_IMR_QCBRORN	0x02000000	/* QCU CBR overrun (?) [5211+] */
 411#define AR5K_IMR_QCBRURN	0x04000000	/* QCU CBR underrun (?) [5211+] */
 412#define AR5K_IMR_QTRIG		0x08000000	/* QCU scheduling trigger [5211+] */
 413
 414/*
 415 * Secondary interrupt mask registers [5211+] (0 - 4)
 416 */
 417#define AR5K_SIMR0		0x00a4			/* Register Address [5211+] */
 418#define AR5K_SIMR0_QCU_TXOK	0x000003ff	/* Mask for QCU_TXOK */
 419#define AR5K_SIMR0_QCU_TXOK_S	0
 420#define AR5K_SIMR0_QCU_TXDESC	0x03ff0000	/* Mask for QCU_TXDESC */
 421#define AR5K_SIMR0_QCU_TXDESC_S	16
 422
 423#define AR5K_SIMR1		0x00a8			/* Register Address [5211+] */
 424#define AR5K_SIMR1_QCU_TXERR	0x000003ff	/* Mask for QCU_TXERR */
 425#define AR5K_SIMR1_QCU_TXERR_S	0
 426#define AR5K_SIMR1_QCU_TXEOL	0x03ff0000	/* Mask for QCU_TXEOL */
 427#define AR5K_SIMR1_QCU_TXEOL_S	16
 428
 429#define AR5K_SIMR2		0x00ac			/* Register Address [5211+] */
 430#define AR5K_SIMR2_QCU_TXURN	0x000003ff	/* Mask for QCU_TXURN */
 431#define AR5K_SIMR2_QCU_TXURN_S	0
 432#define	AR5K_SIMR2_MCABT	0x00010000	/* Master Cycle Abort */
 433#define	AR5K_SIMR2_SSERR	0x00020000	/* Signaled System Error */
 434#define	AR5K_SIMR2_DPERR	0x00040000	/* Bus parity error */
 435#define	AR5K_SIMR2_TIM		0x01000000	/* [5212+] */
 436#define	AR5K_SIMR2_CAB_END	0x02000000	/* [5212+] */
 437#define	AR5K_SIMR2_DTIM_SYNC	0x04000000	/* DTIM Sync lost [5212+] */
 438#define	AR5K_SIMR2_BCN_TIMEOUT	0x08000000	/* Beacon Timeout [5212+] */
 439#define	AR5K_SIMR2_CAB_TIMEOUT	0x10000000	/* CAB Timeout [5212+] */
 440#define	AR5K_SIMR2_DTIM		0x20000000	/* [5212+] */
 441#define	AR5K_SIMR2_TSFOOR	0x80000000	/* TSF OOR (?) */
 442
 443#define AR5K_SIMR3		0x00b0			/* Register Address [5211+] */
 444#define AR5K_SIMR3_QCBRORN	0x000003ff	/* Mask for QCBRORN */
 445#define AR5K_SIMR3_QCBRORN_S	0
 446#define AR5K_SIMR3_QCBRURN	0x03ff0000	/* Mask for QCBRURN */
 447#define AR5K_SIMR3_QCBRURN_S	16
 448
 449#define AR5K_SIMR4		0x00b4			/* Register Address [5211+] */
 450#define AR5K_SIMR4_QTRIG	0x000003ff	/* Mask for QTRIG */
 451#define AR5K_SIMR4_QTRIG_S	0
 452
 453/*
 454 * DMA Debug registers 0-7
 455 * 0xe0 - 0xfc
 456 */
 457
 458/*
 459 * Decompression mask registers [5212+]
 460 */
 461#define AR5K_DCM_ADDR		0x0400		/*Decompression mask address (index) */
 462#define AR5K_DCM_DATA		0x0404		/*Decompression mask data */
 463
 464/*
 465 * Wake On Wireless pattern control register [5212+]
 466 */
 467#define	AR5K_WOW_PCFG			0x0410			/* Register Address */
 468#define	AR5K_WOW_PCFG_PAT_MATCH_EN	0x00000001	/* Pattern match enable */
 469#define	AR5K_WOW_PCFG_LONG_FRAME_POL	0x00000002	/* Long frame policy */
 470#define	AR5K_WOW_PCFG_WOBMISS		0x00000004	/* Wake on bea(con) miss (?) */
 471#define	AR5K_WOW_PCFG_PAT_0_EN		0x00000100	/* Enable pattern 0 */
 472#define	AR5K_WOW_PCFG_PAT_1_EN		0x00000200	/* Enable pattern 1 */
 473#define	AR5K_WOW_PCFG_PAT_2_EN		0x00000400	/* Enable pattern 2 */
 474#define	AR5K_WOW_PCFG_PAT_3_EN		0x00000800	/* Enable pattern 3 */
 475#define	AR5K_WOW_PCFG_PAT_4_EN		0x00001000	/* Enable pattern 4 */
 476#define	AR5K_WOW_PCFG_PAT_5_EN		0x00002000	/* Enable pattern 5 */
 477
 478/*
 479 * Wake On Wireless pattern index register (?) [5212+]
 480 */
 481#define	AR5K_WOW_PAT_IDX	0x0414
 482
 483/*
 484 * Wake On Wireless pattern data register [5212+]
 485 */
 486#define	AR5K_WOW_PAT_DATA	0x0418			/* Register Address */
 487#define	AR5K_WOW_PAT_DATA_0_3_V	0x00000001	/* Pattern 0, 3 value */
 488#define	AR5K_WOW_PAT_DATA_1_4_V	0x00000100	/* Pattern 1, 4 value */
 489#define	AR5K_WOW_PAT_DATA_2_5_V	0x00010000	/* Pattern 2, 5 value */
 490#define	AR5K_WOW_PAT_DATA_0_3_M	0x01000000	/* Pattern 0, 3 mask */
 491#define	AR5K_WOW_PAT_DATA_1_4_M	0x04000000	/* Pattern 1, 4 mask */
 492#define	AR5K_WOW_PAT_DATA_2_5_M	0x10000000	/* Pattern 2, 5 mask */
 493
 494/*
 495 * Decompression configuration registers [5212+]
 496 */
 497#define AR5K_DCCFG		0x0420			/* Register Address */
 498#define AR5K_DCCFG_GLOBAL_EN	0x00000001	/* Enable decompression on all queues */
 499#define AR5K_DCCFG_BYPASS_EN	0x00000002	/* Bypass decompression */
 500#define AR5K_DCCFG_BCAST_EN	0x00000004	/* Enable decompression for bcast frames */
 501#define AR5K_DCCFG_MCAST_EN	0x00000008	/* Enable decompression for mcast frames */
 502
 503/*
 504 * Compression configuration registers [5212+]
 505 */
 506#define AR5K_CCFG		0x0600			/* Register Address */
 507#define	AR5K_CCFG_WINDOW_SIZE	0x00000007	/* Compression window size */
 508#define	AR5K_CCFG_CPC_EN	0x00000008	/* Enable performance counters */
 509
 510#define AR5K_CCFG_CCU		0x0604			/* Register Address */
 511#define AR5K_CCFG_CCU_CUP_EN	0x00000001	/* CCU Catchup enable */
 512#define AR5K_CCFG_CCU_CREDIT	0x00000002	/* CCU Credit (field) */
 513#define AR5K_CCFG_CCU_CD_THRES	0x00000080	/* CCU Cyc(lic?) debt threshold (field) */
 514#define AR5K_CCFG_CCU_CUP_LCNT	0x00010000	/* CCU Catchup lit(?) count */
 515#define	AR5K_CCFG_CCU_INIT	0x00100200	/* Initial value during reset */
 516
 517/*
 518 * Compression performance counter registers [5212+]
 519 */
 520#define AR5K_CPC0		0x0610		/* Compression performance counter 0 */
 521#define AR5K_CPC1		0x0614		/* Compression performance counter 1*/
 522#define AR5K_CPC2		0x0618		/* Compression performance counter 2 */
 523#define AR5K_CPC3		0x061c		/* Compression performance counter 3 */
 524#define AR5K_CPCOVF		0x0620		/* Compression performance overflow */
 525
 526
 527/*
 528 * Queue control unit (QCU) registers [5211+]
 529 *
 530 * Card has 12 TX Queues but i see that only 0-9 are used (?)
 531 * both in binary HAL (see ah.h) and ar5k. Each queue has it's own
 532 * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
 533 * configuration register (0x08c0 - 0x08ec), a ready time configuration
 534 * register (0x0900 - 0x092c), a misc configuration register (0x09c0 -
 535 * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some
 536 * global registers, QCU transmit enable/disable and "one shot arm (?)"
 537 * set/clear, which contain status for all queues (we shift by 1 for each
 538 * queue). To access these registers easily we define some macros here
 539 * that are used inside HAL. For more infos check out *_tx_queue functs.
 540 */
 541
 542/*
 543 * Generic QCU Register access macros
 544 */
 545#define	AR5K_QUEUE_REG(_r, _q)		(((_q) << 2) + _r)
 546#define AR5K_QCU_GLOBAL_READ(_r, _q)	(AR5K_REG_READ(_r) & (1 << _q))
 547#define AR5K_QCU_GLOBAL_WRITE(_r, _q)	AR5K_REG_WRITE(_r, (1 << _q))
 548
 549/*
 550 * QCU Transmit descriptor pointer registers
 551 */
 552#define AR5K_QCU_TXDP_BASE	0x0800		/* Register Address - Queue0 TXDP */
 553#define AR5K_QUEUE_TXDP(_q)	AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)
 554
 555/*
 556 * QCU Transmit enable register
 557 */
 558#define AR5K_QCU_TXE		0x0840
 559#define AR5K_ENABLE_QUEUE(_q)	AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)
 560#define AR5K_QUEUE_ENABLED(_q)	AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)
 561
 562/*
 563 * QCU Transmit disable register
 564 */
 565#define AR5K_QCU_TXD		0x0880
 566#define AR5K_DISABLE_QUEUE(_q)	AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)
 567#define AR5K_QUEUE_DISABLED(_q)	AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)
 568
 569/*
 570 * QCU Constant Bit Rate configuration registers
 571 */
 572#define	AR5K_QCU_CBRCFG_BASE		0x08c0	/* Register Address - Queue0 CBRCFG */
 573#define	AR5K_QCU_CBRCFG_INTVAL		0x00ffffff	/* CBR Interval mask */
 574#define AR5K_QCU_CBRCFG_INTVAL_S	0
 575#define	AR5K_QCU_CBRCFG_ORN_THRES	0xff000000	/* CBR overrun threshold mask */
 576#define AR5K_QCU_CBRCFG_ORN_THRES_S	24
 577#define	AR5K_QUEUE_CBRCFG(_q)		AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)
 578
 579/*
 580 * QCU Ready time configuration registers
 581 */
 582#define	AR5K_QCU_RDYTIMECFG_BASE	0x0900	/* Register Address - Queue0 RDYTIMECFG */
 583#define	AR5K_QCU_RDYTIMECFG_INTVAL	0x00ffffff	/* Ready time interval mask */
 584#define AR5K_QCU_RDYTIMECFG_INTVAL_S	0
 585#define	AR5K_QCU_RDYTIMECFG_ENABLE	0x01000000	/* Ready time enable mask */
 586#define AR5K_QUEUE_RDYTIMECFG(_q)	AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)
 587
 588/*
 589 * QCU one shot arm set registers
 590 */
 591#define	AR5K_QCU_ONESHOTARM_SET		0x0940	/* Register Address -QCU "one shot arm set (?)" */
 592#define	AR5K_QCU_ONESHOTARM_SET_M	0x0000ffff
 593
 594/*
 595 * QCU one shot arm clear registers
 596 */
 597#define	AR5K_QCU_ONESHOTARM_CLEAR	0x0980	/* Register Address -QCU "one shot arm clear (?)" */
 598#define	AR5K_QCU_ONESHOTARM_CLEAR_M	0x0000ffff
 599
 600/*
 601 * QCU misc registers
 602 */
 603#define AR5K_QCU_MISC_BASE		0x09c0			/* Register Address -Queue0 MISC */
 604#define	AR5K_QCU_MISC_FRSHED_M		0x0000000f	/* Frame scheduling mask */
 605#define	AR5K_QCU_MISC_FRSHED_ASAP		0	/* ASAP */
 606#define	AR5K_QCU_MISC_FRSHED_CBR		1	/* Constant Bit Rate */
 607#define	AR5K_QCU_MISC_FRSHED_DBA_GT		2	/* DMA Beacon alert gated */
 608#define	AR5K_QCU_MISC_FRSHED_TIM_GT		3	/* TIMT gated */
 609#define	AR5K_QCU_MISC_FRSHED_BCN_SENT_GT	4	/* Beacon sent gated */
 610#define	AR5K_QCU_MISC_ONESHOT_ENABLE	0x00000010	/* Oneshot enable */
 611#define	AR5K_QCU_MISC_CBREXP_DIS	0x00000020	/* Disable CBR expired counter (normal queue) */
 612#define	AR5K_QCU_MISC_CBREXP_BCN_DIS	0x00000040	/* Disable CBR expired counter (beacon queue) */
 613#define	AR5K_QCU_MISC_BCN_ENABLE	0x00000080	/* Enable Beacon use */
 614#define	AR5K_QCU_MISC_CBR_THRES_ENABLE	0x00000100	/* CBR expired threshold enabled */
 615#define	AR5K_QCU_MISC_RDY_VEOL_POLICY	0x00000200	/* TXE reset when RDYTIME expired or VEOL */
 616#define	AR5K_QCU_MISC_CBR_RESET_CNT	0x00000400	/* CBR threshold (counter) reset */
 617#define	AR5K_QCU_MISC_DCU_EARLY		0x00000800	/* DCU early termination */
 618#define AR5K_QCU_MISC_DCU_CMP_EN	0x00001000	/* Enable frame compression */
 619#define AR5K_QUEUE_MISC(_q)		AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)
 620
 621
 622/*
 623 * QCU status registers
 624 */
 625#define AR5K_QCU_STS_BASE	0x0a00			/* Register Address - Queue0 STS */
 626#define	AR5K_QCU_STS_FRMPENDCNT	0x00000003	/* Frames pending counter */
 627#define	AR5K_QCU_STS_CBREXPCNT	0x0000ff00	/* CBR expired counter */
 628#define	AR5K_QUEUE_STATUS(_q)	AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)
 629
 630/*
 631 * QCU ready time shutdown register
 632 */
 633#define AR5K_QCU_RDYTIMESHDN	0x0a40
 634#define AR5K_QCU_RDYTIMESHDN_M	0x000003ff
 635
 636/*
 637 * QCU compression buffer base registers [5212+]
 638 */
 639#define AR5K_QCU_CBB_SELECT	0x0b00
 640#define AR5K_QCU_CBB_ADDR	0x0b04
 641#define AR5K_QCU_CBB_ADDR_S	9
 642
 643/*
 644 * QCU compression buffer configuration register [5212+]
 645 * (buffer size)
 646 */
 647#define AR5K_QCU_CBCFG		0x0b08
 648
 649
 650
 651/*
 652 * Distributed Coordination Function (DCF) control unit (DCU)
 653 * registers [5211+]
 654 *
 655 * These registers control the various characteristics of each queue
 656 * for 802.11e (WME) compatibility so they go together with
 657 * QCU registers in pairs. For each queue we have a QCU mask register,
 658 * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),
 659 * a retry limit register (0x1080 - 0x10ac), a channel time register
 660 * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and
 661 * a sequence number register (0x1140 - 0x116c). It seems that "global"
 662 * registers here affect all queues (see use of DCU_GBL_IFS_SLOT in ar5k).
 663 * We use the same macros here for easier register access.
 664 *
 665 */
 666
 667/*
 668 * DCU QCU mask registers
 669 */
 670#define AR5K_DCU_QCUMASK_BASE	0x1000		/* Register Address -Queue0 DCU_QCUMASK */
 671#define AR5K_DCU_QCUMASK_M	0x000003ff
 672#define AR5K_QUEUE_QCUMASK(_q)	AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)
 673
 674/*
 675 * DCU local Inter Frame Space settings register
 676 */
 677#define AR5K_DCU_LCL_IFS_BASE		0x1040			/* Register Address -Queue0 DCU_LCL_IFS */
 678#define	AR5K_DCU_LCL_IFS_CW_MIN	        0x000003ff	/* Minimum Contention Window */
 679#define	AR5K_DCU_LCL_IFS_CW_MIN_S	0
 680#define	AR5K_DCU_LCL_IFS_CW_MAX	        0x000ffc00	/* Maximum Contention Window */
 681#define	AR5K_DCU_LCL_IFS_CW_MAX_S	10
 682#define	AR5K_DCU_LCL_IFS_AIFS		0x0ff00000	/* Arbitrated Interframe Space */
 683#define	AR5K_DCU_LCL_IFS_AIFS_S		20
 684#define	AR5K_DCU_LCL_IFS_AIFS_MAX	0xfc		/* Anything above that can cause DCU to hang */
 685#define	AR5K_QUEUE_DFS_LOCAL_IFS(_q)	AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)
 686
 687/*
 688 * DCU retry limit registers
 689 * all these fields don't allow zero values
 690 */
 691#define AR5K_DCU_RETRY_LMT_BASE		0x1080			/* Register Address -Queue0 DCU_RETRY_LMT */
 692#define AR5K_DCU_RETRY_LMT_RTS		0x0000000f	/* RTS failure limit. Transmission fails if no CTS is received for this number of times */
 693#define AR5K_DCU_RETRY_LMT_RTS_S	0
 694#define AR5K_DCU_RETRY_LMT_STA_RTS	0x00003f00	/* STA RTS failure limit. If exceeded CW reset */
 695#define AR5K_DCU_RETRY_LMT_STA_RTS_S	8
 696#define AR5K_DCU_RETRY_LMT_STA_DATA	0x000fc000	/* STA data failure limit. If exceeded CW reset. */
 697#define AR5K_DCU_RETRY_LMT_STA_DATA_S	14
 698#define	AR5K_QUEUE_DFS_RETRY_LIMIT(_q)	AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)
 699
 700/*
 701 * DCU channel time registers
 702 */
 703#define AR5K_DCU_CHAN_TIME_BASE		0x10c0			/* Register Address -Queue0 DCU_CHAN_TIME */
 704#define	AR5K_DCU_CHAN_TIME_DUR		0x000fffff	/* Channel time duration */
 705#define	AR5K_DCU_CHAN_TIME_DUR_S	0
 706#define	AR5K_DCU_CHAN_TIME_ENABLE	0x00100000	/* Enable channel time */
 707#define AR5K_QUEUE_DFS_CHANNEL_TIME(_q)	AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)
 708
 709/*
 710 * DCU misc registers [5211+]
 711 *
 712 * Note: Arbiter lockout control controls the
 713 * behaviour on low priority queues when we have multiple queues
 714 * with pending frames. Intra-frame lockout means we wait until
 715 * the queue's current frame transmits (with post frame backoff and bursting)
 716 * before we transmit anything else and global lockout means we
 717 * wait for the whole queue to finish before higher priority queues
 718 * can transmit (this is used on beacon and CAB queues).
 719 * No lockout means there is no special handling.
 720 */
 721#define AR5K_DCU_MISC_BASE		0x1100			/* Register Address -Queue0 DCU_MISC */
 722#define	AR5K_DCU_MISC_BACKOFF		0x0000003f	/* Mask for backoff threshold */
 723#define	AR5K_DCU_MISC_ETS_RTS_POL	0x00000040	/* End of transmission series
 724							station RTS/data failure count
 725							reset policy (?) */
 726#define AR5K_DCU_MISC_ETS_CW_POL	0x00000080	/* End of transmission series
 727							CW reset policy */
 728#define	AR5K_DCU_MISC_FRAG_WAIT		0x00000100	/* Wait for next fragment */
 729#define AR5K_DCU_MISC_BACKOFF_FRAG	0x00000200	/* Enable backoff while bursting */
 730#define	AR5K_DCU_MISC_HCFPOLL_ENABLE	0x00000800	/* CF - Poll enable */
 731#define	AR5K_DCU_MISC_BACKOFF_PERSIST	0x00001000	/* Persistent backoff */
 732#define	AR5K_DCU_MISC_FRMPRFTCH_ENABLE	0x00002000	/* Enable frame pre-fetch */
 733#define	AR5K_DCU_MISC_VIRTCOL		0x0000c000	/* Mask for Virtual Collision (?) */
 734#define	AR5K_DCU_MISC_VIRTCOL_NORMAL	0
 735#define	AR5K_DCU_MISC_VIRTCOL_IGNORE	1
 736#define	AR5K_DCU_MISC_BCN_ENABLE	0x00010000	/* Enable Beacon use */
 737#define	AR5K_DCU_MISC_ARBLOCK_CTL	0x00060000	/* Arbiter lockout control mask */
 738#define	AR5K_DCU_MISC_ARBLOCK_CTL_S	17
 739#define	AR5K_DCU_MISC_ARBLOCK_CTL_NONE		0	/* No arbiter lockout */
 740#define	AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM	1	/* Intra-frame lockout */
 741#define	AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL	2	/* Global lockout */
 742#define	AR5K_DCU_MISC_ARBLOCK_IGNORE	0x00080000	/* Ignore Arbiter lockout */
 743#define	AR5K_DCU_MISC_SEQ_NUM_INCR_DIS	0x00100000	/* Disable sequence number increment */
 744#define	AR5K_DCU_MISC_POST_FR_BKOFF_DIS	0x00200000	/* Disable post-frame backoff */
 745#define	AR5K_DCU_MISC_VIRT_COLL_POLICY	0x00400000	/* Virtual Collision cw policy */
 746#define	AR5K_DCU_MISC_BLOWN_IFS_POLICY	0x00800000	/* Blown IFS policy (?) */
 747#define	AR5K_DCU_MISC_SEQNUM_CTL	0x01000000	/* Sequence number control (?) */
 748#define AR5K_QUEUE_DFS_MISC(_q)		AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)
 749
 750/*
 751 * DCU frame sequence number registers
 752 */
 753#define AR5K_DCU_SEQNUM_BASE		0x1140
 754#define	AR5K_DCU_SEQNUM_M		0x00000fff
 755#define	AR5K_QUEUE_DCU_SEQNUM(_q)	AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
 756
 757/*
 758 * DCU global IFS SIFS register
 759 */
 760#define AR5K_DCU_GBL_IFS_SIFS	0x1030
 761#define AR5K_DCU_GBL_IFS_SIFS_M	0x0000ffff
 762
 763/*
 764 * DCU global IFS slot interval register
 765 */
 766#define AR5K_DCU_GBL_IFS_SLOT	0x1070
 767#define AR5K_DCU_GBL_IFS_SLOT_M	0x0000ffff
 768
 769/*
 770 * DCU global IFS EIFS register
 771 */
 772#define AR5K_DCU_GBL_IFS_EIFS	0x10b0
 773#define AR5K_DCU_GBL_IFS_EIFS_M	0x0000ffff
 774
 775/*
 776 * DCU global IFS misc register
 777 *
 778 * LFSR stands for Linear Feedback Shift Register
 779 * and it's used for generating pseudo-random
 780 * number sequences.
 781 *
 782 * (If i understand correctly, random numbers are
 783 * used for idle sensing -multiplied with cwmin/max etc-)
 784 */
 785#define AR5K_DCU_GBL_IFS_MISC			0x10f0			/* Register Address */
 786#define	AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE	0x00000007	/* LFSR Slice Select */
 787#define	AR5K_DCU_GBL_IFS_MISC_TURBO_MODE	0x00000008	/* Turbo mode */
 788#define	AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC	0x000003f0	/* SIFS Duration mask */
 789#define	AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC_S	4
 790#define	AR5K_DCU_GBL_IFS_MISC_USEC_DUR		0x000ffc00	/* USEC Duration mask */
 791#define	AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S	10
 792#define	AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY	0x00300000	/* DCU Arbiter delay mask */
 793#define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST	0x00400000	/* SIFS cnt reset policy (?) */
 794#define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST	0x00800000	/* AIFS cnt reset policy (?) */
 795#define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS	0x01000000	/* Disable random LFSR slice */
 796
 797/*
 798 * DCU frame prefetch control register
 799 */
 800#define AR5K_DCU_FP			0x1230			/* Register Address */
 801#define AR5K_DCU_FP_NOBURST_DCU_EN	0x00000001	/* Enable non-burst prefetch on DCU (?) */
 802#define AR5K_DCU_FP_NOBURST_EN		0x00000010	/* Enable non-burst prefetch (?) */
 803#define AR5K_DCU_FP_BURST_DCU_EN	0x00000020	/* Enable burst prefetch on DCU (?) */
 804
 805/*
 806 * DCU transmit pause control/status register
 807 */
 808#define AR5K_DCU_TXP		0x1270			/* Register Address */
 809#define	AR5K_DCU_TXP_M		0x000003ff	/* Tx pause mask */
 810#define	AR5K_DCU_TXP_STATUS	0x00010000	/* Tx pause status */
 811
 812/*
 813 * DCU transmit filter table 0 (32 entries)
 814 * each entry contains a 32bit slice of the
 815 * 128bit tx filter for each DCU (4 slices per DCU)
 816 */
 817#define AR5K_DCU_TX_FILTER_0_BASE	0x1038
 818#define	AR5K_DCU_TX_FILTER_0(_n)	(AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
 819
 820/*
 821 * DCU transmit filter table 1 (16 entries)
 822 */
 823#define AR5K_DCU_TX_FILTER_1_BASE	0x103c
 824#define	AR5K_DCU_TX_FILTER_1(_n)	(AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
 825
 826/*
 827 * DCU clear transmit filter register
 828 */
 829#define AR5K_DCU_TX_FILTER_CLR	0x143c
 830
 831/*
 832 * DCU set transmit filter register
 833 */
 834#define AR5K_DCU_TX_FILTER_SET	0x147c
 835
 836/*
 837 * Reset control register
 838 */
 839#define AR5K_RESET_CTL		0x4000			/* Register Address */
 840#define AR5K_RESET_CTL_PCU	0x00000001	/* Protocol Control Unit reset */
 841#define AR5K_RESET_CTL_DMA	0x00000002	/* DMA (Rx/Tx) reset [5210] */
 842#define	AR5K_RESET_CTL_BASEBAND	0x00000002	/* Baseband reset [5211+] */
 843#define AR5K_RESET_CTL_MAC	0x00000004	/* MAC reset (PCU+Baseband ?) [5210] */
 844#define AR5K_RESET_CTL_PHY	0x00000008	/* PHY reset [5210] */
 845#define AR5K_RESET_CTL_PCI	0x00000010	/* PCI Core reset (interrupts etc) */
 846
 847/*
 848 * Sleep control register
 849 */
 850#define AR5K_SLEEP_CTL			0x4004			/* Register Address */
 851#define AR5K_SLEEP_CTL_SLDUR		0x0000ffff	/* Sleep duration mask */
 852#define AR5K_SLEEP_CTL_SLDUR_S		0
 853#define AR5K_SLEEP_CTL_SLE		0x00030000	/* Sleep enable mask */
 854#define AR5K_SLEEP_CTL_SLE_S		16
 855#define AR5K_SLEEP_CTL_SLE_WAKE		0x00000000	/* Force chip awake */
 856#define AR5K_SLEEP_CTL_SLE_SLP		0x00010000	/* Force chip sleep */
 857#define AR5K_SLEEP_CTL_SLE_ALLOW	0x00020000	/* Normal sleep policy */
 858#define AR5K_SLEEP_CTL_SLE_UNITS	0x00000008	/* [5211+] */
 859#define AR5K_SLEEP_CTL_DUR_TIM_POL	0x00040000	/* Sleep duration timing policy */
 860#define AR5K_SLEEP_CTL_DUR_WRITE_POL	0x00080000	/* Sleep duration write policy */
 861#define AR5K_SLEEP_CTL_SLE_POL		0x00100000	/* Sleep policy mode */
 862
 863/*
 864 * Interrupt pending register
 865 */
 866#define AR5K_INTPEND	0x4008
 867#define AR5K_INTPEND_M	0x00000001
 868
 869/*
 870 * Sleep force register
 871 */
 872#define AR5K_SFR	0x400c
 873#define AR5K_SFR_EN	0x00000001
 874
 875/*
 876 * PCI configuration register
 877 * TODO: Fix LED stuff
 878 */
 879#define AR5K_PCICFG			0x4010			/* Register Address */
 880#define AR5K_PCICFG_EEAE		0x00000001	/* Eeprom access enable [5210] */
 881#define AR5K_PCICFG_SLEEP_CLOCK_EN	0x00000002	/* Enable sleep clock */
 882#define AR5K_PCICFG_CLKRUNEN		0x00000004	/* CLKRUN enable [5211+] */
 883#define AR5K_PCICFG_EESIZE		0x00000018	/* Mask for EEPROM size [5211+] */
 884#define AR5K_PCICFG_EESIZE_S		3
 885#define AR5K_PCICFG_EESIZE_4K		0		/* 4K */
 886#define AR5K_PCICFG_EESIZE_8K		1		/* 8K */
 887#define AR5K_PCICFG_EESIZE_16K		2		/* 16K */
 888#define AR5K_PCICFG_EESIZE_FAIL		3		/* Failed to get size [5211+] */
 889#define AR5K_PCICFG_LED			0x00000060	/* Led status [5211+] */
 890#define AR5K_PCICFG_LED_NONE		0x00000000	/* Default [5211+] */
 891#define AR5K_PCICFG_LED_PEND		0x00000020	/* Scan / Auth pending */
 892#define AR5K_PCICFG_LED_ASSOC		0x00000040	/* Associated */
 893#define	AR5K_PCICFG_BUS_SEL		0x00000380	/* Mask for "bus select" [5211+] (?) */
 894#define AR5K_PCICFG_CBEFIX_DIS		0x00000400	/* Disable CBE fix */
 895#define AR5K_PCICFG_SL_INTEN		0x00000800	/* Enable interrupts when asleep */
 896#define AR5K_PCICFG_LED_BCTL		0x00001000	/* Led blink (?) [5210] */
 897#define AR5K_PCICFG_RETRY_FIX		0x00001000	/* Enable pci core retry fix */
 898#define AR5K_PCICFG_SL_INPEN		0x00002000	/* Sleep even with pending interrupts*/
 899#define AR5K_PCICFG_SPWR_DN		0x00010000	/* Mask for power status */
 900#define AR5K_PCICFG_LEDMODE		0x000e0000	/* Ledmode [5211+] */
 901#define AR5K_PCICFG_LEDMODE_PROP	0x00000000	/* Blink on standard traffic [5211+] */
 902#define AR5K_PCICFG_LEDMODE_PROM	0x00020000	/* Default mode (blink on any traffic) [5211+] */
 903#define AR5K_PCICFG_LEDMODE_PWR		0x00040000	/* Some other blinking mode  (?) [5211+] */
 904#define AR5K_PCICFG_LEDMODE_RAND	0x00060000	/* Random blinking (?) [5211+] */
 905#define AR5K_PCICFG_LEDBLINK		0x00700000	/* Led blink rate */
 906#define AR5K_PCICFG_LEDBLINK_S		20
 907#define AR5K_PCICFG_LEDSLOW		0x00800000	/* Slowest led blink rate [5211+] */
 908#define AR5K_PCICFG_LEDSTATE				\
 909	(AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE |	\
 910	AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
 911#define	AR5K_PCICFG_SLEEP_CLOCK_RATE	0x03000000	/* Sleep clock rate */
 912#define	AR5K_PCICFG_SLEEP_CLOCK_RATE_S	24
 913
 914/*
 915 * "General Purpose Input/Output" (GPIO) control register
 916 *
 917 * I'm not sure about this but after looking at the code
 918 * for all chipsets here is what i got.
 919 *
 920 * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits)
 921 * Mode 0 -> always input
 922 * Mode 1 -> output when GPIODO for this GPIO is set to 0
 923 * Mode 2 -> output when GPIODO for this GPIO is set to 1
 924 * Mode 3 -> always output
 925 *
 926 * For more infos check out get_gpio/set_gpio and
 927 * set_gpio_input/set_gpio_output functs.
 928 * For more infos on gpio interrupt check out set_gpio_intr.
 929 */
 930#define AR5K_NUM_GPIO	6
 931
 932#define AR5K_GPIOCR		0x4014				/* Register Address */
 933#define AR5K_GPIOCR_INT_ENA	0x00008000		/* Enable GPIO interrupt */
 934#define AR5K_GPIOCR_INT_SELL	0x00000000		/* Generate interrupt when pin is low */
 935#define AR5K_GPIOCR_INT_SELH	0x00010000		/* Generate interrupt when pin is high */
 936#define AR5K_GPIOCR_IN(n)	(0 << ((n) * 2))	/* Mode 0 for pin n */
 937#define AR5K_GPIOCR_OUT0(n)	(1 << ((n) * 2))	/* Mode 1 for pin n */
 938#define AR5K_GPIOCR_OUT1(n)	(2 << ((n) * 2))	/* Mode 2 for pin n */
 939#define AR5K_GPIOCR_OUT(n)	(3 << ((n) * 2))	/* Mode 3 for pin n */
 940#define AR5K_GPIOCR_INT_SEL(n)	((n) << 12)		/* Interrupt for GPIO pin n */
 941
 942/*
 943 * "General Purpose Input/Output" (GPIO) data output register
 944 */
 945#define AR5K_GPIODO	0x4018
 946
 947/*
 948 * "General Purpose Input/Output" (GPIO) data input register
 949 */
 950#define AR5K_GPIODI	0x401c
 951#define AR5K_GPIODI_M	0x0000002f
 952
 953/*
 954 * Silicon revision register
 955 */
 956#define AR5K_SREV		0x4020			/* Register Address */
 957#define AR5K_SREV_REV		0x0000000f	/* Mask for revision */
 958#define AR5K_SREV_REV_S		0
 959#define AR5K_SREV_VER		0x000000ff	/* Mask for version */
 960#define AR5K_SREV_VER_S		4
 961
 962/*
 963 * TXE write posting register
 964 */
 965#define	AR5K_TXEPOST	0x4028
 966
 967/*
 968 * QCU sleep mask
 969 */
 970#define	AR5K_QCU_SLEEP_MASK	0x402c
 971
 972/* 0x4068 is compression buffer configuration
 973 * register on 5414 and pm configuration register
 974 * on 5424 and newer pci-e chips. */
 975
 976/*
 977 * Compression buffer configuration
 978 * register (enable/disable) [5414]
 979 */
 980#define AR5K_5414_CBCFG		0x4068
 981#define AR5K_5414_CBCFG_BUF_DIS	0x10	/* Disable buffer */
 982
 983/*
 984 * PCI-E Power management configuration
 985 * and status register [5424+]
 986 */
 987#define	AR5K_PCIE_PM_CTL		0x4068			/* Register address */
 988/* Only 5424 */
 989#define	AR5K_PCIE_PM_CTL_L1_WHEN_D2	0x00000001	/* enable PCIe core enter L1
 990							when d2_sleep_en is asserted */
 991#define	AR5K_PCIE_PM_CTL_L0_L0S_CLEAR	0x00000002	/* Clear L0 and L0S counters */
 992#define	AR5K_PCIE_PM_CTL_L0_L0S_EN	0x00000004	/* Start L0 nd L0S counters */
 993#define	AR5K_PCIE_PM_CTL_LDRESET_EN	0x00000008	/* Enable reset when link goes
 994							down */
 995/* Wake On Wireless */
 996#define	AR5K_PCIE_PM_CTL_PME_EN		0x00000010	/* PME Enable */
 997#define	AR5K_PCIE_PM_CTL_AUX_PWR_DET	0x00000020	/* Aux power detect */
 998#define	AR5K_PCIE_PM_CTL_PME_CLEAR	0x00000040	/* Clear PME */
 999#define	AR5K_PCIE_PM_CTL_PSM_D0		0x00000080
1000#define	AR5K_PCIE_PM_CTL_PSM_D1		0x00000100
1001#define	AR5K_PCIE_PM_CTL_PSM_D2		0x00000200
1002#define	AR5K_PCIE_PM_CTL_PSM_D3		0x00000400
1003
1004/*
1005 * PCI-E Workaround enable register
1006 */
1007#define	AR5K_PCIE_WAEN	0x407c
1008
1009/*
1010 * PCI-E Serializer/Deserializer
1011 * registers
1012 */
1013#define	AR5K_PCIE_SERDES	0x4080
1014#define	AR5K_PCIE_SERDES_RESET	0x4084
1015
1016/*====EEPROM REGISTERS====*/
1017
1018/*
1019 * EEPROM access registers
1020 *
1021 * Here we got a difference between 5210/5211-12
1022 * read data register for 5210 is at 0x6800 and
1023 * status register is at 0x6c00. There is also
1024 * no eeprom command register on 5210 and the
1025 * offsets are different.
1026 *
1027 * To read eeprom data for a specific offset:
1028 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
1029 *        read AR5K_EEPROM_BASE +(4 * offset)
1030 *        check the eeprom status register
1031 *        and read eeprom data register.
1032 *
1033 * 5211 - write offset to AR5K_EEPROM_BASE
1034 * 5212   write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD
1035 *        check the eeprom status register
1036 *        and read eeprom data register.
1037 *
1038 * To write eeprom data for a specific offset:
1039 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
1040 *        write data to AR5K_EEPROM_BASE +(4 * offset)
1041 *        check the eeprom status register
1042 * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD
1043 * 5212   write offset to AR5K_EEPROM_BASE
1044 *        write data to data register
1045 *	  write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD
1046 *        check the eeprom status register
1047 *
1048 * For more infos check eeprom_* functs and the ar5k.c
1049 * file posted in madwifi-devel mailing list.
1050 * http://sourceforge.net/mailarchive/message.php?msg_id=8966525
1051 *
1052 */
1053#define AR5K_EEPROM_BASE	0x6000
1054
1055/*
1056 * EEPROM data register
1057 */
1058#define AR5K_EEPROM_DATA_5211	0x6004
1059#define AR5K_EEPROM_DATA_5210	0x6800
1060#define	AR5K_EEPROM_DATA	(ah->ah_version == AR5K_AR5210 ? \
1061				AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)
1062
1063/*
1064 * EEPROM command register
1065 */
1066#define AR5K_EEPROM_CMD		0x6008			/* Register Address */
1067#define AR5K_EEPROM_CMD_READ	0x00000001	/* EEPROM read */
1068#define AR5K_EEPROM_CMD_WRITE	0x00000002	/* EEPROM write */
1069#define AR5K_EEPROM_CMD_RESET	0x00000004	/* EEPROM reset */
1070
1071/*
1072 * EEPROM status register
1073 */
1074#define AR5K_EEPROM_STAT_5210	0x6c00			/* Register Address [5210] */
1075#define AR5K_EEPROM_STAT_5211	0x600c			/* Register Address [5211+] */
1076#define	AR5K_EEPROM_STATUS	(ah->ah_version == AR5K_AR5210 ? \
1077				AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)
1078#define AR5K_EEPROM_STAT_RDERR	0x00000001	/* EEPROM read failed */
1079#define AR5K_EEPROM_STAT_RDDONE	0x00000002	/* EEPROM read successful */
1080#define AR5K_EEPROM_STAT_WRERR	0x00000004	/* EEPROM write failed */
1081#define AR5K_EEPROM_STAT_WRDONE	0x00000008	/* EEPROM write successful */
1082
1083/*
1084 * EEPROM config register
1085 */
1086#define AR5K_EEPROM_CFG			0x6010			/* Register Address */
1087#define AR5K_EEPROM_CFG_SIZE		0x00000003		/* Size determination override */
1088#define AR5K_EEPROM_CFG_SIZE_AUTO	0
1089#define AR5K_EEPROM_CFG_SIZE_4KBIT	1
1090#define AR5K_EEPROM_CFG_SIZE_8KBIT	2
1091#define AR5K_EEPROM_CFG_SIZE_16KBIT	3
1092#define AR5K_EEPROM_CFG_WR_WAIT_DIS	0x00000004	/* Disable write wait */
1093#define AR5K_EEPROM_CFG_CLK_RATE	0x00000018	/* Clock rate */
1094#define AR5K_EEPROM_CFG_CLK_RATE_S		3
1095#define AR5K_EEPROM_CFG_CLK_RATE_156KHZ	0
1096#define AR5K_EEPROM_CFG_CLK_RATE_312KHZ	1
1097#define AR5K_EEPROM_CFG_CLK_RATE_625KHZ	2
1098#define AR5K_EEPROM_CFG_PROT_KEY	0x00ffff00      /* Protection key */
1099#define AR5K_EEPROM_CFG_PROT_KEY_S	8
1100#define AR5K_EEPROM_CFG_LIND_EN		0x01000000	/* Enable length indicator (?) */
1101
1102
1103/*
1104 * TODO: Wake On Wireless registers
1105 * Range 0x7000 - 0x7ce0
1106 */
1107
1108/*
1109 * Protocol Control Unit (PCU) registers
1110 */
1111/*
1112 * Used for checking initial register writes
1113 * during channel reset (see reset func)
1114 */
1115#define AR5K_PCU_MIN	0x8000
1116#define AR5K_PCU_MAX	0x8fff
1117
1118/*
1119 * First station id register (Lower 32 bits of MAC address)
1120 */
1121#define AR5K_STA_ID0		0x8000
1122#define	AR5K_STA_ID0_ARRD_L32	0xffffffff
1123
1124/*
1125 * Second station id register (Upper 16 bits of MAC address + PCU settings)
1126 */
1127#define AR5K_STA_ID1			0x8004			/* Register Address */
1128#define	AR5K_STA_ID1_ADDR_U16		0x0000ffff	/* Upper 16 bits of MAC address */
1129#define AR5K_STA_ID1_AP			0x00010000	/* Set AP mode */
1130#define AR5K_STA_ID1_ADHOC		0x00020000	/* Set Ad-Hoc mode */
1131#define AR5K_STA_ID1_PWR_SV		0x00040000	/* Power save reporting */
1132#define AR5K_STA_ID1_NO_KEYSRCH		0x00080000	/* No key search */
1133#define AR5K_STA_ID1_NO_PSPOLL		0x00100000	/* No power save polling [5210] */
1134#define AR5K_STA_ID1_PCF_5211		0x00100000	/* Enable PCF on [5211+] */
1135#define AR5K_STA_ID1_PCF_5210		0x00200000	/* Enable PCF on [5210]*/
1136#define	AR5K_STA_ID1_PCF		(ah->ah_version == AR5K_AR5210 ? \
1137					AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)
1138#define AR5K_STA_ID1_DEFAULT_ANTENNA	0x00200000	/* Use default antenna */
1139#define AR5K_STA_ID1_DESC_ANTENNA	0x00400000	/* Update antenna from descriptor */
1140#define AR5K_STA_ID1_RTS_DEF_ANTENNA	0x00800000	/* Use default antenna for RTS */
1141#define AR5K_STA_ID1_ACKCTS_6MB		0x01000000	/* Rate to use for ACK/CTS. 0: highest mandatory rate <= RX rate; 1: 1Mbps in B mode */
1142#define AR5K_STA_ID1_BASE_RATE_11B	0x02000000	/* 802.11b base rate. 0: 1, 2, 5.5 and 11Mbps; 1: 1 and 2Mbps. [5211+] */
1143#define AR5K_STA_ID1_SELFGEN_DEF_ANT	0x04000000	/* Use def. antenna for self generated frames */
1144#define AR5K_STA_ID1_CRYPT_MIC_EN	0x08000000	/* Enable MIC */
1145#define AR5K_STA_ID1_KEYSRCH_MODE	0x10000000	/* Look up key when key id != 0 */
1146#define AR5K_STA_ID1_PRESERVE_SEQ_NUM	0x20000000	/* Preserve sequence number */
1147#define AR5K_STA_ID1_CBCIV_ENDIAN	0x40000000	/* ??? */
1148#define AR5K_STA_ID1_KEYSRCH_MCAST	0x80000000	/* Do key cache search for mcast frames */
1149
1150#define	AR5K_STA_ID1_ANTENNA_SETTINGS	(AR5K_STA_ID1_DEFAULT_ANTENNA | \
1151					AR5K_STA_ID1_DESC_ANTENNA | \
1152					AR5K_STA_ID1_RTS_DEF_ANTENNA | \
1153					AR5K_STA_ID1_SELFGEN_DEF_ANT)
1154
1155/*
1156 * First BSSID register (MAC address, lower 32bits)
1157 */
1158#define AR5K_BSS_ID0	0x8008
1159
1160/*
1161 * Second BSSID register (MAC address in upper 16 bits)
1162 *
1163 * AID: Association ID
1164 */
1165#define AR5K_BSS_ID1		0x800c
1166#define AR5K_BSS_ID1_AID	0xffff0000
1167#define AR5K_BSS_ID1_AID_S	16
1168
1169/*
1170 * Backoff slot time register
1171 */
1172#define AR5K_SLOT_TIME	0x8010
1173
1174/*
1175 * ACK/CTS timeout register
1176 */
1177#define AR5K_TIME_OUT		0x8014			/* Register Address */
1178#define AR5K_TIME_OUT_ACK	0x00001fff	/* ACK timeout mask */
1179#define AR5K_TIME_OUT_ACK_S	0
1180#define AR5K_TIME_OUT_CTS	0x1fff0000	/* CTS timeout mask */
1181#define AR5K_TIME_OUT_CTS_S	16
1182
1183/*
1184 * RSSI threshold register
1185 */
1186#define AR5K_RSSI_THR			0x8018		/* Register Address */
1187#define AR5K_RSSI_THR_M			0x000000ff	/* Mask for RSSI threshold [5211+] */
1188#define AR5K_RSSI_THR_BMISS_5210	0x00000700	/* Mask for Beacon Missed threshold [5210] */
1189#define AR5K_RSSI_THR_BMISS_5210_S	8
1190#define AR5K_RSSI_THR_BMISS_5211	0x0000ff00	/* Mask for Beacon Missed threshold [5211+] */
1191#define AR5K_RSSI_THR_BMISS_5211_S	8
1192#define	AR5K_RSSI_THR_BMISS		(ah->ah_version == AR5K_AR5210 ? \
1193					AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211)
1194#define	AR5K_RSSI_THR_BMISS_S		8
1195
1196/*
1197 * 5210 has more PCU registers because there is no QCU/DCU
1198 * so queue parameters are set here, this way a lot common
1199 * registers have different address for 5210. To make things
1200 * easier we define a macro based on ah->ah_version for common
1201 * registers with different addresses and common flags.
1202 */
1203
1204/*
1205 * Retry limit register
1206 *
1207 * Retry limit register for 5210 (no QCU/DCU so it's done in PCU)
1208 */
1209#define AR5K_NODCU_RETRY_LMT		0x801c			/* Register Address */
1210#define AR5K_NODCU_RETRY_LMT_SH_RETRY	0x0000000f	/* Short retry limit mask */
1211#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S	0
1212#define AR5K_NODCU_RETRY_LMT_LG_RETRY	0x000000f0	/* Long retry mask */
1213#define AR5K_NODCU_RETRY_LMT_LG_RETRY_S	4
1214#define AR5K_NODCU_RETRY_LMT_SSH_RETRY	0x00003f00	/* Station short retry limit mask */
1215#define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S	8
1216#define AR5K_NODCU_RETRY_LMT_SLG_RETRY	0x000fc000	/* Station long retry limit mask */
1217#define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S	14
1218#define AR5K_NODCU_RETRY_LMT_CW_MIN	0x3ff00000	/* Minimum contention window mask */
1219#define AR5K_NODCU_RETRY_LMT_CW_MIN_S	20
1220
1221/*
1222 * Transmit latency register
1223 */
1224#define AR5K_USEC_5210			0x8020			/* Register Address [5210] */
1225#define AR5K_USEC_5211			0x801c			/* Register Address [5211+] */
1226#define AR5K_USEC			(ah->ah_version == AR5K_AR5210 ? \
1227					AR5K_USEC_5210 : AR5K_USEC_5211)
1228#define AR5K_USEC_1			0x0000007f	/* clock cycles for 1us */
1229#define AR5K_USEC_1_S			0
1230#define AR5K_USEC_32			0x00003f80	/* clock cycles for 1us while on 32MHz clock */
1231#define AR5K_USEC_32_S			7
1232#define AR5K_USEC_TX_…

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