/drivers/net/wireless/ath/ath5k/reg.h
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- /*
- * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
- * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
- * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
- *
- * Permission to use, copy, modify, and distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
- /*
- * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k
- * maintained by Reyk Floeter
- *
- * I tried to document those registers by looking at ar5k code, some
- * 802.11 (802.11e mostly) papers and by reading various public available
- * Atheros presentations and papers like these:
- *
- * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
- *
- * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
- *
- * This file also contains register values found on a memory dump of
- * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
- * released by Atheros and on various debug messages found on the net.
- */
- #include "../reg.h"
- /*====MAC DMA REGISTERS====*/
- /*
- * AR5210-Specific TXDP registers
- * 5210 has only 2 transmit queues so no DCU/QCU, just
- * 2 transmit descriptor pointers...
- */
- #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
- #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
- /*
- * Mac Control Register
- */
- #define AR5K_CR 0x0008 /* Register Address */
- #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
- #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
- #define AR5K_CR_RXE 0x00000004 /* RX Enable */
- #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
- #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
- #define AR5K_CR_RXD 0x00000020 /* RX Disable */
- #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
- /*
- * RX Descriptor Pointer register
- */
- #define AR5K_RXDP 0x000c
- /*
- * Configuration and status register
- */
- #define AR5K_CFG 0x0014 /* Register Address */
- #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */
- #define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */
- #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */
- #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */
- #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */
- #define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */
- #define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */
- #define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */
- #define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */
- #define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */
- #define AR5K_CFG_TXCNT_S 11
- #define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */
- #define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */
- #define AR5K_CFG_PCI_THRES 0x00060000 /* PCI Master req q threshold [5211+] */
- #define AR5K_CFG_PCI_THRES_S 17
- /*
- * Interrupt enable register
- */
- #define AR5K_IER 0x0024 /* Register Address */
- #define AR5K_IER_DISABLE 0x00000000 /* Disable card interrupts */
- #define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */
- /*
- * 0x0028 is Beacon Control Register on 5210
- * and first RTS duration register on 5211
- */
- /*
- * Beacon control register [5210]
- */
- #define AR5K_BCR 0x0028 /* Register Address */
- #define AR5K_BCR_AP 0x00000000 /* AP mode */
- #define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */
- #define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */
- #define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */
- #define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */
- #define AR5K_BCR_BCGET 0x00000010
- /*
- * First RTS duration register [5211]
- */
- #define AR5K_RTSD0 0x0028 /* Register Address */
- #define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */
- #define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */
- #define AR5K_RTSD0_9 0x0000ff00 /* 9Mb*/
- #define AR5K_RTSD0_9_S 8
- #define AR5K_RTSD0_12 0x00ff0000 /* 12Mb*/
- #define AR5K_RTSD0_12_S 16
- #define AR5K_RTSD0_18 0xff000000 /* 16Mb*/
- #define AR5K_RTSD0_18_S 24
- /*
- * 0x002c is Beacon Status Register on 5210
- * and second RTS duration register on 5211
- */
- /*
- * Beacon status register [5210]
- *
- * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR
- * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning
- * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR).
- * So SNAPPEDBCRVALID should also stand for "snapped BCR -values- valid", so i
- * renamed it to SNAPSHOTSVALID to make more sense. I really have no idea what
- * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR.
- */
- #define AR5K_BSR 0x002c /* Register Address */
- #define AR5K_BSR_BDLYSW 0x00000001 /* SW Beacon delay (?) */
- #define AR5K_BSR_BDLYDMA 0x00000002 /* DMA Beacon delay (?) */
- #define AR5K_BSR_TXQ1F 0x00000004 /* Beacon queue (1) finished */
- #define AR5K_BSR_ATIMDLY 0x00000008 /* ATIM delay (?) */
- #define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */
- #define AR5K_BSR_SNPBDMAE 0x00000200 /* Beacon DMA enabled (?) */
- #define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */
- #define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */
- #define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */
- #define AR5K_BSR_SWBA_CNT 0x00ff0000
- /*
- * Second RTS duration register [5211]
- */
- #define AR5K_RTSD1 0x002c /* Register Address */
- #define AR5K_RTSD1_24 0x000000ff /* 24Mb */
- #define AR5K_RTSD1_24_S 0
- #define AR5K_RTSD1_36 0x0000ff00 /* 36Mb */
- #define AR5K_RTSD1_36_S 8
- #define AR5K_RTSD1_48 0x00ff0000 /* 48Mb */
- #define AR5K_RTSD1_48_S 16
- #define AR5K_RTSD1_54 0xff000000 /* 54Mb */
- #define AR5K_RTSD1_54_S 24
- /*
- * Transmit configuration register
- */
- #define AR5K_TXCFG 0x0030 /* Register Address */
- #define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size (read) */
- #define AR5K_TXCFG_SDMAMR_S 0
- #define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */
- #define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */
- #define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Trigger level mask */
- #define AR5K_TXCFG_TXFULL_S 4
- #define AR5K_TXCFG_TXFULL_0B 0x00000000
- #define AR5K_TXCFG_TXFULL_64B 0x00000010
- #define AR5K_TXCFG_TXFULL_128B 0x00000020
- #define AR5K_TXCFG_TXFULL_192B 0x00000030
- #define AR5K_TXCFG_TXFULL_256B 0x00000040
- #define AR5K_TXCFG_TXCONT_EN 0x00000080
- #define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */
- #define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400 /* Enable jumbo tx descriptors [5211+] */
- #define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 /* Adhoc Beacon ATIM Policy */
- #define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 /* Disable ATIM window defer [5211+] */
- #define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */
- #define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */
- #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */
- #define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */
- #define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 /* Disable double buffering on DCU */
- #define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */
- /*
- * Receive configuration register
- */
- #define AR5K_RXCFG 0x0034 /* Register Address */
- #define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size (write) */
- #define AR5K_RXCFG_SDMAMW_S 0
- #define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */
- #define AR5K_RXCFG_DEF_ANTENNA 0x00000010 /* Default antenna (?) */
- #define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo rx descriptors [5211+] */
- #define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames [5211+] */
- #define AR5K_RXCFG_SLE_ENTRY 0x00000080 /* Sleep entry policy */
- /*
- * Receive jumbo descriptor last address register
- * Only found in 5211 (?)
- */
- #define AR5K_RXJLA 0x0038
- /*
- * MIB control register
- */
- #define AR5K_MIBC 0x0040 /* Register Address */
- #define AR5K_MIBC_COW 0x00000001 /* Counter Overflow Warning */
- #define AR5K_MIBC_FMC 0x00000002 /* Freeze MIB Counters */
- #define AR5K_MIBC_CMC 0x00000004 /* Clear MIB Counters */
- #define AR5K_MIBC_MCS 0x00000008 /* MIB counter strobe, increment all */
- /*
- * Timeout prescale register
- */
- #define AR5K_TOPS 0x0044
- #define AR5K_TOPS_M 0x0000ffff
- /*
- * Receive timeout register (no frame received)
- */
- #define AR5K_RXNOFRM 0x0048
- #define AR5K_RXNOFRM_M 0x000003ff
- /*
- * Transmit timeout register (no frame sent)
- */
- #define AR5K_TXNOFRM 0x004c
- #define AR5K_TXNOFRM_M 0x000003ff
- #define AR5K_TXNOFRM_QCU 0x000ffc00
- #define AR5K_TXNOFRM_QCU_S 10
- /*
- * Receive frame gap timeout register
- */
- #define AR5K_RPGTO 0x0050
- #define AR5K_RPGTO_M 0x000003ff
- /*
- * Receive frame count limit register
- */
- #define AR5K_RFCNT 0x0054
- #define AR5K_RFCNT_M 0x0000001f /* [5211+] (?) */
- #define AR5K_RFCNT_RFCL 0x0000000f /* [5210] */
- /*
- * Misc settings register
- * (reserved0-3)
- */
- #define AR5K_MISC 0x0058 /* Register Address */
- #define AR5K_MISC_DMA_OBS_M 0x000001e0
- #define AR5K_MISC_DMA_OBS_S 5
- #define AR5K_MISC_MISC_OBS_M 0x00000e00
- #define AR5K_MISC_MISC_OBS_S 9
- #define AR5K_MISC_MAC_OBS_LSB_M 0x00007000
- #define AR5K_MISC_MAC_OBS_LSB_S 12
- #define AR5K_MISC_MAC_OBS_MSB_M 0x00038000
- #define AR5K_MISC_MAC_OBS_MSB_S 15
- #define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */
- #define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */
- /*
- * QCU/DCU clock gating register (5311)
- * (reserved4-5)
- */
- #define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */
- #define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */
- #define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */
- /*
- * Interrupt Status Registers
- *
- * For 5210 there is only one status register but for
- * 5211/5212 we have one primary and 4 secondary registers.
- * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212.
- * Most of these bits are common for all chipsets.
- */
- #define AR5K_ISR 0x001c /* Register Address [5210] */
- #define AR5K_PISR 0x0080 /* Register Address [5211+] */
- #define AR5K_ISR_RXOK 0x00000001 /* Frame successfully received */
- #define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */
- #define AR5K_ISR_RXERR 0x00000004 /* Receive error */
- #define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */
- #define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */
- #define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */
- #define AR5K_ISR_TXOK 0x00000040 /* Frame successfully transmitted */
- #define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */
- #define AR5K_ISR_TXERR 0x00000100 /* Transmit error */
- #define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout) */
- #define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */
- #define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */
- #define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */
- #define AR5K_ISR_SWI 0x00002000 /* Software interrupt */
- #define AR5K_ISR_RXPHY 0x00004000 /* PHY error */
- #define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */
- #define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */
- #define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
- #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */
- #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
- #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */
- #define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */
- #define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */
- #define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */
- #define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */
- #define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */
- #define AR5K_ISR_TIM 0x00800000 /* [5211+] */
- #define AR5K_ISR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
- CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
- #define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */
- #define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */
- #define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */
- #define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */
- /*
- * Secondary status registers [5211+] (0 - 4)
- *
- * These give the status for each QCU, only QCUs 0-9 are
- * represented.
- */
- #define AR5K_SISR0 0x0084 /* Register Address [5211+] */
- #define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */
- #define AR5K_SISR0_QCU_TXOK_S 0
- #define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */
- #define AR5K_SISR0_QCU_TXDESC_S 16
- #define AR5K_SISR1 0x0088 /* Register Address [5211+] */
- #define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */
- #define AR5K_SISR1_QCU_TXERR_S 0
- #define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */
- #define AR5K_SISR1_QCU_TXEOL_S 16
- #define AR5K_SISR2 0x008c /* Register Address [5211+] */
- #define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */
- #define AR5K_SISR2_QCU_TXURN_S 0
- #define AR5K_SISR2_MCABT 0x00010000 /* Master Cycle Abort */
- #define AR5K_SISR2_SSERR 0x00020000 /* Signaled System Error */
- #define AR5K_SISR2_DPERR 0x00040000 /* Bus parity error */
- #define AR5K_SISR2_TIM 0x01000000 /* [5212+] */
- #define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */
- #define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */
- #define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
- #define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
- #define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */
- #define AR5K_SISR2_TSFOOR 0x80000000 /* TSF OOR (?) */
- #define AR5K_SISR3 0x0090 /* Register Address [5211+] */
- #define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */
- #define AR5K_SISR3_QCBRORN_S 0
- #define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */
- #define AR5K_SISR3_QCBRURN_S 16
- #define AR5K_SISR4 0x0094 /* Register Address [5211+] */
- #define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */
- #define AR5K_SISR4_QTRIG_S 0
- /*
- * Shadow read-and-clear interrupt status registers [5211+]
- */
- #define AR5K_RAC_PISR 0x00c0 /* Read and clear PISR */
- #define AR5K_RAC_SISR0 0x00c4 /* Read and clear SISR0 */
- #define AR5K_RAC_SISR1 0x00c8 /* Read and clear SISR1 */
- #define AR5K_RAC_SISR2 0x00cc /* Read and clear SISR2 */
- #define AR5K_RAC_SISR3 0x00d0 /* Read and clear SISR3 */
- #define AR5K_RAC_SISR4 0x00d4 /* Read and clear SISR4 */
- /*
- * Interrupt Mask Registers
- *
- * As with ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary
- * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match.
- */
- #define AR5K_IMR 0x0020 /* Register Address [5210] */
- #define AR5K_PIMR 0x00a0 /* Register Address [5211+] */
- #define AR5K_IMR_RXOK 0x00000001 /* Frame successfully received*/
- #define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/
- #define AR5K_IMR_RXERR 0x00000004 /* Receive error*/
- #define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/
- #define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/
- #define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/
- #define AR5K_IMR_TXOK 0x00000040 /* Frame successfully transmitted*/
- #define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/
- #define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/
- #define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout)*/
- #define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/
- #define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/
- #define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/
- #define AR5K_IMR_SWI 0x00002000 /* Software interrupt */
- #define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/
- #define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */
- #define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/
- #define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
- #define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/
- #define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
- #define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */
- #define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */
- #define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/
- #define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */
- #define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */
- #define AR5K_IMR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */
- #define AR5K_IMR_TIM 0x00800000 /* [5211+] */
- #define AR5K_IMR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
- CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
- #define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/
- #define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */
- #define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */
- #define AR5K_IMR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */
- /*
- * Secondary interrupt mask registers [5211+] (0 - 4)
- */
- #define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */
- #define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */
- #define AR5K_SIMR0_QCU_TXOK_S 0
- #define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */
- #define AR5K_SIMR0_QCU_TXDESC_S 16
- #define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */
- #define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */
- #define AR5K_SIMR1_QCU_TXERR_S 0
- #define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */
- #define AR5K_SIMR1_QCU_TXEOL_S 16
- #define AR5K_SIMR2 0x00ac /* Register Address [5211+] */
- #define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */
- #define AR5K_SIMR2_QCU_TXURN_S 0
- #define AR5K_SIMR2_MCABT 0x00010000 /* Master Cycle Abort */
- #define AR5K_SIMR2_SSERR 0x00020000 /* Signaled System Error */
- #define AR5K_SIMR2_DPERR 0x00040000 /* Bus parity error */
- #define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */
- #define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */
- #define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */
- #define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
- #define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
- #define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */
- #define AR5K_SIMR2_TSFOOR 0x80000000 /* TSF OOR (?) */
- #define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */
- #define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */
- #define AR5K_SIMR3_QCBRORN_S 0
- #define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */
- #define AR5K_SIMR3_QCBRURN_S 16
- #define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */
- #define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */
- #define AR5K_SIMR4_QTRIG_S 0
- /*
- * DMA Debug registers 0-7
- * 0xe0 - 0xfc
- */
- /*
- * Decompression mask registers [5212+]
- */
- #define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (index) */
- #define AR5K_DCM_DATA 0x0404 /*Decompression mask data */
- /*
- * Wake On Wireless pattern control register [5212+]
- */
- #define AR5K_WOW_PCFG 0x0410 /* Register Address */
- #define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 /* Pattern match enable */
- #define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 /* Long frame policy */
- #define AR5K_WOW_PCFG_WOBMISS 0x00000004 /* Wake on bea(con) miss (?) */
- #define AR5K_WOW_PCFG_PAT_0_EN 0x00000100 /* Enable pattern 0 */
- #define AR5K_WOW_PCFG_PAT_1_EN 0x00000200 /* Enable pattern 1 */
- #define AR5K_WOW_PCFG_PAT_2_EN 0x00000400 /* Enable pattern 2 */
- #define AR5K_WOW_PCFG_PAT_3_EN 0x00000800 /* Enable pattern 3 */
- #define AR5K_WOW_PCFG_PAT_4_EN 0x00001000 /* Enable pattern 4 */
- #define AR5K_WOW_PCFG_PAT_5_EN 0x00002000 /* Enable pattern 5 */
- /*
- * Wake On Wireless pattern index register (?) [5212+]
- */
- #define AR5K_WOW_PAT_IDX 0x0414
- /*
- * Wake On Wireless pattern data register [5212+]
- */
- #define AR5K_WOW_PAT_DATA 0x0418 /* Register Address */
- #define AR5K_WOW_PAT_DATA_0_3_V 0x00000001 /* Pattern 0, 3 value */
- #define AR5K_WOW_PAT_DATA_1_4_V 0x00000100 /* Pattern 1, 4 value */
- #define AR5K_WOW_PAT_DATA_2_5_V 0x00010000 /* Pattern 2, 5 value */
- #define AR5K_WOW_PAT_DATA_0_3_M 0x01000000 /* Pattern 0, 3 mask */
- #define AR5K_WOW_PAT_DATA_1_4_M 0x04000000 /* Pattern 1, 4 mask */
- #define AR5K_WOW_PAT_DATA_2_5_M 0x10000000 /* Pattern 2, 5 mask */
- /*
- * Decompression configuration registers [5212+]
- */
- #define AR5K_DCCFG 0x0420 /* Register Address */
- #define AR5K_DCCFG_GLOBAL_EN 0x00000001 /* Enable decompression on all queues */
- #define AR5K_DCCFG_BYPASS_EN 0x00000002 /* Bypass decompression */
- #define AR5K_DCCFG_BCAST_EN 0x00000004 /* Enable decompression for bcast frames */
- #define AR5K_DCCFG_MCAST_EN 0x00000008 /* Enable decompression for mcast frames */
- /*
- * Compression configuration registers [5212+]
- */
- #define AR5K_CCFG 0x0600 /* Register Address */
- #define AR5K_CCFG_WINDOW_SIZE 0x00000007 /* Compression window size */
- #define AR5K_CCFG_CPC_EN 0x00000008 /* Enable performance counters */
- #define AR5K_CCFG_CCU 0x0604 /* Register Address */
- #define AR5K_CCFG_CCU_CUP_EN 0x00000001 /* CCU Catchup enable */
- #define AR5K_CCFG_CCU_CREDIT 0x00000002 /* CCU Credit (field) */
- #define AR5K_CCFG_CCU_CD_THRES 0x00000080 /* CCU Cyc(lic?) debt threshold (field) */
- #define AR5K_CCFG_CCU_CUP_LCNT 0x00010000 /* CCU Catchup lit(?) count */
- #define AR5K_CCFG_CCU_INIT 0x00100200 /* Initial value during reset */
- /*
- * Compression performance counter registers [5212+]
- */
- #define AR5K_CPC0 0x0610 /* Compression performance counter 0 */
- #define AR5K_CPC1 0x0614 /* Compression performance counter 1*/
- #define AR5K_CPC2 0x0618 /* Compression performance counter 2 */
- #define AR5K_CPC3 0x061c /* Compression performance counter 3 */
- #define AR5K_CPCOVF 0x0620 /* Compression performance overflow */
- /*
- * Queue control unit (QCU) registers [5211+]
- *
- * Card has 12 TX Queues but i see that only 0-9 are used (?)
- * both in binary HAL (see ah.h) and ar5k. Each queue has it's own
- * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
- * configuration register (0x08c0 - 0x08ec), a ready time configuration
- * register (0x0900 - 0x092c), a misc configuration register (0x09c0 -
- * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some
- * global registers, QCU transmit enable/disable and "one shot arm (?)"
- * set/clear, which contain status for all queues (we shift by 1 for each
- * queue). To access these registers easily we define some macros here
- * that are used inside HAL. For more infos check out *_tx_queue functs.
- */
- /*
- * Generic QCU Register access macros
- */
- #define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r)
- #define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q))
- #define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q))
- /*
- * QCU Transmit descriptor pointer registers
- */
- #define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */
- #define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)
- /*
- * QCU Transmit enable register
- */
- #define AR5K_QCU_TXE 0x0840
- #define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)
- #define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)
- /*
- * QCU Transmit disable register
- */
- #define AR5K_QCU_TXD 0x0880
- #define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)
- #define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)
- /*
- * QCU Constant Bit Rate configuration registers
- */
- #define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */
- #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */
- #define AR5K_QCU_CBRCFG_INTVAL_S 0
- #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */
- #define AR5K_QCU_CBRCFG_ORN_THRES_S 24
- #define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)
- /*
- * QCU Ready time configuration registers
- */
- #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */
- #define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */
- #define AR5K_QCU_RDYTIMECFG_INTVAL_S 0
- #define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */
- #define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)
- /*
- * QCU one shot arm set registers
- */
- #define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */
- #define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff
- /*
- * QCU one shot arm clear registers
- */
- #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */
- #define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff
- /*
- * QCU misc registers
- */
- #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */
- #define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame scheduling mask */
- #define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */
- #define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */
- #define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated */
- #define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* TIMT gated */
- #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated */
- #define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */
- #define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */
- #define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */
- #define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */
- #define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR expired threshold enabled */
- #define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME expired or VEOL */
- #define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */
- #define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */
- #define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */
- #define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)
- /*
- * QCU status registers
- */
- #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */
- #define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */
- #define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter */
- #define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)
- /*
- * QCU ready time shutdown register
- */
- #define AR5K_QCU_RDYTIMESHDN 0x0a40
- #define AR5K_QCU_RDYTIMESHDN_M 0x000003ff
- /*
- * QCU compression buffer base registers [5212+]
- */
- #define AR5K_QCU_CBB_SELECT 0x0b00
- #define AR5K_QCU_CBB_ADDR 0x0b04
- #define AR5K_QCU_CBB_ADDR_S 9
- /*
- * QCU compression buffer configuration register [5212+]
- * (buffer size)
- */
- #define AR5K_QCU_CBCFG 0x0b08
- /*
- * Distributed Coordination Function (DCF) control unit (DCU)
- * registers [5211+]
- *
- * These registers control the various characteristics of each queue
- * for 802.11e (WME) compatibility so they go together with
- * QCU registers in pairs. For each queue we have a QCU mask register,
- * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),
- * a retry limit register (0x1080 - 0x10ac), a channel time register
- * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and
- * a sequence number register (0x1140 - 0x116c). It seems that "global"
- * registers here affect all queues (see use of DCU_GBL_IFS_SLOT in ar5k).
- * We use the same macros here for easier register access.
- *
- */
- /*
- * DCU QCU mask registers
- */
- #define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */
- #define AR5K_DCU_QCUMASK_M 0x000003ff
- #define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)
- /*
- * DCU local Inter Frame Space settings register
- */
- #define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */
- #define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /* Minimum Contention Window */
- #define AR5K_DCU_LCL_IFS_CW_MIN_S 0
- #define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /* Maximum Contention Window */
- #define AR5K_DCU_LCL_IFS_CW_MAX_S 10
- #define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */
- #define AR5K_DCU_LCL_IFS_AIFS_S 20
- #define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc /* Anything above that can cause DCU to hang */
- #define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)
- /*
- * DCU retry limit registers
- * all these fields don't allow zero values
- */
- #define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */
- #define AR5K_DCU_RETRY_LMT_RTS 0x0000000f /* RTS failure limit. Transmission fails if no CTS is received for this number of times */
- #define AR5K_DCU_RETRY_LMT_RTS_S 0
- #define AR5K_DCU_RETRY_LMT_STA_RTS 0x00003f00 /* STA RTS failure limit. If exceeded CW reset */
- #define AR5K_DCU_RETRY_LMT_STA_RTS_S 8
- #define AR5K_DCU_RETRY_LMT_STA_DATA 0x000fc000 /* STA data failure limit. If exceeded CW reset. */
- #define AR5K_DCU_RETRY_LMT_STA_DATA_S 14
- #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)
- /*
- * DCU channel time registers
- */
- #define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */
- #define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */
- #define AR5K_DCU_CHAN_TIME_DUR_S 0
- #define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */
- #define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)
- /*
- * DCU misc registers [5211+]
- *
- * Note: Arbiter lockout control controls the
- * behaviour on low priority queues when we have multiple queues
- * with pending frames. Intra-frame lockout means we wait until
- * the queue's current frame transmits (with post frame backoff and bursting)
- * before we transmit anything else and global lockout means we
- * wait for the whole queue to finish before higher priority queues
- * can transmit (this is used on beacon and CAB queues).
- * No lockout means there is no special handling.
- */
- #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */
- #define AR5K_DCU_MISC_BACKOFF 0x0000003f /* Mask for backoff threshold */
- #define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040 /* End of transmission series
- station RTS/data failure count
- reset policy (?) */
- #define AR5K_DCU_MISC_ETS_CW_POL 0x00000080 /* End of transmission series
- CW reset policy */
- #define AR5K_DCU_MISC_FRAG_WAIT 0x00000100 /* Wait for next fragment */
- #define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */
- #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */
- #define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */
- #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */
- #define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */
- #define AR5K_DCU_MISC_VIRTCOL_NORMAL 0
- #define AR5K_DCU_MISC_VIRTCOL_IGNORE 1
- #define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */
- #define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */
- #define AR5K_DCU_MISC_ARBLOCK_CTL_S 17
- #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */
- #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */
- #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */
- #define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 /* Ignore Arbiter lockout */
- #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment */
- #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */
- #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision cw policy */
- #define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS policy (?) */
- #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */
- #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)
- /*
- * DCU frame sequence number registers
- */
- #define AR5K_DCU_SEQNUM_BASE 0x1140
- #define AR5K_DCU_SEQNUM_M 0x00000fff
- #define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
- /*
- * DCU global IFS SIFS register
- */
- #define AR5K_DCU_GBL_IFS_SIFS 0x1030
- #define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff
- /*
- * DCU global IFS slot interval register
- */
- #define AR5K_DCU_GBL_IFS_SLOT 0x1070
- #define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff
- /*
- * DCU global IFS EIFS register
- */
- #define AR5K_DCU_GBL_IFS_EIFS 0x10b0
- #define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff
- /*
- * DCU global IFS misc register
- *
- * LFSR stands for Linear Feedback Shift Register
- * and it's used for generating pseudo-random
- * number sequences.
- *
- * (If i understand correctly, random numbers are
- * used for idle sensing -multiplied with cwmin/max etc-)
- */
- #define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */
- #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 /* LFSR Slice Select */
- #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */
- #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */
- #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC_S 4
- #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */
- #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10
- #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */
- #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFS cnt reset policy (?) */
- #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */
- #define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */
- /*
- * DCU frame prefetch control register
- */
- #define AR5K_DCU_FP 0x1230 /* Register Address */
- #define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */
- #define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */
- #define AR5K_DCU_FP_BURST_DCU_EN 0x00000020 /* Enable burst prefetch on DCU (?) */
- /*
- * DCU transmit pause control/status register
- */
- #define AR5K_DCU_TXP 0x1270 /* Register Address */
- #define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask */
- #define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status */
- /*
- * DCU transmit filter table 0 (32 entries)
- * each entry contains a 32bit slice of the
- * 128bit tx filter for each DCU (4 slices per DCU)
- */
- #define AR5K_DCU_TX_FILTER_0_BASE 0x1038
- #define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
- /*
- * DCU transmit filter table 1 (16 entries)
- */
- #define AR5K_DCU_TX_FILTER_1_BASE 0x103c
- #define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
- /*
- * DCU clear transmit filter register
- */
- #define AR5K_DCU_TX_FILTER_CLR 0x143c
- /*
- * DCU set transmit filter register
- */
- #define AR5K_DCU_TX_FILTER_SET 0x147c
- /*
- * Reset control register
- */
- #define AR5K_RESET_CTL 0x4000 /* Register Address */
- #define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */
- #define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */
- #define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */
- #define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */
- #define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */
- #define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */
- /*
- * Sleep control register
- */
- #define AR5K_SLEEP_CTL 0x4004 /* Register Address */
- #define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */
- #define AR5K_SLEEP_CTL_SLDUR_S 0
- #define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */
- #define AR5K_SLEEP_CTL_SLE_S 16
- #define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */
- #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */
- #define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 /* Normal sleep policy */
- #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */
- #define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 /* Sleep duration timing policy */
- #define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 /* Sleep duration write policy */
- #define AR5K_SLEEP_CTL_SLE_POL 0x00100000 /* Sleep policy mode */
- /*
- * Interrupt pending register
- */
- #define AR5K_INTPEND 0x4008
- #define AR5K_INTPEND_M 0x00000001
- /*
- * Sleep force register
- */
- #define AR5K_SFR 0x400c
- #define AR5K_SFR_EN 0x00000001
- /*
- * PCI configuration register
- * TODO: Fix LED stuff
- */
- #define AR5K_PCICFG 0x4010 /* Register Address */
- #define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */
- #define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock */
- #define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */
- #define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */
- #define AR5K_PCICFG_EESIZE_S 3
- #define AR5K_PCICFG_EESIZE_4K 0 /* 4K */
- #define AR5K_PCICFG_EESIZE_8K 1 /* 8K */
- #define AR5K_PCICFG_EESIZE_16K 2 /* 16K */
- #define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size [5211+] */
- #define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */
- #define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */
- #define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */
- #define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */
- #define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */
- #define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix */
- #define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep */
- #define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */
- #define AR5K_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core retry fix */
- #define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even with pending interrupts*/
- #define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */
- #define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */
- #define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */
- #define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */
- #define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */
- #define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */
- #define AR5K_PCICFG_LEDBLINK 0x00700000 /* Led blink rate */
- #define AR5K_PCICFG_LEDBLINK_S 20
- #define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slowest led blink rate [5211+] */
- #define AR5K_PCICFG_LEDSTATE \
- (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \
- AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
- #define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate */
- #define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24
- /*
- * "General Purpose Input/Output" (GPIO) control register
- *
- * I'm not sure about this but after looking at the code
- * for all chipsets here is what i got.
- *
- * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits)
- * Mode 0 -> always input
- * Mode 1 -> output when GPIODO for this GPIO is set to 0
- * Mode 2 -> output when GPIODO for this GPIO is set to 1
- * Mode 3 -> always output
- *
- * For more infos check out get_gpio/set_gpio and
- * set_gpio_input/set_gpio_output functs.
- * For more infos on gpio interrupt check out set_gpio_intr.
- */
- #define AR5K_NUM_GPIO 6
- #define AR5K_GPIOCR 0x4014 /* Register Address */
- #define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */
- #define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is low */
- #define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is high */
- #define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */
- #define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */
- #define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */
- #define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /* Mode 3 for pin n */
- #define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /* Interrupt for GPIO pin n */
- /*
- * "General Purpose Input/Output" (GPIO) data output register
- */
- #define AR5K_GPIODO 0x4018
- /*
- * "General Purpose Input/Output" (GPIO) data input register
- */
- #define AR5K_GPIODI 0x401c
- #define AR5K_GPIODI_M 0x0000002f
- /*
- * Silicon revision register
- */
- #define AR5K_SREV 0x4020 /* Register Address */
- #define AR5K_SREV_REV 0x0000000f /* Mask for revision */
- #define AR5K_SREV_REV_S 0
- #define AR5K_SREV_VER 0x000000ff /* Mask for version */
- #define AR5K_SREV_VER_S 4
- /*
- * TXE write posting register
- */
- #define AR5K_TXEPOST 0x4028
- /*
- * QCU sleep mask
- */
- #define AR5K_QCU_SLEEP_MASK 0x402c
- /* 0x4068 is compression buffer configuration
- * register on 5414 and pm configuration register
- * on 5424 and newer pci-e chips. */
- /*
- * Compression buffer configuration
- * register (enable/disable) [5414]
- */
- #define AR5K_5414_CBCFG 0x4068
- #define AR5K_5414_CBCFG_BUF_DIS 0x10 /* Disable buffer */
- /*
- * PCI-E Power management configuration
- * and status register [5424+]
- */
- #define AR5K_PCIE_PM_CTL 0x4068 /* Register address */
- /* Only 5424 */
- #define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 /* enable PCIe core enter L1
- when d2_sleep_en is asserted */
- #define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 /* Clear L0 and L0S counters */
- #define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 /* Start L0 nd L0S counters */
- #define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 /* Enable reset when link goes
- down */
- /* Wake On Wireless */
- #define AR5K_PCIE_PM_CTL_PME_EN 0x00000010 /* PME Enable */
- #define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 /* Aux power detect */
- #define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 /* Clear PME */
- #define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080
- #define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100
- #define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200
- #define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400
- /*
- * PCI-E Workaround enable register
- */
- #define AR5K_PCIE_WAEN 0x407c
- /*
- * PCI-E Serializer/Deserializer
- * registers
- */
- #define AR5K_PCIE_SERDES 0x4080
- #define AR5K_PCIE_SERDES_RESET 0x4084
- /*====EEPROM REGISTERS====*/
- /*
- * EEPROM access registers
- *
- * Here we got a difference between 5210/5211-12
- * read data register for 5210 is at 0x6800 and
- * status register is at 0x6c00. There is also
- * no eeprom command register on 5210 and the
- * offsets are different.
- *
- * To read eeprom data for a specific offset:
- * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
- * read AR5K_EEPROM_BASE +(4 * offset)
- * check the eeprom status register
- * and read eeprom data register.
- *
- * 5211 - write offset to AR5K_EEPROM_BASE
- * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD
- * check the eeprom status register
- * and read eeprom data register.
- *
- * To write eeprom data for a specific offset:
- * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
- * write data to AR5K_EEPROM_BASE +(4 * offset)
- * check the eeprom status register
- * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD
- * 5212 write offset to AR5K_EEPROM_BASE
- * write data to data register
- * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD
- * check the eeprom status register
- *
- * For more infos check eeprom_* functs and the ar5k.c
- * file posted in madwifi-devel mailing list.
- * http://sourceforge.net/mailarchive/message.php?msg_id=8966525
- *
- */
- #define AR5K_EEPROM_BASE 0x6000
- /*
- * EEPROM data register
- */
- #define AR5K_EEPROM_DATA_5211 0x6004
- #define AR5K_EEPROM_DATA_5210 0x6800
- #define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \
- AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)
- /*
- * EEPROM command register
- */
- #define AR5K_EEPROM_CMD 0x6008 /* Register Address */
- #define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */
- #define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */
- #define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */
- /*
- * EEPROM status register
- */
- #define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */
- #define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */
- #define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \
- AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)
- #define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */
- #define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */
- #define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */
- #define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */
- /*
- * EEPROM config register
- */
- #define AR5K_EEPROM_CFG 0x6010 /* Register Address */
- #define AR5K_EEPROM_CFG_SIZE 0x00000003 /* Size determination override */
- #define AR5K_EEPROM_CFG_SIZE_AUTO 0
- #define AR5K_EEPROM_CFG_SIZE_4KBIT 1
- #define AR5K_EEPROM_CFG_SIZE_8KBIT 2
- #define AR5K_EEPROM_CFG_SIZE_16KBIT 3
- #define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */
- #define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */
- #define AR5K_EEPROM_CFG_CLK_RATE_S 3
- #define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0
- #define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1
- #define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2
- #define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protection key */
- #define AR5K_EEPROM_CFG_PROT_KEY_S 8
- #define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */
- /*
- * TODO: Wake On Wireless registers
- * Range 0x7000 - 0x7ce0
- */
- /*
- * Protocol Control Unit (PCU) registers
- */
- /*
- * Used for checking initial register writes
- * during channel reset (see reset func)
- */
- #define AR5K_PCU_MIN 0x8000
- #define AR5K_PCU_MAX 0x8fff
- /*
- * First station id register (Lower 32 bits of MAC address)
- */
- #define AR5K_STA_ID0 0x8000
- #define AR5K_STA_ID0_ARRD_L32 0xffffffff
- /*
- * Second station id register (Upper 16 bits of MAC address + PCU settings)
- */
- #define AR5K_STA_ID1 0x8004 /* Register Address */
- #define AR5K_STA_ID1_ADDR_U16 0x0000ffff /* Upper 16 bits of MAC address */
- #define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */
- #define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */
- #define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting */
- #define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */
- #define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */
- #define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */
- #define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/
- #define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \
- AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)
- #define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */
- #define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */
- #define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */
- #define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Rate to use for ACK/CTS. 0: highest mandatory rate <= RX rate; 1: 1Mbps in B mode */
- #define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* 802.11b base rate. 0: 1, 2, 5.5 and 11Mbps; 1: 1 and 2Mbps. [5211+] */
- #define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 /* Use def. antenna for self generated frames */
- #define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */
- #define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Look up key when key id != 0 */
- #define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */
- #define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 /* ??? */
- #define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 /* Do key cache search for mcast frames */
- #define AR5K_STA_ID1_ANTENNA_SETTINGS (AR5K_STA_ID1_DEFAULT_ANTENNA | \
- AR5K_STA_ID1_DESC_ANTENNA | \
- AR5K_STA_ID1_RTS_DEF_ANTENNA | \
- AR5K_STA_ID1_SELFGEN_DEF_ANT)
- /*
- * First BSSID register (MAC address, lower 32bits)
- */
- #define AR5K_BSS_ID0 0x8008
- /*
- * Second BSSID register (MAC address in upper 16 bits)
- *
- * AID: Association ID
- */
- #define AR5K_BSS_ID1 0x800c
- #define AR5K_BSS_ID1_AID 0xffff0000
- #define AR5K_BSS_ID1_AID_S 16
- /*
- * Backoff slot time register
- */
- #define AR5K_SLOT_TIME 0x8010
- /*
- * ACK/CTS timeout register
- */
- #define AR5K_TIME_OUT 0x8014 /* Register Address */
- #define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */
- #define AR5K_TIME_OUT_ACK_S 0
- #define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */
- #define AR5K_TIME_OUT_CTS_S 16
- /*
- * RSSI threshold register
- */
- #define AR5K_RSSI_THR 0x8018 /* Register Address */
- #define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */
- #define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */
- #define AR5K_RSSI_THR_BMISS_5210_S 8
- #define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */
- #define AR5K_RSSI_THR_BMISS_5211_S 8
- #define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \
- AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211)
- #define AR5K_RSSI_THR_BMISS_S 8
- /*
- * 5210 has more PCU registers because there is no QCU/DCU
- * so queue parameters are set here, this way a lot common
- * registers have different address for 5210. To make things
- * easier we define a macro based on ah->ah_version for common
- * registers with different addresses and common flags.
- */
- /*
- * Retry limit register
- *
- * Retry limit register for 5210 (no QCU/DCU so it's done in PCU)
- */
- #define AR5K_NODCU_RETRY_LMT 0x801c /* Register Address */
- #define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */
- #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0
- #define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */
- #define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4
- #define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */
- #define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8
- #define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */
- #define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14
- #define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */
- #define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20
- /*
- * Transmit latency register
- */
- #define AR5K_USEC_5210 0x8020 /* Register Address [5210] */
- #define AR5K_USEC_5211 0x801c /* Register Address [5211+] */
- #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \
- AR5K_USEC_5210 : AR5K_USEC_5211)
- #define AR5K_USEC_1 0x0000007f /* clock cycles for 1us */
- #define AR5K_USEC_1_S 0
- #define AR5K_USEC_32 0x00003f80 /* clock cycles for 1us while on 32MHz clock */
- #define AR5K_USEC_32_S 7
- #define AR5K_USEC_TX_…