/drivers/net/wireless/ath/ath5k/reg.h

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  1. /*
  2. * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
  3. * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
  4. * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
  5. *
  6. * Permission to use, copy, modify, and distribute this software for any
  7. * purpose with or without fee is hereby granted, provided that the above
  8. * copyright notice and this permission notice appear in all copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17. *
  18. */
  19. /*
  20. * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k
  21. * maintained by Reyk Floeter
  22. *
  23. * I tried to document those registers by looking at ar5k code, some
  24. * 802.11 (802.11e mostly) papers and by reading various public available
  25. * Atheros presentations and papers like these:
  26. *
  27. * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
  28. *
  29. * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
  30. *
  31. * This file also contains register values found on a memory dump of
  32. * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
  33. * released by Atheros and on various debug messages found on the net.
  34. */
  35. #include "../reg.h"
  36. /*====MAC DMA REGISTERS====*/
  37. /*
  38. * AR5210-Specific TXDP registers
  39. * 5210 has only 2 transmit queues so no DCU/QCU, just
  40. * 2 transmit descriptor pointers...
  41. */
  42. #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
  43. #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
  44. /*
  45. * Mac Control Register
  46. */
  47. #define AR5K_CR 0x0008 /* Register Address */
  48. #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
  49. #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
  50. #define AR5K_CR_RXE 0x00000004 /* RX Enable */
  51. #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
  52. #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
  53. #define AR5K_CR_RXD 0x00000020 /* RX Disable */
  54. #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
  55. /*
  56. * RX Descriptor Pointer register
  57. */
  58. #define AR5K_RXDP 0x000c
  59. /*
  60. * Configuration and status register
  61. */
  62. #define AR5K_CFG 0x0014 /* Register Address */
  63. #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */
  64. #define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */
  65. #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */
  66. #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */
  67. #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */
  68. #define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */
  69. #define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */
  70. #define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */
  71. #define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */
  72. #define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */
  73. #define AR5K_CFG_TXCNT_S 11
  74. #define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */
  75. #define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */
  76. #define AR5K_CFG_PCI_THRES 0x00060000 /* PCI Master req q threshold [5211+] */
  77. #define AR5K_CFG_PCI_THRES_S 17
  78. /*
  79. * Interrupt enable register
  80. */
  81. #define AR5K_IER 0x0024 /* Register Address */
  82. #define AR5K_IER_DISABLE 0x00000000 /* Disable card interrupts */
  83. #define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */
  84. /*
  85. * 0x0028 is Beacon Control Register on 5210
  86. * and first RTS duration register on 5211
  87. */
  88. /*
  89. * Beacon control register [5210]
  90. */
  91. #define AR5K_BCR 0x0028 /* Register Address */
  92. #define AR5K_BCR_AP 0x00000000 /* AP mode */
  93. #define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */
  94. #define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */
  95. #define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */
  96. #define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */
  97. #define AR5K_BCR_BCGET 0x00000010
  98. /*
  99. * First RTS duration register [5211]
  100. */
  101. #define AR5K_RTSD0 0x0028 /* Register Address */
  102. #define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */
  103. #define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */
  104. #define AR5K_RTSD0_9 0x0000ff00 /* 9Mb*/
  105. #define AR5K_RTSD0_9_S 8
  106. #define AR5K_RTSD0_12 0x00ff0000 /* 12Mb*/
  107. #define AR5K_RTSD0_12_S 16
  108. #define AR5K_RTSD0_18 0xff000000 /* 16Mb*/
  109. #define AR5K_RTSD0_18_S 24
  110. /*
  111. * 0x002c is Beacon Status Register on 5210
  112. * and second RTS duration register on 5211
  113. */
  114. /*
  115. * Beacon status register [5210]
  116. *
  117. * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR
  118. * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning
  119. * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR).
  120. * So SNAPPEDBCRVALID should also stand for "snapped BCR -values- valid", so i
  121. * renamed it to SNAPSHOTSVALID to make more sense. I really have no idea what
  122. * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR.
  123. */
  124. #define AR5K_BSR 0x002c /* Register Address */
  125. #define AR5K_BSR_BDLYSW 0x00000001 /* SW Beacon delay (?) */
  126. #define AR5K_BSR_BDLYDMA 0x00000002 /* DMA Beacon delay (?) */
  127. #define AR5K_BSR_TXQ1F 0x00000004 /* Beacon queue (1) finished */
  128. #define AR5K_BSR_ATIMDLY 0x00000008 /* ATIM delay (?) */
  129. #define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */
  130. #define AR5K_BSR_SNPBDMAE 0x00000200 /* Beacon DMA enabled (?) */
  131. #define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */
  132. #define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */
  133. #define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */
  134. #define AR5K_BSR_SWBA_CNT 0x00ff0000
  135. /*
  136. * Second RTS duration register [5211]
  137. */
  138. #define AR5K_RTSD1 0x002c /* Register Address */
  139. #define AR5K_RTSD1_24 0x000000ff /* 24Mb */
  140. #define AR5K_RTSD1_24_S 0
  141. #define AR5K_RTSD1_36 0x0000ff00 /* 36Mb */
  142. #define AR5K_RTSD1_36_S 8
  143. #define AR5K_RTSD1_48 0x00ff0000 /* 48Mb */
  144. #define AR5K_RTSD1_48_S 16
  145. #define AR5K_RTSD1_54 0xff000000 /* 54Mb */
  146. #define AR5K_RTSD1_54_S 24
  147. /*
  148. * Transmit configuration register
  149. */
  150. #define AR5K_TXCFG 0x0030 /* Register Address */
  151. #define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size (read) */
  152. #define AR5K_TXCFG_SDMAMR_S 0
  153. #define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */
  154. #define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */
  155. #define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Trigger level mask */
  156. #define AR5K_TXCFG_TXFULL_S 4
  157. #define AR5K_TXCFG_TXFULL_0B 0x00000000
  158. #define AR5K_TXCFG_TXFULL_64B 0x00000010
  159. #define AR5K_TXCFG_TXFULL_128B 0x00000020
  160. #define AR5K_TXCFG_TXFULL_192B 0x00000030
  161. #define AR5K_TXCFG_TXFULL_256B 0x00000040
  162. #define AR5K_TXCFG_TXCONT_EN 0x00000080
  163. #define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */
  164. #define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400 /* Enable jumbo tx descriptors [5211+] */
  165. #define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 /* Adhoc Beacon ATIM Policy */
  166. #define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 /* Disable ATIM window defer [5211+] */
  167. #define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */
  168. #define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */
  169. #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */
  170. #define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */
  171. #define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 /* Disable double buffering on DCU */
  172. #define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */
  173. /*
  174. * Receive configuration register
  175. */
  176. #define AR5K_RXCFG 0x0034 /* Register Address */
  177. #define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size (write) */
  178. #define AR5K_RXCFG_SDMAMW_S 0
  179. #define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */
  180. #define AR5K_RXCFG_DEF_ANTENNA 0x00000010 /* Default antenna (?) */
  181. #define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo rx descriptors [5211+] */
  182. #define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames [5211+] */
  183. #define AR5K_RXCFG_SLE_ENTRY 0x00000080 /* Sleep entry policy */
  184. /*
  185. * Receive jumbo descriptor last address register
  186. * Only found in 5211 (?)
  187. */
  188. #define AR5K_RXJLA 0x0038
  189. /*
  190. * MIB control register
  191. */
  192. #define AR5K_MIBC 0x0040 /* Register Address */
  193. #define AR5K_MIBC_COW 0x00000001 /* Counter Overflow Warning */
  194. #define AR5K_MIBC_FMC 0x00000002 /* Freeze MIB Counters */
  195. #define AR5K_MIBC_CMC 0x00000004 /* Clear MIB Counters */
  196. #define AR5K_MIBC_MCS 0x00000008 /* MIB counter strobe, increment all */
  197. /*
  198. * Timeout prescale register
  199. */
  200. #define AR5K_TOPS 0x0044
  201. #define AR5K_TOPS_M 0x0000ffff
  202. /*
  203. * Receive timeout register (no frame received)
  204. */
  205. #define AR5K_RXNOFRM 0x0048
  206. #define AR5K_RXNOFRM_M 0x000003ff
  207. /*
  208. * Transmit timeout register (no frame sent)
  209. */
  210. #define AR5K_TXNOFRM 0x004c
  211. #define AR5K_TXNOFRM_M 0x000003ff
  212. #define AR5K_TXNOFRM_QCU 0x000ffc00
  213. #define AR5K_TXNOFRM_QCU_S 10
  214. /*
  215. * Receive frame gap timeout register
  216. */
  217. #define AR5K_RPGTO 0x0050
  218. #define AR5K_RPGTO_M 0x000003ff
  219. /*
  220. * Receive frame count limit register
  221. */
  222. #define AR5K_RFCNT 0x0054
  223. #define AR5K_RFCNT_M 0x0000001f /* [5211+] (?) */
  224. #define AR5K_RFCNT_RFCL 0x0000000f /* [5210] */
  225. /*
  226. * Misc settings register
  227. * (reserved0-3)
  228. */
  229. #define AR5K_MISC 0x0058 /* Register Address */
  230. #define AR5K_MISC_DMA_OBS_M 0x000001e0
  231. #define AR5K_MISC_DMA_OBS_S 5
  232. #define AR5K_MISC_MISC_OBS_M 0x00000e00
  233. #define AR5K_MISC_MISC_OBS_S 9
  234. #define AR5K_MISC_MAC_OBS_LSB_M 0x00007000
  235. #define AR5K_MISC_MAC_OBS_LSB_S 12
  236. #define AR5K_MISC_MAC_OBS_MSB_M 0x00038000
  237. #define AR5K_MISC_MAC_OBS_MSB_S 15
  238. #define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */
  239. #define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */
  240. /*
  241. * QCU/DCU clock gating register (5311)
  242. * (reserved4-5)
  243. */
  244. #define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */
  245. #define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */
  246. #define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */
  247. /*
  248. * Interrupt Status Registers
  249. *
  250. * For 5210 there is only one status register but for
  251. * 5211/5212 we have one primary and 4 secondary registers.
  252. * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212.
  253. * Most of these bits are common for all chipsets.
  254. */
  255. #define AR5K_ISR 0x001c /* Register Address [5210] */
  256. #define AR5K_PISR 0x0080 /* Register Address [5211+] */
  257. #define AR5K_ISR_RXOK 0x00000001 /* Frame successfully received */
  258. #define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */
  259. #define AR5K_ISR_RXERR 0x00000004 /* Receive error */
  260. #define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */
  261. #define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */
  262. #define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */
  263. #define AR5K_ISR_TXOK 0x00000040 /* Frame successfully transmitted */
  264. #define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */
  265. #define AR5K_ISR_TXERR 0x00000100 /* Transmit error */
  266. #define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout) */
  267. #define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */
  268. #define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */
  269. #define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */
  270. #define AR5K_ISR_SWI 0x00002000 /* Software interrupt */
  271. #define AR5K_ISR_RXPHY 0x00004000 /* PHY error */
  272. #define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */
  273. #define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */
  274. #define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
  275. #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */
  276. #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
  277. #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */
  278. #define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */
  279. #define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */
  280. #define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */
  281. #define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */
  282. #define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */
  283. #define AR5K_ISR_TIM 0x00800000 /* [5211+] */
  284. #define AR5K_ISR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
  285. CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
  286. #define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */
  287. #define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */
  288. #define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */
  289. #define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */
  290. /*
  291. * Secondary status registers [5211+] (0 - 4)
  292. *
  293. * These give the status for each QCU, only QCUs 0-9 are
  294. * represented.
  295. */
  296. #define AR5K_SISR0 0x0084 /* Register Address [5211+] */
  297. #define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */
  298. #define AR5K_SISR0_QCU_TXOK_S 0
  299. #define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */
  300. #define AR5K_SISR0_QCU_TXDESC_S 16
  301. #define AR5K_SISR1 0x0088 /* Register Address [5211+] */
  302. #define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */
  303. #define AR5K_SISR1_QCU_TXERR_S 0
  304. #define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */
  305. #define AR5K_SISR1_QCU_TXEOL_S 16
  306. #define AR5K_SISR2 0x008c /* Register Address [5211+] */
  307. #define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */
  308. #define AR5K_SISR2_QCU_TXURN_S 0
  309. #define AR5K_SISR2_MCABT 0x00010000 /* Master Cycle Abort */
  310. #define AR5K_SISR2_SSERR 0x00020000 /* Signaled System Error */
  311. #define AR5K_SISR2_DPERR 0x00040000 /* Bus parity error */
  312. #define AR5K_SISR2_TIM 0x01000000 /* [5212+] */
  313. #define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */
  314. #define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */
  315. #define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
  316. #define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
  317. #define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */
  318. #define AR5K_SISR2_TSFOOR 0x80000000 /* TSF OOR (?) */
  319. #define AR5K_SISR3 0x0090 /* Register Address [5211+] */
  320. #define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */
  321. #define AR5K_SISR3_QCBRORN_S 0
  322. #define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */
  323. #define AR5K_SISR3_QCBRURN_S 16
  324. #define AR5K_SISR4 0x0094 /* Register Address [5211+] */
  325. #define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */
  326. #define AR5K_SISR4_QTRIG_S 0
  327. /*
  328. * Shadow read-and-clear interrupt status registers [5211+]
  329. */
  330. #define AR5K_RAC_PISR 0x00c0 /* Read and clear PISR */
  331. #define AR5K_RAC_SISR0 0x00c4 /* Read and clear SISR0 */
  332. #define AR5K_RAC_SISR1 0x00c8 /* Read and clear SISR1 */
  333. #define AR5K_RAC_SISR2 0x00cc /* Read and clear SISR2 */
  334. #define AR5K_RAC_SISR3 0x00d0 /* Read and clear SISR3 */
  335. #define AR5K_RAC_SISR4 0x00d4 /* Read and clear SISR4 */
  336. /*
  337. * Interrupt Mask Registers
  338. *
  339. * As with ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary
  340. * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match.
  341. */
  342. #define AR5K_IMR 0x0020 /* Register Address [5210] */
  343. #define AR5K_PIMR 0x00a0 /* Register Address [5211+] */
  344. #define AR5K_IMR_RXOK 0x00000001 /* Frame successfully received*/
  345. #define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/
  346. #define AR5K_IMR_RXERR 0x00000004 /* Receive error*/
  347. #define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/
  348. #define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/
  349. #define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/
  350. #define AR5K_IMR_TXOK 0x00000040 /* Frame successfully transmitted*/
  351. #define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/
  352. #define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/
  353. #define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout)*/
  354. #define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/
  355. #define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/
  356. #define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/
  357. #define AR5K_IMR_SWI 0x00002000 /* Software interrupt */
  358. #define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/
  359. #define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */
  360. #define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/
  361. #define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
  362. #define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/
  363. #define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
  364. #define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */
  365. #define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */
  366. #define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/
  367. #define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */
  368. #define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */
  369. #define AR5K_IMR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */
  370. #define AR5K_IMR_TIM 0x00800000 /* [5211+] */
  371. #define AR5K_IMR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
  372. CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
  373. #define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/
  374. #define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */
  375. #define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */
  376. #define AR5K_IMR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */
  377. /*
  378. * Secondary interrupt mask registers [5211+] (0 - 4)
  379. */
  380. #define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */
  381. #define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */
  382. #define AR5K_SIMR0_QCU_TXOK_S 0
  383. #define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */
  384. #define AR5K_SIMR0_QCU_TXDESC_S 16
  385. #define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */
  386. #define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */
  387. #define AR5K_SIMR1_QCU_TXERR_S 0
  388. #define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */
  389. #define AR5K_SIMR1_QCU_TXEOL_S 16
  390. #define AR5K_SIMR2 0x00ac /* Register Address [5211+] */
  391. #define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */
  392. #define AR5K_SIMR2_QCU_TXURN_S 0
  393. #define AR5K_SIMR2_MCABT 0x00010000 /* Master Cycle Abort */
  394. #define AR5K_SIMR2_SSERR 0x00020000 /* Signaled System Error */
  395. #define AR5K_SIMR2_DPERR 0x00040000 /* Bus parity error */
  396. #define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */
  397. #define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */
  398. #define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */
  399. #define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
  400. #define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
  401. #define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */
  402. #define AR5K_SIMR2_TSFOOR 0x80000000 /* TSF OOR (?) */
  403. #define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */
  404. #define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */
  405. #define AR5K_SIMR3_QCBRORN_S 0
  406. #define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */
  407. #define AR5K_SIMR3_QCBRURN_S 16
  408. #define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */
  409. #define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */
  410. #define AR5K_SIMR4_QTRIG_S 0
  411. /*
  412. * DMA Debug registers 0-7
  413. * 0xe0 - 0xfc
  414. */
  415. /*
  416. * Decompression mask registers [5212+]
  417. */
  418. #define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (index) */
  419. #define AR5K_DCM_DATA 0x0404 /*Decompression mask data */
  420. /*
  421. * Wake On Wireless pattern control register [5212+]
  422. */
  423. #define AR5K_WOW_PCFG 0x0410 /* Register Address */
  424. #define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 /* Pattern match enable */
  425. #define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 /* Long frame policy */
  426. #define AR5K_WOW_PCFG_WOBMISS 0x00000004 /* Wake on bea(con) miss (?) */
  427. #define AR5K_WOW_PCFG_PAT_0_EN 0x00000100 /* Enable pattern 0 */
  428. #define AR5K_WOW_PCFG_PAT_1_EN 0x00000200 /* Enable pattern 1 */
  429. #define AR5K_WOW_PCFG_PAT_2_EN 0x00000400 /* Enable pattern 2 */
  430. #define AR5K_WOW_PCFG_PAT_3_EN 0x00000800 /* Enable pattern 3 */
  431. #define AR5K_WOW_PCFG_PAT_4_EN 0x00001000 /* Enable pattern 4 */
  432. #define AR5K_WOW_PCFG_PAT_5_EN 0x00002000 /* Enable pattern 5 */
  433. /*
  434. * Wake On Wireless pattern index register (?) [5212+]
  435. */
  436. #define AR5K_WOW_PAT_IDX 0x0414
  437. /*
  438. * Wake On Wireless pattern data register [5212+]
  439. */
  440. #define AR5K_WOW_PAT_DATA 0x0418 /* Register Address */
  441. #define AR5K_WOW_PAT_DATA_0_3_V 0x00000001 /* Pattern 0, 3 value */
  442. #define AR5K_WOW_PAT_DATA_1_4_V 0x00000100 /* Pattern 1, 4 value */
  443. #define AR5K_WOW_PAT_DATA_2_5_V 0x00010000 /* Pattern 2, 5 value */
  444. #define AR5K_WOW_PAT_DATA_0_3_M 0x01000000 /* Pattern 0, 3 mask */
  445. #define AR5K_WOW_PAT_DATA_1_4_M 0x04000000 /* Pattern 1, 4 mask */
  446. #define AR5K_WOW_PAT_DATA_2_5_M 0x10000000 /* Pattern 2, 5 mask */
  447. /*
  448. * Decompression configuration registers [5212+]
  449. */
  450. #define AR5K_DCCFG 0x0420 /* Register Address */
  451. #define AR5K_DCCFG_GLOBAL_EN 0x00000001 /* Enable decompression on all queues */
  452. #define AR5K_DCCFG_BYPASS_EN 0x00000002 /* Bypass decompression */
  453. #define AR5K_DCCFG_BCAST_EN 0x00000004 /* Enable decompression for bcast frames */
  454. #define AR5K_DCCFG_MCAST_EN 0x00000008 /* Enable decompression for mcast frames */
  455. /*
  456. * Compression configuration registers [5212+]
  457. */
  458. #define AR5K_CCFG 0x0600 /* Register Address */
  459. #define AR5K_CCFG_WINDOW_SIZE 0x00000007 /* Compression window size */
  460. #define AR5K_CCFG_CPC_EN 0x00000008 /* Enable performance counters */
  461. #define AR5K_CCFG_CCU 0x0604 /* Register Address */
  462. #define AR5K_CCFG_CCU_CUP_EN 0x00000001 /* CCU Catchup enable */
  463. #define AR5K_CCFG_CCU_CREDIT 0x00000002 /* CCU Credit (field) */
  464. #define AR5K_CCFG_CCU_CD_THRES 0x00000080 /* CCU Cyc(lic?) debt threshold (field) */
  465. #define AR5K_CCFG_CCU_CUP_LCNT 0x00010000 /* CCU Catchup lit(?) count */
  466. #define AR5K_CCFG_CCU_INIT 0x00100200 /* Initial value during reset */
  467. /*
  468. * Compression performance counter registers [5212+]
  469. */
  470. #define AR5K_CPC0 0x0610 /* Compression performance counter 0 */
  471. #define AR5K_CPC1 0x0614 /* Compression performance counter 1*/
  472. #define AR5K_CPC2 0x0618 /* Compression performance counter 2 */
  473. #define AR5K_CPC3 0x061c /* Compression performance counter 3 */
  474. #define AR5K_CPCOVF 0x0620 /* Compression performance overflow */
  475. /*
  476. * Queue control unit (QCU) registers [5211+]
  477. *
  478. * Card has 12 TX Queues but i see that only 0-9 are used (?)
  479. * both in binary HAL (see ah.h) and ar5k. Each queue has it's own
  480. * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
  481. * configuration register (0x08c0 - 0x08ec), a ready time configuration
  482. * register (0x0900 - 0x092c), a misc configuration register (0x09c0 -
  483. * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some
  484. * global registers, QCU transmit enable/disable and "one shot arm (?)"
  485. * set/clear, which contain status for all queues (we shift by 1 for each
  486. * queue). To access these registers easily we define some macros here
  487. * that are used inside HAL. For more infos check out *_tx_queue functs.
  488. */
  489. /*
  490. * Generic QCU Register access macros
  491. */
  492. #define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r)
  493. #define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q))
  494. #define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q))
  495. /*
  496. * QCU Transmit descriptor pointer registers
  497. */
  498. #define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */
  499. #define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)
  500. /*
  501. * QCU Transmit enable register
  502. */
  503. #define AR5K_QCU_TXE 0x0840
  504. #define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)
  505. #define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)
  506. /*
  507. * QCU Transmit disable register
  508. */
  509. #define AR5K_QCU_TXD 0x0880
  510. #define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)
  511. #define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)
  512. /*
  513. * QCU Constant Bit Rate configuration registers
  514. */
  515. #define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */
  516. #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */
  517. #define AR5K_QCU_CBRCFG_INTVAL_S 0
  518. #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */
  519. #define AR5K_QCU_CBRCFG_ORN_THRES_S 24
  520. #define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)
  521. /*
  522. * QCU Ready time configuration registers
  523. */
  524. #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */
  525. #define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */
  526. #define AR5K_QCU_RDYTIMECFG_INTVAL_S 0
  527. #define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */
  528. #define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)
  529. /*
  530. * QCU one shot arm set registers
  531. */
  532. #define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */
  533. #define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff
  534. /*
  535. * QCU one shot arm clear registers
  536. */
  537. #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */
  538. #define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff
  539. /*
  540. * QCU misc registers
  541. */
  542. #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */
  543. #define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame scheduling mask */
  544. #define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */
  545. #define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */
  546. #define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated */
  547. #define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* TIMT gated */
  548. #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated */
  549. #define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */
  550. #define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */
  551. #define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */
  552. #define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */
  553. #define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR expired threshold enabled */
  554. #define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME expired or VEOL */
  555. #define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */
  556. #define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */
  557. #define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */
  558. #define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)
  559. /*
  560. * QCU status registers
  561. */
  562. #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */
  563. #define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */
  564. #define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter */
  565. #define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)
  566. /*
  567. * QCU ready time shutdown register
  568. */
  569. #define AR5K_QCU_RDYTIMESHDN 0x0a40
  570. #define AR5K_QCU_RDYTIMESHDN_M 0x000003ff
  571. /*
  572. * QCU compression buffer base registers [5212+]
  573. */
  574. #define AR5K_QCU_CBB_SELECT 0x0b00
  575. #define AR5K_QCU_CBB_ADDR 0x0b04
  576. #define AR5K_QCU_CBB_ADDR_S 9
  577. /*
  578. * QCU compression buffer configuration register [5212+]
  579. * (buffer size)
  580. */
  581. #define AR5K_QCU_CBCFG 0x0b08
  582. /*
  583. * Distributed Coordination Function (DCF) control unit (DCU)
  584. * registers [5211+]
  585. *
  586. * These registers control the various characteristics of each queue
  587. * for 802.11e (WME) compatibility so they go together with
  588. * QCU registers in pairs. For each queue we have a QCU mask register,
  589. * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),
  590. * a retry limit register (0x1080 - 0x10ac), a channel time register
  591. * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and
  592. * a sequence number register (0x1140 - 0x116c). It seems that "global"
  593. * registers here affect all queues (see use of DCU_GBL_IFS_SLOT in ar5k).
  594. * We use the same macros here for easier register access.
  595. *
  596. */
  597. /*
  598. * DCU QCU mask registers
  599. */
  600. #define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */
  601. #define AR5K_DCU_QCUMASK_M 0x000003ff
  602. #define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)
  603. /*
  604. * DCU local Inter Frame Space settings register
  605. */
  606. #define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */
  607. #define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /* Minimum Contention Window */
  608. #define AR5K_DCU_LCL_IFS_CW_MIN_S 0
  609. #define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /* Maximum Contention Window */
  610. #define AR5K_DCU_LCL_IFS_CW_MAX_S 10
  611. #define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */
  612. #define AR5K_DCU_LCL_IFS_AIFS_S 20
  613. #define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc /* Anything above that can cause DCU to hang */
  614. #define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)
  615. /*
  616. * DCU retry limit registers
  617. * all these fields don't allow zero values
  618. */
  619. #define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */
  620. #define AR5K_DCU_RETRY_LMT_RTS 0x0000000f /* RTS failure limit. Transmission fails if no CTS is received for this number of times */
  621. #define AR5K_DCU_RETRY_LMT_RTS_S 0
  622. #define AR5K_DCU_RETRY_LMT_STA_RTS 0x00003f00 /* STA RTS failure limit. If exceeded CW reset */
  623. #define AR5K_DCU_RETRY_LMT_STA_RTS_S 8
  624. #define AR5K_DCU_RETRY_LMT_STA_DATA 0x000fc000 /* STA data failure limit. If exceeded CW reset. */
  625. #define AR5K_DCU_RETRY_LMT_STA_DATA_S 14
  626. #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)
  627. /*
  628. * DCU channel time registers
  629. */
  630. #define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */
  631. #define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */
  632. #define AR5K_DCU_CHAN_TIME_DUR_S 0
  633. #define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */
  634. #define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)
  635. /*
  636. * DCU misc registers [5211+]
  637. *
  638. * Note: Arbiter lockout control controls the
  639. * behaviour on low priority queues when we have multiple queues
  640. * with pending frames. Intra-frame lockout means we wait until
  641. * the queue's current frame transmits (with post frame backoff and bursting)
  642. * before we transmit anything else and global lockout means we
  643. * wait for the whole queue to finish before higher priority queues
  644. * can transmit (this is used on beacon and CAB queues).
  645. * No lockout means there is no special handling.
  646. */
  647. #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */
  648. #define AR5K_DCU_MISC_BACKOFF 0x0000003f /* Mask for backoff threshold */
  649. #define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040 /* End of transmission series
  650. station RTS/data failure count
  651. reset policy (?) */
  652. #define AR5K_DCU_MISC_ETS_CW_POL 0x00000080 /* End of transmission series
  653. CW reset policy */
  654. #define AR5K_DCU_MISC_FRAG_WAIT 0x00000100 /* Wait for next fragment */
  655. #define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */
  656. #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */
  657. #define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */
  658. #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */
  659. #define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */
  660. #define AR5K_DCU_MISC_VIRTCOL_NORMAL 0
  661. #define AR5K_DCU_MISC_VIRTCOL_IGNORE 1
  662. #define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */
  663. #define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */
  664. #define AR5K_DCU_MISC_ARBLOCK_CTL_S 17
  665. #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */
  666. #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */
  667. #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */
  668. #define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 /* Ignore Arbiter lockout */
  669. #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment */
  670. #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */
  671. #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision cw policy */
  672. #define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS policy (?) */
  673. #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */
  674. #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)
  675. /*
  676. * DCU frame sequence number registers
  677. */
  678. #define AR5K_DCU_SEQNUM_BASE 0x1140
  679. #define AR5K_DCU_SEQNUM_M 0x00000fff
  680. #define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
  681. /*
  682. * DCU global IFS SIFS register
  683. */
  684. #define AR5K_DCU_GBL_IFS_SIFS 0x1030
  685. #define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff
  686. /*
  687. * DCU global IFS slot interval register
  688. */
  689. #define AR5K_DCU_GBL_IFS_SLOT 0x1070
  690. #define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff
  691. /*
  692. * DCU global IFS EIFS register
  693. */
  694. #define AR5K_DCU_GBL_IFS_EIFS 0x10b0
  695. #define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff
  696. /*
  697. * DCU global IFS misc register
  698. *
  699. * LFSR stands for Linear Feedback Shift Register
  700. * and it's used for generating pseudo-random
  701. * number sequences.
  702. *
  703. * (If i understand correctly, random numbers are
  704. * used for idle sensing -multiplied with cwmin/max etc-)
  705. */
  706. #define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */
  707. #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 /* LFSR Slice Select */
  708. #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */
  709. #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */
  710. #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC_S 4
  711. #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */
  712. #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10
  713. #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */
  714. #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFS cnt reset policy (?) */
  715. #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */
  716. #define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */
  717. /*
  718. * DCU frame prefetch control register
  719. */
  720. #define AR5K_DCU_FP 0x1230 /* Register Address */
  721. #define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */
  722. #define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */
  723. #define AR5K_DCU_FP_BURST_DCU_EN 0x00000020 /* Enable burst prefetch on DCU (?) */
  724. /*
  725. * DCU transmit pause control/status register
  726. */
  727. #define AR5K_DCU_TXP 0x1270 /* Register Address */
  728. #define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask */
  729. #define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status */
  730. /*
  731. * DCU transmit filter table 0 (32 entries)
  732. * each entry contains a 32bit slice of the
  733. * 128bit tx filter for each DCU (4 slices per DCU)
  734. */
  735. #define AR5K_DCU_TX_FILTER_0_BASE 0x1038
  736. #define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
  737. /*
  738. * DCU transmit filter table 1 (16 entries)
  739. */
  740. #define AR5K_DCU_TX_FILTER_1_BASE 0x103c
  741. #define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
  742. /*
  743. * DCU clear transmit filter register
  744. */
  745. #define AR5K_DCU_TX_FILTER_CLR 0x143c
  746. /*
  747. * DCU set transmit filter register
  748. */
  749. #define AR5K_DCU_TX_FILTER_SET 0x147c
  750. /*
  751. * Reset control register
  752. */
  753. #define AR5K_RESET_CTL 0x4000 /* Register Address */
  754. #define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */
  755. #define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */
  756. #define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */
  757. #define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */
  758. #define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */
  759. #define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */
  760. /*
  761. * Sleep control register
  762. */
  763. #define AR5K_SLEEP_CTL 0x4004 /* Register Address */
  764. #define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */
  765. #define AR5K_SLEEP_CTL_SLDUR_S 0
  766. #define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */
  767. #define AR5K_SLEEP_CTL_SLE_S 16
  768. #define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */
  769. #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */
  770. #define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 /* Normal sleep policy */
  771. #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */
  772. #define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 /* Sleep duration timing policy */
  773. #define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 /* Sleep duration write policy */
  774. #define AR5K_SLEEP_CTL_SLE_POL 0x00100000 /* Sleep policy mode */
  775. /*
  776. * Interrupt pending register
  777. */
  778. #define AR5K_INTPEND 0x4008
  779. #define AR5K_INTPEND_M 0x00000001
  780. /*
  781. * Sleep force register
  782. */
  783. #define AR5K_SFR 0x400c
  784. #define AR5K_SFR_EN 0x00000001
  785. /*
  786. * PCI configuration register
  787. * TODO: Fix LED stuff
  788. */
  789. #define AR5K_PCICFG 0x4010 /* Register Address */
  790. #define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */
  791. #define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock */
  792. #define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */
  793. #define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */
  794. #define AR5K_PCICFG_EESIZE_S 3
  795. #define AR5K_PCICFG_EESIZE_4K 0 /* 4K */
  796. #define AR5K_PCICFG_EESIZE_8K 1 /* 8K */
  797. #define AR5K_PCICFG_EESIZE_16K 2 /* 16K */
  798. #define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size [5211+] */
  799. #define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */
  800. #define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */
  801. #define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */
  802. #define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */
  803. #define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */
  804. #define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix */
  805. #define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep */
  806. #define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */
  807. #define AR5K_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core retry fix */
  808. #define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even with pending interrupts*/
  809. #define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */
  810. #define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */
  811. #define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */
  812. #define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */
  813. #define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */
  814. #define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */
  815. #define AR5K_PCICFG_LEDBLINK 0x00700000 /* Led blink rate */
  816. #define AR5K_PCICFG_LEDBLINK_S 20
  817. #define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slowest led blink rate [5211+] */
  818. #define AR5K_PCICFG_LEDSTATE \
  819. (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \
  820. AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
  821. #define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate */
  822. #define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24
  823. /*
  824. * "General Purpose Input/Output" (GPIO) control register
  825. *
  826. * I'm not sure about this but after looking at the code
  827. * for all chipsets here is what i got.
  828. *
  829. * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits)
  830. * Mode 0 -> always input
  831. * Mode 1 -> output when GPIODO for this GPIO is set to 0
  832. * Mode 2 -> output when GPIODO for this GPIO is set to 1
  833. * Mode 3 -> always output
  834. *
  835. * For more infos check out get_gpio/set_gpio and
  836. * set_gpio_input/set_gpio_output functs.
  837. * For more infos on gpio interrupt check out set_gpio_intr.
  838. */
  839. #define AR5K_NUM_GPIO 6
  840. #define AR5K_GPIOCR 0x4014 /* Register Address */
  841. #define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */
  842. #define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is low */
  843. #define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is high */
  844. #define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */
  845. #define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */
  846. #define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */
  847. #define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /* Mode 3 for pin n */
  848. #define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /* Interrupt for GPIO pin n */
  849. /*
  850. * "General Purpose Input/Output" (GPIO) data output register
  851. */
  852. #define AR5K_GPIODO 0x4018
  853. /*
  854. * "General Purpose Input/Output" (GPIO) data input register
  855. */
  856. #define AR5K_GPIODI 0x401c
  857. #define AR5K_GPIODI_M 0x0000002f
  858. /*
  859. * Silicon revision register
  860. */
  861. #define AR5K_SREV 0x4020 /* Register Address */
  862. #define AR5K_SREV_REV 0x0000000f /* Mask for revision */
  863. #define AR5K_SREV_REV_S 0
  864. #define AR5K_SREV_VER 0x000000ff /* Mask for version */
  865. #define AR5K_SREV_VER_S 4
  866. /*
  867. * TXE write posting register
  868. */
  869. #define AR5K_TXEPOST 0x4028
  870. /*
  871. * QCU sleep mask
  872. */
  873. #define AR5K_QCU_SLEEP_MASK 0x402c
  874. /* 0x4068 is compression buffer configuration
  875. * register on 5414 and pm configuration register
  876. * on 5424 and newer pci-e chips. */
  877. /*
  878. * Compression buffer configuration
  879. * register (enable/disable) [5414]
  880. */
  881. #define AR5K_5414_CBCFG 0x4068
  882. #define AR5K_5414_CBCFG_BUF_DIS 0x10 /* Disable buffer */
  883. /*
  884. * PCI-E Power management configuration
  885. * and status register [5424+]
  886. */
  887. #define AR5K_PCIE_PM_CTL 0x4068 /* Register address */
  888. /* Only 5424 */
  889. #define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 /* enable PCIe core enter L1
  890. when d2_sleep_en is asserted */
  891. #define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 /* Clear L0 and L0S counters */
  892. #define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 /* Start L0 nd L0S counters */
  893. #define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 /* Enable reset when link goes
  894. down */
  895. /* Wake On Wireless */
  896. #define AR5K_PCIE_PM_CTL_PME_EN 0x00000010 /* PME Enable */
  897. #define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 /* Aux power detect */
  898. #define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 /* Clear PME */
  899. #define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080
  900. #define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100
  901. #define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200
  902. #define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400
  903. /*
  904. * PCI-E Workaround enable register
  905. */
  906. #define AR5K_PCIE_WAEN 0x407c
  907. /*
  908. * PCI-E Serializer/Deserializer
  909. * registers
  910. */
  911. #define AR5K_PCIE_SERDES 0x4080
  912. #define AR5K_PCIE_SERDES_RESET 0x4084
  913. /*====EEPROM REGISTERS====*/
  914. /*
  915. * EEPROM access registers
  916. *
  917. * Here we got a difference between 5210/5211-12
  918. * read data register for 5210 is at 0x6800 and
  919. * status register is at 0x6c00. There is also
  920. * no eeprom command register on 5210 and the
  921. * offsets are different.
  922. *
  923. * To read eeprom data for a specific offset:
  924. * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
  925. * read AR5K_EEPROM_BASE +(4 * offset)
  926. * check the eeprom status register
  927. * and read eeprom data register.
  928. *
  929. * 5211 - write offset to AR5K_EEPROM_BASE
  930. * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD
  931. * check the eeprom status register
  932. * and read eeprom data register.
  933. *
  934. * To write eeprom data for a specific offset:
  935. * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
  936. * write data to AR5K_EEPROM_BASE +(4 * offset)
  937. * check the eeprom status register
  938. * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD
  939. * 5212 write offset to AR5K_EEPROM_BASE
  940. * write data to data register
  941. * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD
  942. * check the eeprom status register
  943. *
  944. * For more infos check eeprom_* functs and the ar5k.c
  945. * file posted in madwifi-devel mailing list.
  946. * http://sourceforge.net/mailarchive/message.php?msg_id=8966525
  947. *
  948. */
  949. #define AR5K_EEPROM_BASE 0x6000
  950. /*
  951. * EEPROM data register
  952. */
  953. #define AR5K_EEPROM_DATA_5211 0x6004
  954. #define AR5K_EEPROM_DATA_5210 0x6800
  955. #define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \
  956. AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)
  957. /*
  958. * EEPROM command register
  959. */
  960. #define AR5K_EEPROM_CMD 0x6008 /* Register Address */
  961. #define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */
  962. #define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */
  963. #define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */
  964. /*
  965. * EEPROM status register
  966. */
  967. #define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */
  968. #define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */
  969. #define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \
  970. AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)
  971. #define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */
  972. #define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */
  973. #define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */
  974. #define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */
  975. /*
  976. * EEPROM config register
  977. */
  978. #define AR5K_EEPROM_CFG 0x6010 /* Register Address */
  979. #define AR5K_EEPROM_CFG_SIZE 0x00000003 /* Size determination override */
  980. #define AR5K_EEPROM_CFG_SIZE_AUTO 0
  981. #define AR5K_EEPROM_CFG_SIZE_4KBIT 1
  982. #define AR5K_EEPROM_CFG_SIZE_8KBIT 2
  983. #define AR5K_EEPROM_CFG_SIZE_16KBIT 3
  984. #define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */
  985. #define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */
  986. #define AR5K_EEPROM_CFG_CLK_RATE_S 3
  987. #define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0
  988. #define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1
  989. #define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2
  990. #define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protection key */
  991. #define AR5K_EEPROM_CFG_PROT_KEY_S 8
  992. #define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */
  993. /*
  994. * TODO: Wake On Wireless registers
  995. * Range 0x7000 - 0x7ce0
  996. */
  997. /*
  998. * Protocol Control Unit (PCU) registers
  999. */
  1000. /*
  1001. * Used for checking initial register writes
  1002. * during channel reset (see reset func)
  1003. */
  1004. #define AR5K_PCU_MIN 0x8000
  1005. #define AR5K_PCU_MAX 0x8fff
  1006. /*
  1007. * First station id register (Lower 32 bits of MAC address)
  1008. */
  1009. #define AR5K_STA_ID0 0x8000
  1010. #define AR5K_STA_ID0_ARRD_L32 0xffffffff
  1011. /*
  1012. * Second station id register (Upper 16 bits of MAC address + PCU settings)
  1013. */
  1014. #define AR5K_STA_ID1 0x8004 /* Register Address */
  1015. #define AR5K_STA_ID1_ADDR_U16 0x0000ffff /* Upper 16 bits of MAC address */
  1016. #define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */
  1017. #define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */
  1018. #define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting */
  1019. #define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */
  1020. #define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */
  1021. #define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */
  1022. #define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/
  1023. #define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \
  1024. AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)
  1025. #define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */
  1026. #define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */
  1027. #define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */
  1028. #define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Rate to use for ACK/CTS. 0: highest mandatory rate <= RX rate; 1: 1Mbps in B mode */
  1029. #define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* 802.11b base rate. 0: 1, 2, 5.5 and 11Mbps; 1: 1 and 2Mbps. [5211+] */
  1030. #define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 /* Use def. antenna for self generated frames */
  1031. #define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */
  1032. #define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Look up key when key id != 0 */
  1033. #define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */
  1034. #define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 /* ??? */
  1035. #define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 /* Do key cache search for mcast frames */
  1036. #define AR5K_STA_ID1_ANTENNA_SETTINGS (AR5K_STA_ID1_DEFAULT_ANTENNA | \
  1037. AR5K_STA_ID1_DESC_ANTENNA | \
  1038. AR5K_STA_ID1_RTS_DEF_ANTENNA | \
  1039. AR5K_STA_ID1_SELFGEN_DEF_ANT)
  1040. /*
  1041. * First BSSID register (MAC address, lower 32bits)
  1042. */
  1043. #define AR5K_BSS_ID0 0x8008
  1044. /*
  1045. * Second BSSID register (MAC address in upper 16 bits)
  1046. *
  1047. * AID: Association ID
  1048. */
  1049. #define AR5K_BSS_ID1 0x800c
  1050. #define AR5K_BSS_ID1_AID 0xffff0000
  1051. #define AR5K_BSS_ID1_AID_S 16
  1052. /*
  1053. * Backoff slot time register
  1054. */
  1055. #define AR5K_SLOT_TIME 0x8010
  1056. /*
  1057. * ACK/CTS timeout register
  1058. */
  1059. #define AR5K_TIME_OUT 0x8014 /* Register Address */
  1060. #define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */
  1061. #define AR5K_TIME_OUT_ACK_S 0
  1062. #define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */
  1063. #define AR5K_TIME_OUT_CTS_S 16
  1064. /*
  1065. * RSSI threshold register
  1066. */
  1067. #define AR5K_RSSI_THR 0x8018 /* Register Address */
  1068. #define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */
  1069. #define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */
  1070. #define AR5K_RSSI_THR_BMISS_5210_S 8
  1071. #define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */
  1072. #define AR5K_RSSI_THR_BMISS_5211_S 8
  1073. #define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \
  1074. AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211)
  1075. #define AR5K_RSSI_THR_BMISS_S 8
  1076. /*
  1077. * 5210 has more PCU registers because there is no QCU/DCU
  1078. * so queue parameters are set here, this way a lot common
  1079. * registers have different address for 5210. To make things
  1080. * easier we define a macro based on ah->ah_version for common
  1081. * registers with different addresses and common flags.
  1082. */
  1083. /*
  1084. * Retry limit register
  1085. *
  1086. * Retry limit register for 5210 (no QCU/DCU so it's done in PCU)
  1087. */
  1088. #define AR5K_NODCU_RETRY_LMT 0x801c /* Register Address */
  1089. #define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */
  1090. #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0
  1091. #define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */
  1092. #define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4
  1093. #define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */
  1094. #define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8
  1095. #define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */
  1096. #define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14
  1097. #define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */
  1098. #define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20
  1099. /*
  1100. * Transmit latency register
  1101. */
  1102. #define AR5K_USEC_5210 0x8020 /* Register Address [5210] */
  1103. #define AR5K_USEC_5211 0x801c /* Register Address [5211+] */
  1104. #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \
  1105. AR5K_USEC_5210 : AR5K_USEC_5211)
  1106. #define AR5K_USEC_1 0x0000007f /* clock cycles for 1us */
  1107. #define AR5K_USEC_1_S 0
  1108. #define AR5K_USEC_32 0x00003f80 /* clock cycles for 1us while on 32MHz clock */
  1109. #define AR5K_USEC_32_S 7
  1110. #define AR5K_USEC_TX_