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/drivers/net/wireless/tiwlan1251/common/src/BusAccess/Shm_Common/shmFwCtrl.c

https://bitbucket.org/cyanogenmod/cm-kernel
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Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0

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  1. /****************************************************************************
  2. **+-----------------------------------------------------------------------+**
  3. **| |**
  4. **| Copyright(c) 1998 - 2008 Texas Instruments. All rights reserved. |**
  5. **| All rights reserved. |**
  6. **| |**
  7. **| Redistribution and use in source and binary forms, with or without |**
  8. **| modification, are permitted provided that the following conditions |**
  9. **| are met: |**
  10. **| |**
  11. **| * Redistributions of source code must retain the above copyright |**
  12. **| notice, this list of conditions and the following disclaimer. |**
  13. **| * Redistributions in binary form must reproduce the above copyright |**
  14. **| notice, this list of conditions and the following disclaimer in |**
  15. **| the documentation and/or other materials provided with the |**
  16. **| distribution. |**
  17. **| * Neither the name Texas Instruments nor the names of its |**
  18. **| contributors may be used to endorse or promote products derived |**
  19. **| from this software without specific prior written permission. |**
  20. **| |**
  21. **| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |**
  22. **| "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |**
  23. **| LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |**
  24. **| A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |**
  25. **| OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |**
  26. **| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |**
  27. **| LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |**
  28. **| DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |**
  29. **| THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |**
  30. **| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |**
  31. **| OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |**
  32. **| |**
  33. **+-----------------------------------------------------------------------+**
  34. ****************************************************************************/
  35. /****************************************************************************
  36. *
  37. * MODULE: ShmFwCtrl.c
  38. * PURPOSE: shared memory firmware control
  39. *
  40. ****************************************************************************/
  41. #include "whalCommon.h"
  42. #include "whalBus_Api.h"
  43. #include "shmBus.h"
  44. #include "TNETWIF.h"
  45. #include "whalHwAccess.h"
  46. #include "whalHwCtrl.h"
  47. #include "shmFwCtrl.h"
  48. #include "TNETW_Driver.h"
  49. #include "CmdMBox_api.h"
  50. #include "eventMbox_api.h"
  51. #include "FwEvent_api.h"
  52. /* Firmware image header size */
  53. #define FW_HDR_SIZE 8
  54. static TI_STATUS whal_FwCtrl_BootSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status);
  55. static TI_STATUS whal_FwCtrl_ResetSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status);
  56. static TI_STATUS whal_FwCtrl_EepromlessStartBurstSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status);
  57. static TI_STATUS whal_FwCtrl_InitSequenceSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status);
  58. static TI_STATUS whal_FwCtrl_LoadFwImageSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status);
  59. static TI_STATUS whal_FwCtrl_FinalizeDownloadSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status);
  60. #ifdef USE_SYNC_API
  61. static int whal_FwCtrl_Reset (TI_HANDLE hWhalBus);
  62. #endif
  63. /* Handle return status inside a state machine */
  64. #define EXCEPT(pwhalbus,status) \
  65. switch (status) { \
  66. case OK: \
  67. case TNETWIF_COMPLETE: \
  68. break; \
  69. case TNETWIF_PENDING: \
  70. return TNETWIF_PENDING; \
  71. default: \
  72. whal_hwCtrl_FinalizeOnFailure (pwhalbus->hHwCtrl); \
  73. return TNETWIF_ERROR; \
  74. }
  75. /* Handle return status inside an init sequence state machine */
  76. #define EXCEPT_I(pwhalbus,status) \
  77. switch (status) { \
  78. case OK: \
  79. case TNETWIF_COMPLETE: \
  80. break; \
  81. case TNETWIF_PENDING: \
  82. pwhalbus->uInitSeqStatus = status; \
  83. return TNETWIF_PENDING; \
  84. default: \
  85. whal_hwCtrl_FinalizeOnFailure (pwhalbus->hHwCtrl); \
  86. return TNETWIF_ERROR; \
  87. }
  88. /* Handle return status inside a load image state machine */
  89. #define EXCEPT_L(pwhalbus,status) \
  90. switch (status) { \
  91. case OK: \
  92. case TNETWIF_COMPLETE: \
  93. break; \
  94. case TNETWIF_PENDING: \
  95. pwhalbus->DownloadStatus = status; \
  96. return TNETWIF_PENDING; \
  97. default: \
  98. pwhalbus->DownloadStatus = status; \
  99. whal_hwCtrl_FinalizeOnFailure (pwhalbus->hHwCtrl); \
  100. return TNETWIF_ERROR; \
  101. }
  102. /****************************************************************************
  103. * whalBus_FwCtrl_Boot()
  104. ****************************************************************************
  105. * DESCRIPTION: Download firmware code to the Hardware and run it
  106. *
  107. * INPUTS: None
  108. *
  109. * OUTPUT: None
  110. *
  111. * RETURNS: OK or NOK
  112. ****************************************************************************/
  113. TI_STATUS whalBus_FwCtrl_Boot (TI_HANDLE hWhalBus, TI_HANDLE hHwCtrl, BootAttr_T *pBootAttr)
  114. {
  115. whalBus_T *pWhalBus = (whalBus_T *)hWhalBus;
  116. HwCtrl_T *pHwCtrl = (HwCtrl_T *)hHwCtrl;
  117. pWhalBus->hHwCtrl = hHwCtrl;
  118. /* Store the pointer to the FW buffer for further use in FW download in part */
  119. pWhalBus->pFwBuf = (UINT8 *)pHwCtrl->uFwBuf;
  120. pWhalBus->uFwLastAddr = pHwCtrl->uFwAddr;
  121. pWhalBus->pEEPROMBuf = (UINT8 *)pHwCtrl->uEEEPROMBuf;
  122. pWhalBus->uEEPROMLen = pHwCtrl->uEEEPROMLen;
  123. /*
  124. * Initialize the status of download to pending
  125. * It will be set to TNETWIF_COMPLETE at the FinalizeDownload function
  126. */
  127. pWhalBus->DownloadStatus = TNETWIF_PENDING;
  128. /* Call the boot sequence state machine */
  129. pWhalBus->uInitStage = 0;
  130. os_memoryCopy (pWhalBus->hOs, &pWhalBus->BootAttr, pBootAttr, sizeof(BootAttr_T));
  131. whal_FwCtrl_BootSm (hWhalBus, HAL_INIT_MODULE_ID, OK);
  132. /*
  133. * If it returns the status of the StartInstance only then we can here query for the download status
  134. * and then return the status up to the TNETW_Driver.
  135. * This return value will go back up to the TNETW Driver layer so that the init from OS will know
  136. * if to wait for the InitComplte or not in case of TNETWIF_ERROR.
  137. * This value will always be pending since the SPI is ASYNC
  138. * and in SDIOa timer is set so it will be ASync also in anyway.
  139. */
  140. return pWhalBus->DownloadStatus;
  141. }
  142. /****************************************************************************
  143. * DESCRIPTION: Firmware boot state machine
  144. *
  145. * INPUTS:
  146. * TI_HANDLE hWhalBus Handle to the Bus
  147. * UINT8 module_id The module id of the Init process in the TNETWIF
  148. *
  149. * OUTPUT: None
  150. *
  151. * RETURNS: OK
  152. ****************************************************************************/
  153. static TI_STATUS whal_FwCtrl_BootSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status)
  154. {
  155. whalBus_T *pWhalBus = (whalBus_T *)hWhalBus;
  156. BootAttr_T *pBootAttr;
  157. UINT8 minorMinorE2Ver = 0;
  158. EXCEPT (pWhalBus, status)
  159. switch (pWhalBus->uInitStage)
  160. {
  161. case 0:
  162. pWhalBus->uInitStage ++;
  163. pWhalBus->uChipId = 0;
  164. /* Read the CHIP ID to get an indication that the bus is OK */
  165. status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF,
  166. CHIP_ID,
  167. &pWhalBus->uChipId,
  168. module_id,
  169. (TNETWIF_callback_t)whal_FwCtrl_BootSm,
  170. hWhalBus);
  171. EXCEPT (pWhalBus, status)
  172. case 1:
  173. pWhalBus->uInitStage ++;
  174. /* This is only sanity check that the HW exists, we can continue and fail on FwLoad */
  175. if (pWhalBus->uChipId == CHIP_ID_1251_PG10)
  176. {
  177. WLAN_OS_REPORT(("Working on a 1251 PG 1.0 board.\n"));
  178. }
  179. else if (pWhalBus->uChipId == CHIP_ID_1251_PG11)
  180. {
  181. WLAN_OS_REPORT(("Working on a 1251 PG 1.1 board.\n"));
  182. }
  183. else if (pWhalBus->uChipId == CHIP_ID_1251_PG12)
  184. {
  185. WLAN_OS_REPORT(("Working on a 1251 PG 1.2 board.\n"));
  186. }
  187. else
  188. {
  189. WLAN_REPORT_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  190. ("whalBus_FwCtrl_Boot: ERROR, Fail to identify Wlan Hardware card, ChipId(0x%x)=0x%x\n",
  191. CHIP_ID, pWhalBus->uChipId));
  192. WLAN_OS_REPORT (("Found unknown Chip Id = 0x%x\n", pWhalBus->uChipId));
  193. /*
  194. * NOTE: no exception because of forward compatibility
  195. */
  196. }
  197. /*
  198. * Soft reset
  199. */
  200. pWhalBus->uResetStage = 0;
  201. pWhalBus->uSelfClearTime = 0;
  202. pWhalBus->uBootData = 0;
  203. status = whal_FwCtrl_ResetSm (pWhalBus, module_id, OK);
  204. EXCEPT (pWhalBus, status)
  205. case 2:
  206. pWhalBus->uInitStage ++;
  207. WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, ("TNET SOFT-RESET\n"));
  208. WLAN_OS_REPORT(("Starting to process NVS...\n"));
  209. /*
  210. * Start EEPROM/NVS burst (get RadioType)
  211. */
  212. if (pWhalBus->pEEPROMBuf)
  213. {
  214. /* NVS file exists (EEPROM-less support) */
  215. pWhalBus->uEEPROMCurLen = pWhalBus->uEEPROMLen;
  216. pWhalBus->pEEPROMCurPtr = pWhalBus->pEEPROMBuf;
  217. pWhalBus->uEEPROMStage = 0;
  218. WLAN_REPORT_INIT (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  219. ("whal_FwCtrl_EepromlessStartBurst: EEPROM Image addr=0x%x, EEPROM Len=0x0x%x\n",
  220. pWhalBus->pEEPROMBuf, pWhalBus->uEEPROMLen));
  221. status = whal_FwCtrl_EepromlessStartBurstSm (hWhalBus, module_id, OK);
  222. EXCEPT (pWhalBus, status)
  223. }
  224. case 3:
  225. pWhalBus->uInitStage ++;
  226. if (pWhalBus->pEEPROMBuf)
  227. {
  228. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  229. ACX_EEPROMLESS_IND_REG,
  230. pWhalBus->uFwLastAddr,
  231. module_id,
  232. (TNETWIF_callback_t)whal_FwCtrl_BootSm,
  233. hWhalBus);
  234. EXCEPT (pWhalBus, status)
  235. }
  236. case 4:
  237. pWhalBus->uInitStage ++;
  238. if (pWhalBus->pEEPROMBuf)
  239. {
  240. WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG,
  241. ("DRIVER NVS BURST-READ\n"));
  242. }
  243. if (!pWhalBus->pEEPROMBuf)
  244. {
  245. /*
  246. * Start ACX EEPROM
  247. */
  248. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  249. ACX_REG_EE_START,
  250. START_EEPROM_MGR,
  251. module_id,
  252. (TNETWIF_callback_t)whal_FwCtrl_BootSm,
  253. hWhalBus);
  254. EXCEPT (pWhalBus, status)
  255. }
  256. case 5:
  257. pWhalBus->uInitStage ++;
  258. if (!pWhalBus->pEEPROMBuf)
  259. {
  260. /*
  261. * The stall is needed so the EEPROM NVS burst read will complete
  262. */
  263. os_StalluSec (pWhalBus->hOs, 40000);
  264. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  265. ACX_EEPROMLESS_IND_REG,
  266. USE_EEPROM,
  267. module_id,
  268. (TNETWIF_callback_t)whal_FwCtrl_BootSm,
  269. hWhalBus);
  270. EXCEPT (pWhalBus, status)
  271. }
  272. case 6:
  273. pWhalBus->uInitStage ++;
  274. if (!pWhalBus->pEEPROMBuf)
  275. {
  276. WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG,
  277. ("STARTING EEPROM NVS BURST-READ\n"));
  278. }
  279. /* Read the EEPROM parameters */
  280. status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF,
  281. SCR_PAD2,
  282. &pWhalBus->uBootData,
  283. module_id,
  284. (TNETWIF_callback_t)whal_FwCtrl_BootSm,
  285. hWhalBus);
  286. EXCEPT (pWhalBus, status)
  287. case 7:
  288. pWhalBus->uInitStage ++;
  289. pBootAttr = &pWhalBus->BootAttr;
  290. pBootAttr->radioType = (pWhalBus->uBootData & 0x0000FF00) >> 8;
  291. pBootAttr->majorE2Ver = (pWhalBus->uBootData & 0x00FF0000) >> 16;
  292. status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF,
  293. SCR_PAD3,
  294. &pWhalBus->uBootData,
  295. module_id,
  296. (TNETWIF_callback_t)whal_FwCtrl_BootSm,
  297. hWhalBus);
  298. EXCEPT (pWhalBus, status)
  299. case 8:
  300. pWhalBus->uInitStage ++;
  301. pBootAttr = &pWhalBus->BootAttr;
  302. pBootAttr->minorE2Ver = (pWhalBus->uBootData & 0x00FF0000) >> 16;
  303. minorMinorE2Ver = (pWhalBus->uBootData & 0xFF000000) >> 24;
  304. if (pBootAttr->radioType == 0xffffffff)
  305. {
  306. WLAN_REPORT_FATAL_ERROR (pWhalBus->hReport, HAL_CTRL_MODULE_LOG,
  307. ("whalBus_FwCtrl_Boot: error in RadioType\n"));
  308. EXCEPT (pWhalBus, TNETWIF_ERROR)
  309. }
  310. WLAN_OS_REPORT(("NVS version %d.%d.%d found.\n", pBootAttr->majorE2Ver, pBootAttr->minorE2Ver, minorMinorE2Ver));
  311. WLAN_OS_REPORT(("Radio type is 0x%X.\n", pBootAttr->radioType));
  312. /* Call the restart sequence */
  313. pWhalBus->uInitSeqStage = 0;
  314. pWhalBus->uInitSeqStatus = TNETWIF_COMPLETE;
  315. status = whal_FwCtrl_InitSequenceSm (hWhalBus, module_id, OK);
  316. EXCEPT (pWhalBus, status)
  317. case 9:
  318. pWhalBus->uInitStage ++;
  319. WLAN_OS_REPORT(("Finished processing NVS.\n"));
  320. /* Download the firmware */
  321. status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF,
  322. ACX_REG_ECPU_CONTROL,
  323. &pWhalBus->uBootData,
  324. module_id,
  325. (TNETWIF_callback_t)whal_FwCtrl_BootSm,
  326. hWhalBus);
  327. EXCEPT (pWhalBus, status)
  328. case 10:
  329. pWhalBus->uInitStage = 0;
  330. if (pWhalBus->pFwBuf && (pWhalBus->uBootData & ECPU_CONTROL_HALT) != 0)
  331. {
  332. WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG,
  333. ("CPU halt -> download code"));
  334. /* Load firmware image */
  335. pWhalBus->uLoadStage = 0;
  336. status = whal_FwCtrl_LoadFwImageSm (pWhalBus, module_id, OK);
  337. switch (status)
  338. {
  339. case TNETWIF_COMPLETE:
  340. /*WLAN_OS_REPORT (("Firmware successfully downloaded.\n"));*/
  341. break;
  342. case TNETWIF_PENDING:
  343. WLAN_OS_REPORT (("Starting to download firmware...\n"));
  344. break;
  345. default:
  346. WLAN_REPORT_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, ("Firmware download failed!\n"));
  347. break;
  348. }
  349. EXCEPT (pWhalBus, status);
  350. }
  351. else
  352. {
  353. WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, ("Firmware not downloaded...\n"));
  354. EXCEPT (pWhalBus, TNETWIF_ERROR)
  355. }
  356. } /* Switch end */
  357. return TNETWIF_COMPLETE;
  358. }
  359. /****************************************************************************
  360. * whal_FwCtrl_FinalizeDownloadSm()
  361. ****************************************************************************
  362. * DESCRIPTION: Run the Hardware firmware
  363. * Wait for Init Complete
  364. * Configure the Bus Access with Addresses available on the scratch pad register
  365. * Change the SDIO/SPI partitions to be able to see all the memory addresses
  366. *
  367. * INPUTS: None
  368. *
  369. * OUTPUT: None
  370. *
  371. * RETURNS: None
  372. ****************************************************************************/
  373. static TI_STATUS whal_FwCtrl_FinalizeDownloadSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status)
  374. {
  375. whalBus_T *pWhalBus = (whalBus_T *)hWhalBus;
  376. #define FIN_LOOP 20000
  377. EXCEPT (pWhalBus, status)
  378. while (TRUE)
  379. {
  380. switch (pWhalBus->uFinStage)
  381. {
  382. case 0:
  383. pWhalBus->uFinStage ++;
  384. /*
  385. * Run the firmware (I)
  386. */
  387. status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF,
  388. ACX_REG_ECPU_CONTROL,
  389. &pWhalBus->uFinData,
  390. module_id,
  391. (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm,
  392. hWhalBus);
  393. EXCEPT (pWhalBus, status);
  394. case 1:
  395. pWhalBus->uFinStage ++;
  396. /*
  397. * Run the firmware (II)
  398. */
  399. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  400. ACX_REG_ECPU_CONTROL,
  401. pWhalBus->uFinData & ~ECPU_CONTROL_HALT,
  402. module_id,
  403. (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm,
  404. hWhalBus);
  405. EXCEPT (pWhalBus, status);
  406. case 2:
  407. pWhalBus->uFinStage ++;
  408. #if defined(TNETW1150) && defined(RIVENDELL)
  409. /* (!!!1150) added when testing with the prateekai/rivendell */
  410. WLAN_REPORT_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  411. ("whal_hwCtrl_Run: Only 1150 - wait 500 msec between FW download and run CPU\n"));
  412. os_StalluSec (pWhalBus->hOs, 500000);
  413. #endif
  414. WLAN_OS_REPORT (("Firmware running.\n"));
  415. /*
  416. * CHIP ID Debug
  417. */
  418. status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF,
  419. CHIP_ID,
  420. &pWhalBus->uFinData,
  421. module_id,
  422. (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm,
  423. hWhalBus);
  424. EXCEPT (pWhalBus, status);
  425. case 3:
  426. pWhalBus->uFinStage ++;
  427. pWhalBus->uFinLoop = 0;
  428. WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG,
  429. ("CHIP ID IS %x\n", pWhalBus->uFinData));
  430. WLAN_REPORT_INIT (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG, ("Wait init complete\n"));
  431. case 4:
  432. /*
  433. * Wait for init complete
  434. */
  435. if (pWhalBus->uFinLoop < FIN_LOOP)
  436. {
  437. pWhalBus->uFinStage = 5;
  438. os_StalluSec (pWhalBus->hOs, 50);
  439. /* Read interrupt status register */
  440. status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF,
  441. ACX_REG_INTERRUPT_NO_CLEAR,
  442. &pWhalBus->uFinData,
  443. module_id,
  444. (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm,
  445. hWhalBus);
  446. EXCEPT (pWhalBus, status);
  447. }
  448. else
  449. pWhalBus->uFinStage = 6;
  450. continue;
  451. case 5:
  452. if (pWhalBus->uFinData == 0xffffffff) /* error */
  453. {
  454. WLAN_REPORT_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  455. ("Error reading hardware complete init indication\n"));
  456. pWhalBus->DownloadStatus = TNETWIF_ERROR;
  457. EXCEPT (pWhalBus, TNETWIF_ERROR);
  458. }
  459. if (IS_MASK_ON (pWhalBus->uFinData, ACX_INTR_INIT_COMPLETE))
  460. {
  461. pWhalBus->uFinStage = 6;
  462. /* Interrupt ACK */
  463. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  464. ACX_REG_INTERRUPT_ACK,
  465. ACX_INTR_INIT_COMPLETE,
  466. module_id,
  467. (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm,
  468. hWhalBus);
  469. EXCEPT (pWhalBus, status);
  470. }
  471. else
  472. {
  473. pWhalBus->uFinStage = 4;
  474. pWhalBus->uFinLoop ++;
  475. }
  476. continue;
  477. case 6:
  478. pWhalBus->uFinStage = 7;
  479. if (pWhalBus->uFinLoop >= FIN_LOOP)
  480. {
  481. WLAN_REPORT_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  482. ("Timeout waiting for the hardware to complete initialization\n"));
  483. pWhalBus->DownloadStatus = TNETWIF_ERROR;
  484. EXCEPT (pWhalBus, TNETWIF_ERROR);
  485. }
  486. WLAN_REPORT_INIT (pWhalBus->hReport, HAL_CTRL_MODULE_LOG, ("Firmware init complete...\n"));
  487. /*
  488. * There are valid addresses of the command and event mailbox
  489. * on the scratch pad registers
  490. */
  491. {
  492. /* Hardware config command mail box */
  493. TnetwDrv_t *pTnetwDrv = (TnetwDrv_t *)pWhalBus->hTnetwDrv;
  494. status = CmdMBox_ConfigHw (pTnetwDrv->hCmdMBox,
  495. module_id,
  496. (fnotify_t)whal_FwCtrl_FinalizeDownloadSm,
  497. hWhalBus);
  498. EXCEPT (pWhalBus, status);
  499. }
  500. continue;
  501. case 7:
  502. pWhalBus->uFinStage = 8;
  503. {
  504. /* Hardware config event mail box */
  505. TnetwDrv_t *pTnetwDrv = (TnetwDrv_t *)pWhalBus->hTnetwDrv;
  506. status = eventMbox_ConfigHw (pTnetwDrv->hEventMbox,
  507. module_id,
  508. (fnotify_t)whal_FwCtrl_FinalizeDownloadSm,
  509. hWhalBus);
  510. EXCEPT (pWhalBus, status);
  511. }
  512. continue;
  513. case 8:
  514. pWhalBus->uFinStage = 9;
  515. /* Set the working partition to its "running" mode offset */
  516. #if defined(HW_ACCESS_SDIO) || defined(HW_ACCESS_WSPI)
  517. status = TNETWIF_SetPartitionsOpt (pWhalBus->hTNETWIF,
  518. HW_ACCESS_WORKING,
  519. HW_ACCESS_WORK_PART0_ADDR,
  520. module_id,
  521. (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm,
  522. hWhalBus);
  523. EXCEPT (pWhalBus, status);
  524. #endif
  525. continue;
  526. case 9:
  527. pWhalBus->uFinStage = 10;
  528. /*
  529. * In case of full asynchronous mode the firmware event must be ready
  530. * to receive event from the command mailbox
  531. */
  532. {
  533. TnetwDrv_t *pTnetwDrv = (TnetwDrv_t *)pWhalBus->hTnetwDrv;
  534. UINT32 uIntVect;
  535. if (pWhalBus->recoveryProcess == FALSE)
  536. FwEvent_Config (pTnetwDrv->hFwEvent, pWhalBus->hTnetwDrv);
  537. #if !defined(USE_SYNC_API)
  538. /* This makes command mailbox to work in normal mode */
  539. whalBus_ExitFromInitMode (hWhalBus);
  540. /* Enable command complete interrupt */
  541. FwEvent_Enable (pTnetwDrv->hFwEvent, ACX_INTR_CMD_COMPLETE);
  542. /* At the driver init the interrupts must be disabled */
  543. os_enableIrq (pWhalBus->hOs);
  544. #endif
  545. #ifdef PRIODIC_INTERRUPT
  546. /* Enable periodic interrupts. It means that every period of time the FwEvent SM will be called */
  547. os_periodicIntrTimerStart (pWhalBus->hOs);
  548. #endif
  549. uIntVect = FwEvent_GetEnabled (pTnetwDrv->hFwEvent);
  550. /* Clearing all the interrupt status register sources */
  551. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  552. ACX_REG_INTERRUPT_MASK,
  553. ~uIntVect,
  554. module_id,
  555. (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm,
  556. hWhalBus);
  557. }
  558. EXCEPT (pWhalBus, status);
  559. continue;
  560. case 10:
  561. pWhalBus->uFinStage = 11;
  562. /*
  563. * Setting the right operation of the interrupt
  564. * bit 5 - enable interrupt
  565. * bit 7 - active low
  566. */
  567. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  568. HI_CFG,
  569. HI_CFG_DEF_VAL,
  570. module_id,
  571. (TNETWIF_callback_t)whal_FwCtrl_FinalizeDownloadSm,
  572. hWhalBus);
  573. EXCEPT (pWhalBus, status);
  574. continue;
  575. case 11:
  576. pWhalBus->uFinStage = 0;
  577. #ifdef DEBUG_INTERRUPTS_PRINT
  578. WLAN_REPORT_INFORMATION (pHwIntr->hReport,
  579. HAL_HW_CTRL_MODULE_LOG,
  580. ("whal_hwIntr_EnableInterrupts(0x%08X)",
  581. pHwIntr->InterruptEnabled));
  582. #endif
  583. #if defined(HAL_ON_WIN)
  584. /* (!!!) Only in CardBus, add HostIfType parameter */
  585. /* Enable interrupt on a CardBus */
  586. TNETWIF_WriteRegSync (pWhalBus->hTNETWIF, FEMR, 0x8000);
  587. #endif
  588. /*
  589. * The last thing to be done after the upper layers have been called
  590. * is to send FINISH to the TNETWIF to end the init process
  591. */
  592. TNETWIF_Finish (pWhalBus->hTNETWIF, HAL_INIT_MODULE_ID, hWhalBus, NULL);
  593. /* Call the whal_hwCtrl_FinalizeDownload of the upper layer to finalize the download process */
  594. whal_hwCtrl_FinalizeDownload (pWhalBus->hHwCtrl, &pWhalBus->BootAttr);
  595. /* Set the Download Status to COMPLETE */
  596. pWhalBus->DownloadStatus = TNETWIF_COMPLETE;
  597. return TNETWIF_COMPLETE;
  598. } /* End switch */
  599. } /* End while */
  600. }
  601. #ifdef USE_SYNC_API
  602. /****************************************************************************
  603. * whal_hwCtrl_Reset()
  604. ****************************************************************************
  605. * DESCRIPTION: Reset the Hardware
  606. *
  607. * INPUTS: None
  608. *
  609. * OUTPUT: None
  610. *
  611. * RETURNS: OK or NOK
  612. ****************************************************************************/
  613. static int whal_FwCtrl_Reset (TI_HANDLE hWhalBus)
  614. {
  615. #ifdef USE_SYNC_API
  616. whalBus_T *pWhalBus = (whalBus_T *)hWhalBus;
  617. UINT32 data;
  618. #ifdef TNETW1251
  619. /***************************************************************/
  620. /* SOFT RESET is done here - its a temporary fix */
  621. /***************************************************************/
  622. UINT32 SelfClearTime;
  623. /*
  624. * Perform Soft Reset
  625. */
  626. TNETWIF_WriteRegSync(pWhalBus->hTNETWIF, ACX_REG_SLV_SOFT_RESET, SLV_SOFT_RESET_BIT);
  627. /* SOFT_RESET - Self clearing */
  628. for (SelfClearTime=0; SelfClearTime<SOFT_RESET_MAX_TIME; SelfClearTime+=SOFT_RESET_STALL_TIME)
  629. {
  630. TNETWIF_ReadRegSync(pWhalBus->hTNETWIF, ACX_REG_SLV_SOFT_RESET,&data);
  631. if (( data & SLV_SOFT_RESET_BIT) == 0)
  632. break;
  633. os_StalluSec(pWhalBus->hOs, SOFT_RESET_STALL_TIME);
  634. }
  635. WLAN_REPORT_INFORMATION(pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  636. ("whal_hwCtrl_Reset: SOFT_RESET Self clearing time = %d (%d)\n", SelfClearTime, SOFT_RESET_MAX_TIME));
  637. if (SelfClearTime >= SOFT_RESET_MAX_TIME)
  638. {
  639. WLAN_REPORT_FATAL_ERROR(pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  640. ("whal_hwCtrl_Reset: ACX_REG_SLV_SOFT_RESET - Self clearing timer expired !!!\n"));
  641. return NOK;
  642. }
  643. /***************************************************************/
  644. /* SOFT RESET is done here - its a temporary fix */
  645. /***************************************************************/
  646. /* Disable Rx/Tx */
  647. TNETWIF_WriteRegSync(pWhalBus->hTNETWIF, ENABLE, 0x0); /* disable TX,RX */
  648. /* Auto Calibration on start Disable */
  649. TNETWIF_WriteRegSync(pWhalBus->hTNETWIF, SPARE_A2, (UINT32)0xFFFF);
  650. #else /* TNETW1251 */
  651. UINT32 SelfClearTime;
  652. /*
  653. * Halt the Acx Cpu
  654. */
  655. TNETWIF_RegIsBitSet(pWhalBus->hTNETWIF, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT);
  656. /*
  657. * Reset the ACX cpu
  658. */
  659. TNETWIF_RegIsBitSet(pWhalBus->hTNETWIF, ACX_REG_SLV_SOFT_RESET, SLV_SOFT_RESET_BIT);
  660. /*
  661. * Wait for Soft reset (Self clearing only in 1150)
  662. */
  663. #if defined(TNETW1150)
  664. /* SOFT_RESET - Self clearing only on 1150 */
  665. for (SelfClearTime=0; SelfClearTime<SOFT_RESET_MAX_TIME; SelfClearTime+=SOFT_RESET_STALL_TIME)
  666. {
  667. os_StalluSec(pWhalBus->hOs, SOFT_RESET_STALL_TIME);
  668. if (((TNETWIF_ReadRegSync(pWhalBus->hTNETWIF,ACX_REG_SLV_SOFT_RESET,&data)) & SLV_SOFT_RESET_BIT) == 0)
  669. break;
  670. }
  671. WLAN_REPORT_INFORMATION(pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  672. ("whal_hwCtrl_Reset: SOFT_RESET Self clearing time = %d (%d)\n", SelfClearTime, SOFT_RESET_MAX_TIME));
  673. if (SelfClearTime >= SOFT_RESET_MAX_TIME)
  674. {
  675. WLAN_REPORT_FATAL_ERROR(pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  676. ("whal_hwCtrl_Reset: ACX_REG_SLV_SOFT_RESET - Self clearing timer expired !!!\n"));
  677. return NOK;
  678. }
  679. #else
  680. os_StalluSec(pWhalBus->hOs, 10000);
  681. TNETWIF_RegResetBitVal(pWhalBus->hTNETWIF, ACX_REG_SLV_SOFT_RESET, SLV_SOFT_RESET_BIT);
  682. #endif
  683. /*
  684. * Start Acx Eeprom
  685. */
  686. TNETWIF_RegIsBitSet(pWhalBus->hTNETWIF, ACX_REG_EE_START, START_EEPROM_MGR);
  687. /* Do Not Reduce the StallSec time !!!!! */
  688. os_StalluSec(pWhalBus->hOs, 40000);
  689. #endif /* TNETW1251 */
  690. #endif /* USE_SYNC_API*/
  691. return OK;
  692. }
  693. #endif /* USE_SYNC_API */
  694. /****************************************************************************
  695. * whal_hwCtrl_Reset()
  696. ****************************************************************************
  697. * DESCRIPTION: Reset hardware state machine
  698. *
  699. * INPUTS: None
  700. *
  701. * OUTPUT: None
  702. *
  703. * RETURNS: OK or NOK
  704. ****************************************************************************/
  705. static TI_STATUS whal_FwCtrl_ResetSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status)
  706. {
  707. whalBus_T *pWhalBus = (whalBus_T *)hWhalBus;
  708. /***************************************************************/
  709. /* SOFT RESET is done here - its a temporary fix */
  710. /***************************************************************/
  711. EXCEPT (pWhalBus, status);
  712. switch (pWhalBus->uResetStage)
  713. {
  714. case 0:
  715. /*
  716. * Perform soft reset
  717. */
  718. pWhalBus->uResetStage ++;
  719. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  720. ACX_REG_SLV_SOFT_RESET,
  721. SLV_SOFT_RESET_BIT,
  722. module_id,
  723. (TNETWIF_callback_t)whal_FwCtrl_ResetSm,
  724. hWhalBus);
  725. EXCEPT (pWhalBus, status);
  726. case 1:
  727. /* SOFT_RESET - self clearing */
  728. while (pWhalBus->uSelfClearTime < SOFT_RESET_MAX_TIME)
  729. {
  730. if (pWhalBus->uSelfClearTime != 0)
  731. {
  732. if ((pWhalBus->uBootData & SLV_SOFT_RESET_BIT) == 0)
  733. break;
  734. os_StalluSec (pWhalBus->hOs, SOFT_RESET_STALL_TIME);
  735. }
  736. status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF,
  737. ACX_REG_SLV_SOFT_RESET,
  738. &pWhalBus->uBootData,
  739. module_id,
  740. (TNETWIF_callback_t)whal_FwCtrl_ResetSm,
  741. hWhalBus);
  742. pWhalBus->uSelfClearTime += SOFT_RESET_STALL_TIME;
  743. EXCEPT (pWhalBus, status);
  744. }
  745. pWhalBus->uResetStage ++;
  746. case 2:
  747. pWhalBus->uResetStage ++;
  748. WLAN_REPORT_INFORMATION (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  749. ("whal_hwCtrl_Reset: SOFT_RESET self clearing time = %d (%d)\n",
  750. pWhalBus->uSelfClearTime, SOFT_RESET_MAX_TIME));
  751. if (pWhalBus->uSelfClearTime >= SOFT_RESET_MAX_TIME)
  752. {
  753. WLAN_REPORT_FATAL_ERROR (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  754. ("whal_hwCtrl_Reset: ACX_REG_SLV_SOFT_RESET - Self clearing timer expired !!!\n"));
  755. EXCEPT (pWhalBus, TNETWIF_ERROR);
  756. }
  757. case 3:
  758. pWhalBus->uResetStage ++;
  759. /* Disable Rx/Tx */
  760. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  761. ENABLE,
  762. 0x0,
  763. module_id,
  764. (TNETWIF_callback_t)whal_FwCtrl_ResetSm,
  765. hWhalBus);
  766. EXCEPT (pWhalBus, status);
  767. case 4:
  768. pWhalBus->uResetStage ++;
  769. /* Disable auto calibration on start */
  770. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  771. SPARE_A2,
  772. 0xFFFF,
  773. module_id,
  774. (TNETWIF_callback_t)whal_FwCtrl_ResetSm,
  775. hWhalBus);
  776. return status;
  777. case 5:
  778. pWhalBus->uResetStage = 0;
  779. /* If the previous status was pending call the upper layer init state machine */
  780. whal_FwCtrl_BootSm (hWhalBus, module_id, status);
  781. }
  782. return status;
  783. }
  784. /****************************************************************************
  785. * whal_FwCtrl_Eepromless_StartBurst()
  786. ****************************************************************************
  787. * DESCRIPTION: prepare eepromless configuration before boot
  788. *
  789. * INPUTS:
  790. *
  791. * OUTPUT:
  792. *
  793. * RETURNS:
  794. ****************************************************************************/
  795. static TI_STATUS whal_FwCtrl_EepromlessStartBurstSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status)
  796. {
  797. whalBus_T* pWhalBus = (whalBus_T *)hWhalBus;
  798. EXCEPT (pWhalBus, status);
  799. while (TRUE)
  800. {
  801. switch (pWhalBus->uEEPROMStage)
  802. {
  803. case 0:
  804. if ((pWhalBus->uEEPROMRegAddr = pWhalBus->pEEPROMCurPtr[1]) & 1)
  805. {
  806. pWhalBus->uEEPROMRegAddr &= 0xfe;
  807. pWhalBus->uEEPROMRegAddr |= (UINT32)pWhalBus->pEEPROMCurPtr[2] << 8;
  808. pWhalBus->uEEPROMBurstLen = pWhalBus->pEEPROMCurPtr[0];
  809. pWhalBus->pEEPROMCurPtr += 3;
  810. pWhalBus->uEEPROMBurstLoop = 0;
  811. pWhalBus->uEEPROMStage = 1;
  812. }
  813. else
  814. {
  815. if (pWhalBus->pEEPROMCurPtr[0] == 0)
  816. pWhalBus->pEEPROMCurPtr += 7;
  817. pWhalBus->uEEPROMCurLen -= pWhalBus->pEEPROMCurPtr - pWhalBus->pEEPROMBuf;
  818. pWhalBus->uEEPROMCurLen = (pWhalBus->uEEPROMCurLen + NVS_DATA_BUNDARY_ALIGNMENT - 1) & 0xfffffffc;
  819. pWhalBus->uEEPROMStage = 2;
  820. }
  821. continue;
  822. case 1:
  823. if (pWhalBus->uEEPROMBurstLoop < pWhalBus->uEEPROMBurstLen)
  824. {
  825. UINT32 val = (pWhalBus->pEEPROMCurPtr[0] |
  826. (pWhalBus->pEEPROMCurPtr[1] << 8) |
  827. (pWhalBus->pEEPROMCurPtr[2] << 16) |
  828. (pWhalBus->pEEPROMCurPtr[3] << 24));
  829. WLAN_REPORT_INIT (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  830. ("NVS::BurstRead: *(%08x) = %x\n", pWhalBus->uEEPROMRegAddr, val));
  831. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  832. pWhalBus->uEEPROMRegAddr,
  833. val,
  834. module_id,
  835. (TNETWIF_callback_t)whal_FwCtrl_EepromlessStartBurstSm,
  836. hWhalBus);
  837. pWhalBus->uEEPROMStatus = status;
  838. pWhalBus->uEEPROMRegAddr += 4;
  839. pWhalBus->pEEPROMCurPtr += 4;
  840. pWhalBus->uEEPROMStage = 1;
  841. pWhalBus->uEEPROMBurstLoop ++;
  842. EXCEPT (pWhalBus, status);
  843. }
  844. else
  845. pWhalBus->uEEPROMStage = 0;
  846. continue;
  847. case 2:
  848. WLAN_REPORT_INIT (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  849. ("Get NVS file information: NvsDataLen = %#x TableAddr %#x\n", pWhalBus->uEEPROMCurLen, pWhalBus->uFwLastAddr));
  850. pWhalBus->uNVSStartAddr = pWhalBus->uFwLastAddr;
  851. pWhalBus->uNVSNumChar = 0;
  852. pWhalBus->uNVSNumByte = 0;
  853. pWhalBus->uNVSTempWord = 0;
  854. pWhalBus->uEEPROMStage = 3;
  855. #if defined(HW_ACCESS_SDIO) || defined(HW_ACCESS_WSPI)
  856. status = TNETWIF_SetPartitionsOpt (pWhalBus->hTNETWIF,
  857. HW_ACCESS_DOWNLOAD,
  858. pWhalBus->uNVSStartAddr,
  859. module_id,
  860. (TNETWIF_callback_t)whal_FwCtrl_EepromlessStartBurstSm,
  861. hWhalBus);
  862. EXCEPT (pWhalBus, status);
  863. #endif
  864. continue;
  865. case 3:
  866. /*
  867. * Download EEPROM data to ACX internal memory
  868. */
  869. if (pWhalBus->uNVSNumChar < pWhalBus->uEEPROMCurLen)
  870. {
  871. pWhalBus->uNVSTempWord |= (*pWhalBus->pEEPROMCurPtr) << (8 * pWhalBus->uNVSNumByte);
  872. pWhalBus->pEEPROMCurPtr ++;
  873. pWhalBus->uNVSNumChar ++;
  874. if (++pWhalBus->uNVSNumByte > 3)
  875. {
  876. pWhalBus->uEEPROMStage = 4;
  877. pWhalBus->uNVSTempWord = ENDIAN_HANDLE_LONG (pWhalBus->uNVSTempWord);
  878. WLAN_REPORT_INIT (pWhalBus->hReport, HAL_HW_CTRL_MODULE_LOG,
  879. ("NVS::WriteTable: *(%08x) = %x\n", pWhalBus->uNVSStartAddr, pWhalBus->uNVSTempWord));
  880. status = TNETWIF_WriteMemOpt (pWhalBus->hTNETWIF,
  881. pWhalBus->uNVSStartAddr,
  882. PADWRITE (&pWhalBus->uNVSTempWord),
  883. sizeof(pWhalBus->uNVSTempWord),
  884. module_id,
  885. (TNETWIF_callback_t)whal_FwCtrl_EepromlessStartBurstSm,
  886. hWhalBus);
  887. pWhalBus->uNVSStatus = status;
  888. EXCEPT (pWhalBus, status);
  889. }
  890. }
  891. else
  892. {
  893. /* Call the upper level state machine */
  894. if (pWhalBus->uEEPROMStatus == TNETWIF_PENDING ||
  895. pWhalBus->uNVSStatus == TNETWIF_PENDING)
  896. whal_FwCtrl_BootSm (hWhalBus, module_id, status);
  897. return TNETWIF_COMPLETE;
  898. }
  899. continue;
  900. case 4:
  901. pWhalBus->uNVSStartAddr += 4;
  902. pWhalBus->uNVSTempWord = 0;
  903. pWhalBus->uNVSNumByte = 0;
  904. pWhalBus->uEEPROMStage = 3;
  905. continue;
  906. } /* End switch */
  907. } /* End while */
  908. }
  909. /****************************************************************************
  910. * whal_FwCtrl_InitSequenceSm()
  911. ****************************************************************************
  912. * DESCRIPTION: the restart wakeup sequence state machine
  913. *
  914. * INPUTS: None
  915. *
  916. * OUTPUT: None
  917. *
  918. * RETURNS: OK or NOK
  919. ****************************************************************************/
  920. static TI_STATUS whal_FwCtrl_InitSequenceSm (TI_HANDLE hWhalBus, UINT8 module_id, TI_STATUS status)
  921. {
  922. whalBus_T *pWhalBus = (whalBus_T *)hWhalBus;
  923. static const UINT32 LUT [REF_FREQ_NUM][LUT_PARAM_NUM] =
  924. { /* INTEGER_DIVIDER FRACTIONAL_DIVIDER ATTN_BB ALPHA_BB STOP_TIME_BB BB_PLL_LOOP_FILTER */
  925. { 83, 87381, 0xB, 5, 0xF00, 3}, /* REF_FREQ_19_2*/
  926. { 61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/
  927. { 41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/
  928. { 40, 0, 0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/
  929. { 47, 162280, 0xC, 6, 0x2760, 1} /* REF_FREQ_33_6 */
  930. };
  931. EXCEPT_I (pWhalBus, status);
  932. switch (pWhalBus->uInitSeqStage)
  933. {
  934. case 0:
  935. pWhalBus->uInitSeqStage ++;
  936. WLAN_REPORT_INIT(pWhalBus->hReport, HAL_CTRL_MODULE_LOG, ("Starting INIT sequence\n"));
  937. /* Read NVS params */
  938. status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF,
  939. SCR_PAD6,
  940. &pWhalBus->uScrPad6,
  941. module_id,
  942. (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm,
  943. hWhalBus);
  944. EXCEPT_I (pWhalBus, status);
  945. case 1:
  946. pWhalBus->uInitSeqStage ++;
  947. /* Read ELP_CMD */
  948. status = TNETWIF_ReadRegOpt (pWhalBus->hTNETWIF,
  949. ELP_CMD,
  950. &pWhalBus->uElpCmd,
  951. module_id,
  952. (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm,
  953. hWhalBus);
  954. EXCEPT_I (pWhalBus, status);
  955. case 2:
  956. pWhalBus->uInitSeqStage ++;
  957. pWhalBus->uRefFreq = pWhalBus->uScrPad6 & 0x000000FF;
  958. /******************** Set ELP configuration *********************/
  959. /*
  960. * Set the BB Calibration time to be 300 usec (PLL_CAL_TIME)
  961. */
  962. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  963. PLL_CAL_TIME/*0x5810*/,
  964. 0x9/*0x4*/,
  965. module_id,
  966. (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm,
  967. hWhalBus);
  968. EXCEPT_I (pWhalBus, status);
  969. case 3:
  970. pWhalBus->uInitSeqStage ++;
  971. /* PG 1.1 & 1.0: Set the clock buffer time to be 760 usec (CLK_BUF_TIME) */
  972. if (pWhalBus->uChipId == CHIP_ID_1251_PG10 ||
  973. pWhalBus->uChipId == CHIP_ID_1251_PG11)
  974. {
  975. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  976. CLK_BUF_TIME/*0x5818*/,
  977. 0x19,
  978. module_id,
  979. (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm,
  980. hWhalBus);
  981. }
  982. /* PG 1.2: Set the clock buffer time to be 210 usec (CLK_BUF_TIME) */
  983. else
  984. {
  985. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  986. CLK_BUF_TIME/*0x5818*/,
  987. 0x6,
  988. module_id,
  989. (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm,
  990. hWhalBus);
  991. }
  992. EXCEPT_I (pWhalBus, status);
  993. case 4:
  994. pWhalBus->uInitSeqStage ++;
  995. /*
  996. * Set the clock detect feature to work in the restart wu procedure (ELP_CFG_MODE[14])
  997. * &
  998. * Select the clock source type (ELP_CFG_MODE[13:12] )
  999. */
  1000. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  1001. ELP_CFG_MODE/*0x5804*/,
  1002. ((pWhalBus->uScrPad6 & 0x0000FF00) << 4) | 0x00004000,
  1003. module_id,
  1004. (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm,
  1005. hWhalBus);
  1006. EXCEPT_I (pWhalBus, status);
  1007. case 5:
  1008. pWhalBus->uInitSeqStage ++;
  1009. /* PG 1.1 & 1.0 */
  1010. if (pWhalBus->uChipId == CHIP_ID_1251_PG10 ||
  1011. pWhalBus->uChipId == CHIP_ID_1251_PG11)
  1012. {
  1013. /* Do nothing */
  1014. }
  1015. /* PG 1.2: Enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */
  1016. else
  1017. {
  1018. pWhalBus->uElpCmd |= 0x00000040;
  1019. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  1020. ELP_CMD/*0x5808*/,
  1021. pWhalBus->uElpCmd,
  1022. module_id,
  1023. (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm,
  1024. hWhalBus);
  1025. EXCEPT_I (pWhalBus, status);
  1026. }
  1027. case 6:
  1028. pWhalBus->uInitSeqStage ++;
  1029. /* PG 1.1 & 1.0: set the BB PLL stable time to be 30usec (PLL_STABLE_TIME) */
  1030. if (pWhalBus->uChipId == CHIP_ID_1251_PG10 ||
  1031. pWhalBus->uChipId == CHIP_ID_1251_PG11)
  1032. {
  1033. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  1034. CFG_PLL_SYNC_CNT/*0x5820*/,
  1035. 0x00,
  1036. module_id,
  1037. (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm,
  1038. hWhalBus);
  1039. }
  1040. /* PG 1.2: Set the BB PLL stable time to be 1000usec (PLL_STABLE_TIME) */
  1041. else
  1042. {
  1043. status = TNETWIF_WriteRegOpt (pWhalBus->hTNETWIF,
  1044. CFG_PLL_SYNC_CNT/*0x5820*/,
  1045. 0x20,
  1046. module_id,
  1047. (TNETWIF_callback_t)whal_FwCtrl_InitSequenceSm,

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