PageRenderTime 54ms CodeModel.GetById 23ms RepoModel.GetById 1ms app.codeStats 0ms

/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c

https://bitbucket.org/freebsd/freebsd-head/
C | 1290 lines | 1071 code | 69 blank | 150 comment | 0 complexity | 8f1c13e12513fe394b77046f44de47f2 MD5 | raw file
Possible License(s): MPL-2.0-no-copyleft-exception, BSD-3-Clause, LGPL-2.0, LGPL-2.1, BSD-2-Clause, 0BSD, JSON, AGPL-1.0, GPL-2.0

Large files files are truncated, but you can click here to view the full file

    

  1. /***********************license start***************
    2. 

  2.  * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
    3. 

  3.  * reserved.
    4. 

  4.  *
    5. 

  5.  *
    6. 

  6.  * Redistribution and use in source and binary forms, with or without
    7. 

  7.  * modification, are permitted provided that the following conditions are
    8. 

  8.  * met:
    9. 

  9.  *
    10. 

  10.  *   * Redistributions of source code must retain the above copyright
    11. 

  11.  *     notice, this list of conditions and the following disclaimer.
    12. 

  12.  *
    13. 

  13.  *   * Redistributions in binary form must reproduce the above
    14. 

  14.  *     copyright notice, this list of conditions and the following
    15. 

  15.  *     disclaimer in the documentation and/or other materials provided
    16. 

  16.  *     with the distribution.
    17. 

    18. 

  18.  *   * Neither the name of Cavium Networks nor the names of
    19. 

  19.  *     its contributors may be used to endorse or promote products
    20. 

  20.  *     derived from this software without specific prior written
    21. 

  21.  *     permission.
    22. 

    23. 

  23.  * This Software, including technical data, may be subject to U.S. export  control
    24. 

  24.  * laws, including the U.S. Export Administration Act and its  associated
    25. 

  25.  * regulations, and may be subject to export or import  regulations in other
    26. 

  26.  * countries.
    27. 

    28. 

  28.  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
    29. 

  29.  * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
    30. 

  30.  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
    31. 

  31.  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
    32. 

  32.  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
    33. 

  33.  * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
    34. 

  34.  * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
    35. 

  35.  * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
    36. 

  36.  * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
    37. 

  37.  * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
    38. 

  38.  ***********************license end**************************************/
    39. 

  39. 

  40. 

  41. /**
    42. 

  42.  * @file
    43. 

  43.  *
    44. 

  44.  * Automatically generated error messages for cn38xx.
    45. 

  45.  *
    46. 

  46.  * This file is auto generated. Do not edit.
    47. 

  47.  *
    48. 

  48.  * <hr>$Revision$<hr>
    49. 

  49.  *
    50. 

  50.  * <hr><h2>Error tree for CN38XX</h2>
    51. 

  51.  * @dot
    52. 

  52.  * digraph cn38xx
    53. 

  53.  * {
    54. 

  54.  *     rankdir=LR;
    55. 

  55.  *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
    56. 

  56.  *     edge [fontsize=7, font=helvitica];
    57. 

  57.  *     cvmx_root [label="ROOT|<root>root"];
    58. 

  58.  *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"];
    59. 

  59.  *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
    60. 

  60.  *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
    61. 

  61.  *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
    62. 

  62.  *     cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"];
    63. 

  63.  *     cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
    64. 

  64.  *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
    65. 

  65.  *     cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
    66. 

  66.  *     cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
    67. 

  67.  *     cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
    68. 

  68.  *     cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
    69. 

  69.  *     cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
    70. 

  70.  *     cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
    71. 

  71.  *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
    72. 

  72.  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
    73. 

  73.  *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
    74. 

  74.  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
    75. 

  75.  *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
    76. 

  76.  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
    77. 

  77.  *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
    78. 

  78.  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
    79. 

  79.  *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
    80. 

  80.  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
    81. 

  81.  *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
    82. 

  82.  *     cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
    83. 

  83.  *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
    84. 

  84.  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
    85. 

  85.  *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
    86. 

  86.  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
    87. 

  87.  *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
    88. 

  88.  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
    89. 

  89.  *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
    90. 

  90.  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
    91. 

  91.  *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
    92. 

  92.  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
    93. 

  93.  *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
    94. 

  94.  *     cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
    95. 

  95.  *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
    96. 

  96.  *     cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
    97. 

  97.  *     cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
    98. 

  98.  *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"];
    99. 

  99.  *     cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
    100. 

  100.  *     cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"];
    101. 

  101.  *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
    102. 

  102.  *     cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
    103. 

  103.  *     cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
    104. 

  104.  *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"];
    105. 

  105.  *     cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
    106. 

  106.  *     cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"];
    107. 

  107.  *     cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
    108. 

  108.  *     cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
    109. 

  109.  *     cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
    110. 

  110.  *     cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"];
    111. 

  111.  *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
    112. 

  112.  *     cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
    113. 

  113.  *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
    114. 

  114.  *     cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
    115. 

  115.  *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
    116. 

  116.  *     cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
    117. 

  117.  *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
    118. 

  118.  *     cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
    119. 

  119.  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
    120. 

  120.  *     cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
    121. 

  121.  *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
    122. 

  122.  *     cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
    123. 

  123.  *     cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
    124. 

  124.  *     cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
    125. 

  125.  *     cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
    126. 

  126.  *     cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
    127. 

  127.  *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
    128. 

  128.  *     cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
    129. 

  129.  *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
    130. 

  130.  *     cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
    131. 

  131.  *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
    132. 

  132.  *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
    133. 

  133.  *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
    134. 

  134.  *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
    135. 

  135.  *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
    136. 

  136.  *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
    137. 

  137.  *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
    138. 

  138.  *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
    139. 

  139.  *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
    140. 

  140.  *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
    141. 

  141.  *     cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis];
    142. 

  142.  *     cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis];
    143. 

  143.  *     cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
    144. 

  144.  * }
    145. 

  145.  * @enddot
    146. 

  146.  */
    147. 

  147. #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
    148. 

  148. #include <asm/octeon/cvmx.h>
    149. 

  149. #include <asm/octeon/cvmx-error.h>
    150. 

  150. #include <asm/octeon/cvmx-error-custom.h>
    151. 

  151. #include <asm/octeon/cvmx-csr-typedefs.h>
    152. 

  152. #else
    153. 

  153. #include "cvmx.h"
    154. 

  154. #include "cvmx-error.h"
    155. 

  155. #include "cvmx-error-custom.h"
    156. 

  156. #endif
    157. 

  157. 

  158. int cvmx_error_initialize_cn38xx(void);
    159. 

  159. 

  160. int cvmx_error_initialize_cn38xx(void)
    161. 

  161. {
    162. 

  162.     cvmx_error_info_t info;
    163. 

  163.     int fail = 0;
    164. 

  164. 

  165.     /* CVMX_CIU_INTX_SUM0(0) */
    166. 

  166.     /* CVMX_CIU_INT_SUM1 */
    167. 

  167.     /* CVMX_NPI_RSL_INT_BLOCKS */
    168. 

  168.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    169. 

  169.     info.status_addr        = CVMX_NPI_RSL_INT_BLOCKS;
    170. 

  170.     info.status_mask        = 0;
    171. 

  171.     info.enable_addr        = 0;
    172. 

  172.     info.enable_mask        = 0;
    173. 

  173.     info.flags              = 0;
    174. 

  174.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    175. 

  175.     info.group_index        = 0;
    176. 

  176.     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
    177. 

  177.     info.parent.status_addr = 0;
    178. 

  178.     info.parent.status_mask = 0;
    179. 

  179.     info.func               = __cvmx_error_decode;
    180. 

  180.     info.user_info          = 0;
    181. 

  181.     fail |= cvmx_error_add(&info);
    182. 

  182. 

  183.     /* CVMX_L2D_ERR */
    184. 

  184.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    185. 

  185.     info.status_addr        = CVMX_L2D_ERR;
    186. 

  186.     info.status_mask        = 1ull<<3 /* sec_err */;
    187. 

  187.     info.enable_addr        = CVMX_L2D_ERR;
    188. 

  188.     info.enable_mask        = 1ull<<1 /* sec_intena */;
    189. 

  189.     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
    190. 

  190.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    191. 

  191.     info.group_index        = 0;
    192. 

  192.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    193. 

  193.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    194. 

  194.     info.parent.status_mask = 1ull<<16 /* l2c */;
    195. 

  195.     info.func               = __cvmx_error_handle_l2d_err_sec_err;
    196. 

  196.     info.user_info          = (long)
    197. 

  197.         "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
    198. 

  198.     fail |= cvmx_error_add(&info);
    199. 

  199. 

  200.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    201. 

  201.     info.status_addr        = CVMX_L2D_ERR;
    202. 

  202.     info.status_mask        = 1ull<<4 /* ded_err */;
    203. 

  203.     info.enable_addr        = CVMX_L2D_ERR;
    204. 

  204.     info.enable_mask        = 1ull<<2 /* ded_intena */;
    205. 

  205.     info.flags              = 0;
    206. 

  206.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    207. 

  207.     info.group_index        = 0;
    208. 

  208.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    209. 

  209.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    210. 

  210.     info.parent.status_mask = 1ull<<16 /* l2c */;
    211. 

  211.     info.func               = __cvmx_error_handle_l2d_err_ded_err;
    212. 

  212.     info.user_info          = (long)
    213. 

  213.         "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
    214. 

  214.     fail |= cvmx_error_add(&info);
    215. 

  215. 

  216.     /* CVMX_L2T_ERR */
    217. 

  217.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    218. 

  218.     info.status_addr        = CVMX_L2T_ERR;
    219. 

  219.     info.status_mask        = 1ull<<3 /* sec_err */;
    220. 

  220.     info.enable_addr        = CVMX_L2T_ERR;
    221. 

  221.     info.enable_mask        = 1ull<<1 /* sec_intena */;
    222. 

  222.     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
    223. 

  223.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    224. 

  224.     info.group_index        = 0;
    225. 

  225.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    226. 

  226.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    227. 

  227.     info.parent.status_mask = 1ull<<16 /* l2c */;
    228. 

  228.     info.func               = __cvmx_error_handle_l2t_err_sec_err;
    229. 

  229.     info.user_info          = (long)
    230. 

  230.         "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
    231. 

  231.         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
    232. 

  232.         "    given index) are checked for single bit errors(SBEs).\n"
    233. 

  233.         "    This bit is set if ANY of the 8 sets contains an SBE.\n"
    234. 

  234.         "    SBEs are auto corrected in HW and generate an\n"
    235. 

  235.         "    interrupt(if enabled).\n";
    236. 

  236.     fail |= cvmx_error_add(&info);
    237. 

  237. 

  238.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    239. 

  239.     info.status_addr        = CVMX_L2T_ERR;
    240. 

  240.     info.status_mask        = 1ull<<4 /* ded_err */;
    241. 

  241.     info.enable_addr        = CVMX_L2T_ERR;
    242. 

  242.     info.enable_mask        = 1ull<<2 /* ded_intena */;
    243. 

  243.     info.flags              = 0;
    244. 

  244.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    245. 

  245.     info.group_index        = 0;
    246. 

  246.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    247. 

  247.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    248. 

  248.     info.parent.status_mask = 1ull<<16 /* l2c */;
    249. 

  249.     info.func               = __cvmx_error_handle_l2t_err_ded_err;
    250. 

  250.     info.user_info          = (long)
    251. 

  251.         "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
    252. 

  252.         "    During every L2 Tag Probe, all 8 sets Tag's (at a\n"
    253. 

  253.         "    given index) are checked for double bit errors(DBEs).\n"
    254. 

  254.         "    This bit is set if ANY of the 8 sets contains a DBE.\n"
    255. 

  255.         "    DBEs also generated an interrupt(if enabled).\n";
    256. 

  256.     fail |= cvmx_error_add(&info);
    257. 

  257. 

  258.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    259. 

  259.     info.status_addr        = CVMX_L2T_ERR;
    260. 

  260.     info.status_mask        = 1ull<<24 /* lckerr */;
    261. 

  261.     info.enable_addr        = CVMX_L2T_ERR;
    262. 

  262.     info.enable_mask        = 1ull<<25 /* lck_intena */;
    263. 

  263.     info.flags              = 0;
    264. 

  264.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    265. 

  265.     info.group_index        = 0;
    266. 

  266.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    267. 

  267.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    268. 

  268.     info.parent.status_mask = 1ull<<16 /* l2c */;
    269. 

  269.     info.func               = __cvmx_error_handle_l2t_err_lckerr;
    270. 

  270.     info.user_info          = (long)
    271. 

  271.         "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
    272. 

  272.         "    the INDEX (which is ignored by HW - but reported to SW).\n"
    273. 

  273.         "    The LDD(L1 load-miss) for the LOCK operation is completed\n"
    274. 

  274.         "    successfully, however the address is NOT locked.\n"
    275. 

  275.         "    NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
    276. 

  276.         "    into account. For example, if diagnostic PPx has\n"
    277. 

  277.         "    UMSKx defined to only use SETs [1:0], and SET1 had\n"
    278. 

  278.         "    been previously LOCKED, then an attempt to LOCK the\n"
    279. 

  279.         "    last available SET0 would result in a LCKERR. (This\n"
    280. 

  280.         "    is to ensure that at least 1 SET at each INDEX is\n"
    281. 

  281.         "    not LOCKED for general use by other PPs).\n";
    282. 

  282.     fail |= cvmx_error_add(&info);
    283. 

  283. 

  284.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    285. 

  285.     info.status_addr        = CVMX_L2T_ERR;
    286. 

  286.     info.status_mask        = 1ull<<26 /* lckerr2 */;
    287. 

  287.     info.enable_addr        = CVMX_L2T_ERR;
    288. 

  288.     info.enable_mask        = 1ull<<27 /* lck_intena2 */;
    289. 

  289.     info.flags              = 0;
    290. 

  290.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    291. 

  291.     info.group_index        = 0;
    292. 

  292.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    293. 

  293.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    294. 

  294.     info.parent.status_mask = 1ull<<16 /* l2c */;
    295. 

  295.     info.func               = __cvmx_error_handle_l2t_err_lckerr2;
    296. 

  296.     info.user_info          = (long)
    297. 

  297.         "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
    298. 

  298.         "    could not find an available/unlocked set (for\n"
    299. 

  299.         "    replacement).\n"
    300. 

  300.         "    Most likely, this is a result of SW mixing SET\n"
    301. 

  301.         "    PARTITIONING with ADDRESS LOCKING. If SW allows\n"
    302. 

  302.         "    another PP to LOCKDOWN all SETs available to PP#n,\n"
    303. 

  303.         "    then a Rd/Wr Miss from PP#n will be unable\n"
    304. 

  304.         "    to determine a 'valid' replacement set (since LOCKED\n"
    305. 

  305.         "    addresses should NEVER be replaced).\n"
    306. 

  306.         "    If such an event occurs, the HW will select the smallest\n"
    307. 

  307.         "    available SET(specified by UMSK'x)' as the replacement\n"
    308. 

  308.         "    set, and the address is unlocked.\n";
    309. 

  309.     fail |= cvmx_error_add(&info);
    310. 

  310. 

  311.     /* CVMX_NPI_INT_SUM */
    312. 

  312.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    313. 

  313.     info.status_addr        = CVMX_NPI_INT_SUM;
    314. 

  314.     info.status_mask        = 1ull<<0 /* rml_rto */;
    315. 

  315.     info.enable_addr        = CVMX_NPI_INT_ENB;
    316. 

  316.     info.enable_mask        = 1ull<<0 /* rml_rto */;
    317. 

  317.     info.flags              = 0;
    318. 

  318.     info.group              = CVMX_ERROR_GROUP_PCI;
    319. 

  319.     info.group_index        = 0;
    320. 

  320.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    321. 

  321.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    322. 

  322.     info.parent.status_mask = 1ull<<3 /* npi */;
    323. 

  323.     info.func               = __cvmx_error_display;
    324. 

  324.     info.user_info          = (long)
    325. 

  325.         "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
    326. 

  326.         "    back from a RSL after sending a read command to\n"
    327. 

  327.         "    a RSL.\n";
    328. 

  328.     fail |= cvmx_error_add(&info);
    329. 

  329. 

  330.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    331. 

  331.     info.status_addr        = CVMX_NPI_INT_SUM;
    332. 

  332.     info.status_mask        = 1ull<<1 /* rml_wto */;
    333. 

  333.     info.enable_addr        = CVMX_NPI_INT_ENB;
    334. 

  334.     info.enable_mask        = 1ull<<1 /* rml_wto */;
    335. 

  335.     info.flags              = 0;
    336. 

  336.     info.group              = CVMX_ERROR_GROUP_PCI;
    337. 

  337.     info.group_index        = 0;
    338. 

  338.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    339. 

  339.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    340. 

  340.     info.parent.status_mask = 1ull<<3 /* npi */;
    341. 

  341.     info.func               = __cvmx_error_display;
    342. 

  342.     info.user_info          = (long)
    343. 

  343.         "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
    344. 

  344.         "    back from a RSL after sending a write command to\n"
    345. 

  345.         "    a RSL.\n";
    346. 

  346.     fail |= cvmx_error_add(&info);
    347. 

  347. 

  348.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    349. 

  349.     info.status_addr        = CVMX_NPI_INT_SUM;
    350. 

  350.     info.status_mask        = 1ull<<3 /* po0_2sml */;
    351. 

  351.     info.enable_addr        = CVMX_NPI_INT_ENB;
    352. 

  352.     info.enable_mask        = 1ull<<3 /* po0_2sml */;
    353. 

  353.     info.flags              = 0;
    354. 

  354.     info.group              = CVMX_ERROR_GROUP_PCI;
    355. 

  355.     info.group_index        = 0;
    356. 

  356.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    357. 

  357.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    358. 

  358.     info.parent.status_mask = 1ull<<3 /* npi */;
    359. 

  359.     info.func               = __cvmx_error_display;
    360. 

  360.     info.user_info          = (long)
    361. 

  361.         "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
    362. 

  362.         "    than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
    363. 

  363.     fail |= cvmx_error_add(&info);
    364. 

  364. 

  365.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    366. 

  366.     info.status_addr        = CVMX_NPI_INT_SUM;
    367. 

  367.     info.status_mask        = 1ull<<4 /* po1_2sml */;
    368. 

  368.     info.enable_addr        = CVMX_NPI_INT_ENB;
    369. 

  369.     info.enable_mask        = 1ull<<4 /* po1_2sml */;
    370. 

  370.     info.flags              = 0;
    371. 

  371.     info.group              = CVMX_ERROR_GROUP_PCI;
    372. 

  372.     info.group_index        = 0;
    373. 

  373.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    374. 

  374.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    375. 

  375.     info.parent.status_mask = 1ull<<3 /* npi */;
    376. 

  376.     info.func               = __cvmx_error_display;
    377. 

  377.     info.user_info          = (long)
    378. 

  378.         "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
    379. 

  379.         "    than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
    380. 

  380.     fail |= cvmx_error_add(&info);
    381. 

  381. 

  382.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    383. 

  383.     info.status_addr        = CVMX_NPI_INT_SUM;
    384. 

  384.     info.status_mask        = 1ull<<5 /* po2_2sml */;
    385. 

  385.     info.enable_addr        = CVMX_NPI_INT_ENB;
    386. 

  386.     info.enable_mask        = 1ull<<5 /* po2_2sml */;
    387. 

  387.     info.flags              = 0;
    388. 

  388.     info.group              = CVMX_ERROR_GROUP_PCI;
    389. 

  389.     info.group_index        = 0;
    390. 

  390.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    391. 

  391.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    392. 

  392.     info.parent.status_mask = 1ull<<3 /* npi */;
    393. 

  393.     info.func               = __cvmx_error_display;
    394. 

  394.     info.user_info          = (long)
    395. 

  395.         "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
    396. 

  396.         "    than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n";
    397. 

  397.     fail |= cvmx_error_add(&info);
    398. 

  398. 

  399.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    400. 

  400.     info.status_addr        = CVMX_NPI_INT_SUM;
    401. 

  401.     info.status_mask        = 1ull<<6 /* po3_2sml */;
    402. 

  402.     info.enable_addr        = CVMX_NPI_INT_ENB;
    403. 

  403.     info.enable_mask        = 1ull<<6 /* po3_2sml */;
    404. 

  404.     info.flags              = 0;
    405. 

  405.     info.group              = CVMX_ERROR_GROUP_PCI;
    406. 

  406.     info.group_index        = 0;
    407. 

  407.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    408. 

  408.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    409. 

  409.     info.parent.status_mask = 1ull<<3 /* npi */;
    410. 

  410.     info.func               = __cvmx_error_display;
    411. 

  411.     info.user_info          = (long)
    412. 

  412.         "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
    413. 

  413.         "    than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n";
    414. 

  414.     fail |= cvmx_error_add(&info);
    415. 

  415. 

  416.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    417. 

  417.     info.status_addr        = CVMX_NPI_INT_SUM;
    418. 

  418.     info.status_mask        = 1ull<<7 /* i0_rtout */;
    419. 

  419.     info.enable_addr        = CVMX_NPI_INT_ENB;
    420. 

  420.     info.enable_mask        = 1ull<<7 /* i0_rtout */;
    421. 

  421.     info.flags              = 0;
    422. 

  422.     info.group              = CVMX_ERROR_GROUP_PCI;
    423. 

  423.     info.group_index        = 0;
    424. 

  424.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    425. 

  425.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    426. 

  426.     info.parent.status_mask = 1ull<<3 /* npi */;
    427. 

  427.     info.func               = __cvmx_error_display;
    428. 

  428.     info.user_info          = (long)
    429. 

  429.         "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
    430. 

  430.         "    read instructions.\n";
    431. 

  431.     fail |= cvmx_error_add(&info);
    432. 

  432. 

  433.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    434. 

  434.     info.status_addr        = CVMX_NPI_INT_SUM;
    435. 

  435.     info.status_mask        = 1ull<<8 /* i1_rtout */;
    436. 

  436.     info.enable_addr        = CVMX_NPI_INT_ENB;
    437. 

  437.     info.enable_mask        = 1ull<<8 /* i1_rtout */;
    438. 

  438.     info.flags              = 0;
    439. 

  439.     info.group              = CVMX_ERROR_GROUP_PCI;
    440. 

  440.     info.group_index        = 0;
    441. 

  441.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    442. 

  442.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    443. 

  443.     info.parent.status_mask = 1ull<<3 /* npi */;
    444. 

  444.     info.func               = __cvmx_error_display;
    445. 

  445.     info.user_info          = (long)
    446. 

  446.         "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
    447. 

  447.         "    read instructions.\n";
    448. 

  448.     fail |= cvmx_error_add(&info);
    449. 

  449. 

  450.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    451. 

  451.     info.status_addr        = CVMX_NPI_INT_SUM;
    452. 

  452.     info.status_mask        = 1ull<<9 /* i2_rtout */;
    453. 

  453.     info.enable_addr        = CVMX_NPI_INT_ENB;
    454. 

  454.     info.enable_mask        = 1ull<<9 /* i2_rtout */;
    455. 

  455.     info.flags              = 0;
    456. 

  456.     info.group              = CVMX_ERROR_GROUP_PCI;
    457. 

  457.     info.group_index        = 0;
    458. 

  458.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    459. 

  459.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    460. 

  460.     info.parent.status_mask = 1ull<<3 /* npi */;
    461. 

  461.     info.func               = __cvmx_error_display;
    462. 

  462.     info.user_info          = (long)
    463. 

  463.         "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
    464. 

  464.         "    read instructions.\n";
    465. 

  465.     fail |= cvmx_error_add(&info);
    466. 

  466. 

  467.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    468. 

  468.     info.status_addr        = CVMX_NPI_INT_SUM;
    469. 

  469.     info.status_mask        = 1ull<<10 /* i3_rtout */;
    470. 

  470.     info.enable_addr        = CVMX_NPI_INT_ENB;
    471. 

  471.     info.enable_mask        = 1ull<<10 /* i3_rtout */;
    472. 

  472.     info.flags              = 0;
    473. 

  473.     info.group              = CVMX_ERROR_GROUP_PCI;
    474. 

  474.     info.group_index        = 0;
    475. 

  475.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    476. 

  476.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    477. 

  477.     info.parent.status_mask = 1ull<<3 /* npi */;
    478. 

  478.     info.func               = __cvmx_error_display;
    479. 

  479.     info.user_info          = (long)
    480. 

  480.         "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
    481. 

  481.         "    read instructions.\n";
    482. 

  482.     fail |= cvmx_error_add(&info);
    483. 

  483. 

  484.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    485. 

  485.     info.status_addr        = CVMX_NPI_INT_SUM;
    486. 

  486.     info.status_mask        = 1ull<<11 /* i0_overf */;
    487. 

  487.     info.enable_addr        = CVMX_NPI_INT_ENB;
    488. 

  488.     info.enable_mask        = 1ull<<11 /* i0_overf */;
    489. 

  489.     info.flags              = 0;
    490. 

  490.     info.group              = CVMX_ERROR_GROUP_PCI;
    491. 

  491.     info.group_index        = 0;
    492. 

  492.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    493. 

  493.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    494. 

  494.     info.parent.status_mask = 1ull<<3 /* npi */;
    495. 

  495.     info.func               = __cvmx_error_display;
    496. 

  496.     info.user_info          = (long)
    497. 

  497.         "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
    498. 

  498.         "    doorbell count was set.\n";
    499. 

  499.     fail |= cvmx_error_add(&info);
    500. 

  500. 

  501.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    502. 

  502.     info.status_addr        = CVMX_NPI_INT_SUM;
    503. 

  503.     info.status_mask        = 1ull<<12 /* i1_overf */;
    504. 

  504.     info.enable_addr        = CVMX_NPI_INT_ENB;
    505. 

  505.     info.enable_mask        = 1ull<<12 /* i1_overf */;
    506. 

  506.     info.flags              = 0;
    507. 

  507.     info.group              = CVMX_ERROR_GROUP_PCI;
    508. 

  508.     info.group_index        = 0;
    509. 

  509.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    510. 

  510.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    511. 

  511.     info.parent.status_mask = 1ull<<3 /* npi */;
    512. 

  512.     info.func               = __cvmx_error_display;
    513. 

  513.     info.user_info          = (long)
    514. 

  514.         "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
    515. 

  515.         "    doorbell count was set.\n";
    516. 

  516.     fail |= cvmx_error_add(&info);
    517. 

  517. 

  518.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    519. 

  519.     info.status_addr        = CVMX_NPI_INT_SUM;
    520. 

  520.     info.status_mask        = 1ull<<13 /* i2_overf */;
    521. 

  521.     info.enable_addr        = CVMX_NPI_INT_ENB;
    522. 

  522.     info.enable_mask        = 1ull<<13 /* i2_overf */;
    523. 

  523.     info.flags              = 0;
    524. 

  524.     info.group              = CVMX_ERROR_GROUP_PCI;
    525. 

  525.     info.group_index        = 0;
    526. 

  526.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    527. 

  527.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    528. 

  528.     info.parent.status_mask = 1ull<<3 /* npi */;
    529. 

  529.     info.func               = __cvmx_error_display;
    530. 

  530.     info.user_info          = (long)
    531. 

  531.         "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
    532. 

  532.         "    doorbell count was set.\n";
    533. 

  533.     fail |= cvmx_error_add(&info);
    534. 

  534. 

  535.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    536. 

  536.     info.status_addr        = CVMX_NPI_INT_SUM;
    537. 

  537.     info.status_mask        = 1ull<<14 /* i3_overf */;
    538. 

  538.     info.enable_addr        = CVMX_NPI_INT_ENB;
    539. 

  539.     info.enable_mask        = 1ull<<14 /* i3_overf */;
    540. 

  540.     info.flags              = 0;
    541. 

  541.     info.group              = CVMX_ERROR_GROUP_PCI;
    542. 

  542.     info.group_index        = 0;
    543. 

  543.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    544. 

  544.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    545. 

  545.     info.parent.status_mask = 1ull<<3 /* npi */;
    546. 

  546.     info.func               = __cvmx_error_display;
    547. 

  547.     info.user_info          = (long)
    548. 

  548.         "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
    549. 

  549.         "    doorbell count was set.\n";
    550. 

  550.     fail |= cvmx_error_add(&info);
    551. 

  551. 

  552.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    553. 

  553.     info.status_addr        = CVMX_NPI_INT_SUM;
    554. 

  554.     info.status_mask        = 1ull<<15 /* p0_rtout */;
    555. 

  555.     info.enable_addr        = CVMX_NPI_INT_ENB;
    556. 

  556.     info.enable_mask        = 1ull<<15 /* p0_rtout */;
    557. 

  557.     info.flags              = 0;
    558. 

  558.     info.group              = CVMX_ERROR_GROUP_PCI;
    559. 

  559.     info.group_index        = 0;
    560. 

  560.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    561. 

  561.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    562. 

  562.     info.parent.status_mask = 1ull<<3 /* npi */;
    563. 

  563.     info.func               = __cvmx_error_display;
    564. 

  564.     info.user_info          = (long)
    565. 

  565.         "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
    566. 

  566.         "    read packet data.\n";
    567. 

  567.     fail |= cvmx_error_add(&info);
    568. 

  568. 

  569.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    570. 

  570.     info.status_addr        = CVMX_NPI_INT_SUM;
    571. 

  571.     info.status_mask        = 1ull<<16 /* p1_rtout */;
    572. 

  572.     info.enable_addr        = CVMX_NPI_INT_ENB;
    573. 

  573.     info.enable_mask        = 1ull<<16 /* p1_rtout */;
    574. 

  574.     info.flags              = 0;
    575. 

  575.     info.group              = CVMX_ERROR_GROUP_PCI;
    576. 

  576.     info.group_index        = 0;
    577. 

  577.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    578. 

  578.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    579. 

  579.     info.parent.status_mask = 1ull<<3 /* npi */;
    580. 

  580.     info.func               = __cvmx_error_display;
    581. 

  581.     info.user_info          = (long)
    582. 

  582.         "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
    583. 

  583.         "    read packet data.\n";
    584. 

  584.     fail |= cvmx_error_add(&info);
    585. 

  585. 

  586.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    587. 

  587.     info.status_addr        = CVMX_NPI_INT_SUM;
    588. 

  588.     info.status_mask        = 1ull<<17 /* p2_rtout */;
    589. 

  589.     info.enable_addr        = CVMX_NPI_INT_ENB;
    590. 

  590.     info.enable_mask        = 1ull<<17 /* p2_rtout */;
    591. 

  591.     info.flags              = 0;
    592. 

  592.     info.group              = CVMX_ERROR_GROUP_PCI;
    593. 

  593.     info.group_index        = 0;
    594. 

  594.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    595. 

  595.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    596. 

  596.     info.parent.status_mask = 1ull<<3 /* npi */;
    597. 

  597.     info.func               = __cvmx_error_display;
    598. 

  598.     info.user_info          = (long)
    599. 

  599.         "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
    600. 

  600.         "    read packet data.\n";
    601. 

  601.     fail |= cvmx_error_add(&info);
    602. 

  602. 

  603.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    604. 

  604.     info.status_addr        = CVMX_NPI_INT_SUM;
    605. 

  605.     info.status_mask        = 1ull<<18 /* p3_rtout */;
    606. 

  606.     info.enable_addr        = CVMX_NPI_INT_ENB;
    607. 

  607.     info.enable_mask        = 1ull<<18 /* p3_rtout */;
    608. 

  608.     info.flags              = 0;
    609. 

  609.     info.group              = CVMX_ERROR_GROUP_PCI;
    610. 

  610.     info.group_index        = 0;
    611. 

  611.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    612. 

  612.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    613. 

  613.     info.parent.status_mask = 1ull<<3 /* npi */;
    614. 

  614.     info.func               = __cvmx_error_display;
    615. 

  615.     info.user_info          = (long)
    616. 

  616.         "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
    617. 

  617.         "    read packet data.\n";
    618. 

  618.     fail |= cvmx_error_add(&info);
    619. 

  619. 

  620.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    621. 

  621.     info.status_addr        = CVMX_NPI_INT_SUM;
    622. 

  622.     info.status_mask        = 1ull<<19 /* p0_perr */;
    623. 

  623.     info.enable_addr        = CVMX_NPI_INT_ENB;
    624. 

  624.     info.enable_mask        = 1ull<<19 /* p0_perr */;
    625. 

  625.     info.flags              = 0;
    626. 

  626.     info.group              = CVMX_ERROR_GROUP_PCI;
    627. 

  627.     info.group_index        = 0;
    628. 

  628.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    629. 

  629.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    630. 

  630.     info.parent.status_mask = 1ull<<3 /* npi */;
    631. 

  631.     info.func               = __cvmx_error_display;
    632. 

  632.     info.user_info          = (long)
    633. 

  633.         "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
    634. 

  634.         "    data this bit may be set.\n";
    635. 

  635.     fail |= cvmx_error_add(&info);
    636. 

  636. 

  637.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    638. 

  638.     info.status_addr        = CVMX_NPI_INT_SUM;
    639. 

  639.     info.status_mask        = 1ull<<20 /* p1_perr */;
    640. 

  640.     info.enable_addr        = CVMX_NPI_INT_ENB;
    641. 

  641.     info.enable_mask        = 1ull<<20 /* p1_perr */;
    642. 

  642.     info.flags              = 0;
    643. 

  643.     info.group              = CVMX_ERROR_GROUP_PCI;
    644. 

  644.     info.group_index        = 0;
    645. 

  645.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    646. 

  646.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    647. 

  647.     info.parent.status_mask = 1ull<<3 /* npi */;
    648. 

  648.     info.func               = __cvmx_error_display;
    649. 

  649.     info.user_info          = (long)
    650. 

  650.         "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
    651. 

  651.         "    data this bit may be set.\n";
    652. 

  652.     fail |= cvmx_error_add(&info);
    653. 

  653. 

  654.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    655. 

  655.     info.status_addr        = CVMX_NPI_INT_SUM;
    656. 

  656.     info.status_mask        = 1ull<<21 /* p2_perr */;
    657. 

  657.     info.enable_addr        = CVMX_NPI_INT_ENB;
    658. 

  658.     info.enable_mask        = 1ull<<21 /* p2_perr */;
    659. 

  659.     info.flags              = 0;
    660. 

  660.     info.group              = CVMX_ERROR_GROUP_PCI;
    661. 

  661.     info.group_index        = 0;
    662. 

  662.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    663. 

  663.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    664. 

  664.     info.parent.status_mask = 1ull<<3 /* npi */;
    665. 

  665.     info.func               = __cvmx_error_display;
    666. 

  666.     info.user_info          = (long)
    667. 

  667.         "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
    668. 

  668.         "    data this bit may be set.\n";
    669. 

  669.     fail |= cvmx_error_add(&info);
    670. 

  670. 

  671.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    672. 

  672.     info.status_addr        = CVMX_NPI_INT_SUM;
    673. 

  673.     info.status_mask        = 1ull<<22 /* p3_perr */;
    674. 

  674.     info.enable_addr        = CVMX_NPI_INT_ENB;
    675. 

  675.     info.enable_mask        = 1ull<<22 /* p3_perr */;
    676. 

  676.     info.flags              = 0;
    677. 

  677.     info.group              = CVMX_ERROR_GROUP_PCI;
    678. 

  678.     info.group_index        = 0;
    679. 

  679.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    680. 

  680.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    681. 

  681.     info.parent.status_mask = 1ull<<3 /* npi */;
    682. 

  682.     info.func               = __cvmx_error_display;
    683. 

  683.     info.user_info          = (long)
    684. 

  684.         "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
    685. 

  685.         "    data this bit may be set.\n";
    686. 

  686.     fail |= cvmx_error_add(&info);
    687. 

  687. 

  688.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    689. 

  689.     info.status_addr        = CVMX_NPI_INT_SUM;
    690. 

  690.     info.status_mask        = 1ull<<23 /* g0_rtout */;
    691. 

  691.     info.enable_addr        = CVMX_NPI_INT_ENB;
    692. 

  692.     info.enable_mask        = 1ull<<23 /* g0_rtout */;
    693. 

  693.     info.flags              = 0;
    694. 

  694.     info.group              = CVMX_ERROR_GROUP_PCI;
    695. 

  695.     info.group_index        = 0;
    696. 

  696.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    697. 

  697.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    698. 

  698.     info.parent.status_mask = 1ull<<3 /* npi */;
    699. 

  699.     info.func               = __cvmx_error_display;
    700. 

  700.     info.user_info          = (long)
    701. 

  701.         "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
    702. 

  702.         "    read a gather list.\n";
    703. 

  703.     fail |= cvmx_error_add(&info);
    704. 

  704. 

  705.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    706. 

  706.     info.status_addr        = CVMX_NPI_INT_SUM;
    707. 

  707.     info.status_mask        = 1ull<<24 /* g1_rtout */;
    708. 

  708.     info.enable_addr        = CVMX_NPI_INT_ENB;
    709. 

  709.     info.enable_mask        = 1ull<<24 /* g1_rtout */;
    710. 

  710.     info.flags              = 0;
    711. 

  711.     info.group              = CVMX_ERROR_GROUP_PCI;
    712. 

  712.     info.group_index        = 0;
    713. 

  713.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    714. 

  714.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    715. 

  715.     info.parent.status_mask = 1ull<<3 /* npi */;
    716. 

  716.     info.func               = __cvmx_error_display;
    717. 

  717.     info.user_info          = (long)
    718. 

  718.         "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
    719. 

  719.         "    read a gather list.\n";
    720. 

  720.     fail |= cvmx_error_add(&info);
    721. 

  721. 

  722.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    723. 

  723.     info.status_addr        = CVMX_NPI_INT_SUM;
    724. 

  724.     info.status_mask        = 1ull<<25 /* g2_rtout */;
    725. 

  725.     info.enable_addr        = CVMX_NPI_INT_ENB;
    726. 

  726.     info.enable_mask        = 1ull<<25 /* g2_rtout */;
    727. 

  727.     info.flags              = 0;
    728. 

  728.     info.group              = CVMX_ERROR_GROUP_PCI;
    729. 

  729.     info.group_index        = 0;
    730. 

  730.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    731. 

  731.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    732. 

  732.     info.parent.status_mask = 1ull<<3 /* npi */;
    733. 

  733.     info.func               = __cvmx_error_display;
    734. 

  734.     info.user_info          = (long)
    735. 

  735.         "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
    736. 

  736.         "    read a gather list.\n";
    737. 

  737.     fail |= cvmx_error_add(&info);
    738. 

  738. 

  739.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    740. 

  740.     info.status_addr        = CVMX_NPI_INT_SUM;
    741. 

  741.     info.status_mask        = 1ull<<26 /* g3_rtout */;
    742. 

  742.     info.enable_addr        = CVMX_NPI_INT_ENB;
    743. 

  743.     info.enable_mask        = 1ull<<26 /* g3_rtout */;
    744. 

  744.     info.flags              = 0;
    745. 

  745.     info.group              = CVMX_ERROR_GROUP_PCI;
    746. 

  746.     info.group_index        = 0;
    747. 

  747.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    748. 

  748.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    749. 

  749.     info.parent.status_mask = 1ull<<3 /* npi */;
    750. 

  750.     info.func               = __cvmx_error_display;
    751. 

  751.     info.user_info          = (long)
    752. 

  752.         "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
    753. 

  753.         "    read a gather list.\n";
    754. 

  754.     fail |= cvmx_error_add(&info);
    755. 

  755. 

  756.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    757. 

  757.     info.status_addr        = CVMX_NPI_INT_SUM;
    758. 

  758.     info.status_mask        = 1ull<<27 /* p0_pperr */;
    759. 

  759.     info.enable_addr        = CVMX_NPI_INT_ENB;
    760. 

  760.     info.enable_mask        = 1ull<<27 /* p0_pperr */;
    761. 

  761.     info.flags              = 0;
    762. 

  762.     info.group              = CVMX_ERROR_GROUP_PCI;
    763. 

  763.     info.group_index        = 0;
    764. 

  764.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    765. 

  765.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    766. 

  766.     info.parent.status_mask = 1ull<<3 /* npi */;
    767. 

  767.     info.func               = __cvmx_error_display;
    768. 

  768.     info.user_info          = (long)
    769. 

  769.         "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
    770. 

  770.         "    pointer-pair, this bit may be set.\n";
    771. 

  771.     fail |= cvmx_error_add(&info);
    772. 

  772. 

  773.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    774. 

  774.     info.status_addr        = CVMX_NPI_INT_SUM;
    775. 

  775.     info.status_mask        = 1ull<<28 /* p1_pperr */;
    776. 

  776.     info.enable_addr        = CVMX_NPI_INT_ENB;
    777. 

  777.     info.enable_mask        = 1ull<<28 /* p1_pperr */;
    778. 

  778.     info.flags              = 0;
    779. 

  779.     info.group              = CVMX_ERROR_GROUP_PCI;
    780. 

  780.     info.group_index        = 0;
    781. 

  781.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    782. 

  782.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    783. 

  783.     info.parent.status_mask = 1ull<<3 /* npi */;
    784. 

  784.     info.func               = __cvmx_error_display;
    785. 

  785.     info.user_info          = (long)
    786. 

  786.         "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
    787. 

  787.         "    pointer-pair, this bit may be set.\n";
    788. 

  788.     fail |= cvmx_error_add(&info);
    789. 

  789. 

  790.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    791. 

  791.     info.status_addr        = CVMX_NPI_INT_SUM;
    792. 

  792.     info.status_mask        = 1ull<<29 /* p2_pperr */;
    793. 

  793.     info.enable_addr        = CVMX_NPI_INT_ENB;
    794. 

  794.     info.enable_mask        = 1ull<<29 /* p2_pperr */;
    795. 

  795.     info.flags              = 0;
    796. 

  796.     info.group              = CVMX_ERROR_GROUP_PCI;
    797. 

  797.     info.group_index        = 0;
    798. 

  798.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    799. 

  799.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    800. 

  800.     info.parent.status_mask = 1ull<<3 /* npi */;
    801. 

  801.     info.func               = __cvmx_error_display;
    802. 

  802.     info.user_info          = (long)
    803. 

  803.         "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
    804. 

  804.         "    pointer-pair, this bit may be set.\n";
    805. 

  805.     fail |= cvmx_error_add(&info);
    806. 

  806. 

  807.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    808. 

  808.     info.status_addr        = CVMX_NPI_INT_SUM;
    809. 

  809.     info.status_mask        = 1ull<<30 /* p3_pperr */;
    810. 

  810.     info.enable_addr        = CVMX_NPI_INT_ENB;
    811. 

  811.     info.enable_mask        = 1ull<<30 /* p3_pperr */;
    812. 

  812.     info.flags              = 0;
    813. 

  813.     info.group              = CVMX_ERROR_GROUP_PCI;
    814. 

  814.     info.group_index        = 0;
    815. 

  815.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    816. 

  816.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    817. 

  817.     info.parent.status_mask = 1ull<<3 /* npi */;
    818. 

  818.     info.func               = __cvmx_error_display;
    819. 

  819.     info.user_info          = (long)
    820. 

  820.         "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
    821. 

  821.         "    pointer-pair, this bit may be set.\n";
    822. 

  822.     fail |= cvmx_error_add(&info);
    823. 

  823. 

  824.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    825. 

  825.     info.status_addr        = CVMX_NPI_INT_SUM;
    826. 

  826.     info.status_mask        = 1ull<<31 /* p0_ptout */;
    827. 

  827.     info.enable_addr        = CVMX_NPI_INT_ENB;
    828. 

  828.     info.enable_mask        = 1ull<<31 /* p0_ptout */;
    829. 

  829.     info.flags              = 0;
    830. 

  830.     info.group              = CVMX_ERROR_GROUP_PCI;
    831. 

  831.     info.group_index        = 0;
    832. 

  832.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    833. 

  833.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    834. 

  834.     info.parent.status_mask = 1ull<<3 /* npi */;
    835. 

  835.     info.func               = __cvmx_error_display;
    836. 

  836.     info.user_info          = (long)
    837. 

  837.         "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
    838. 

  838.         "    pair.\n";
    839. 

  839.     fail |= cvmx_error_add(&info);
    840. 

  840. 

  841.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    842. 

  842.     info.status_addr        = CVMX_NPI_INT_SUM;
    843. 

  843.     info.status_mask        = 1ull<<32 /* p1_ptout */;
    844. 

  844.     info.enable_addr        = CVMX_NPI_INT_ENB;
    845. 

  845.     info.enable_mask        = 1ull<<32 /* p1_ptout */;
    846. 

  846.     info.flags              = 0;
    847. 

  847.     info.group              = CVMX_ERROR_GROUP_PCI;
    848. 

  848.     info.group_index        = 0;
    849. 

  849.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    850. 

  850.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    851. 

  851.     info.parent.status_mask = 1ull<<3 /* npi */;
    852. 

  852.     info.func               = __cvmx_error_display;
    853. 

  853.     info.user_info          = (long)
    854. 

  854.         "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
    855. 

  855.         "    pair.\n";
    856. 

  856.     fail |= cvmx_error_add(&info);
    857. 

  857. 

  858.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    859. 

  859.     info.status_addr        = CVMX_NPI_INT_SUM;
    860. 

  860.     info.status_mask        = 1ull<<33 /* p2_ptout */;
    861. 

  861.     info.enable_addr        = CVMX_NPI_INT_ENB;
    862. 

  862.     info.enable_mask        = 1ull<<33 /* p2_ptout */;
    863. 

  863.     info.flags              = 0;
    864. 

  864.     info.group              = CVMX_ERROR_GROUP_PCI;
    865. 

  865.     info.group_index        = 0;
    866. 

  866.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    867. 

  867.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    868. 

  868.     info.parent.status_mask = 1ull<<3 /* npi */;
    869. 

  869.     info.func               = __cvmx_error_display;
    870. 

  870.     info.user_info          = (long)
    871. 

  871.         "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
    872. 

  872.         "    pair.\n";
    873. 

  873.     fail |= cvmx_error_add(&info);
    874. 

  874. 

  875.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    876. 

  876.     info.status_addr        = CVMX_NPI_INT_SUM;
    877. 

  877.     info.status_mask        = 1ull<<34 /* p3_ptout */;
    878. 

  878.     info.enable_addr        = CVMX_NPI_INT_ENB;
    879. 

  879.     info.enable_mask        = 1ull<<34 /* p3_ptout */;
    880. 

  880.     info.flags              = 0;
    881. 

  881.     info.group              = CVMX_ERROR_GROUP_PCI;
    882. 

  882.     info.group_index        = 0;
    883. 

  883.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    884. 

  884.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    885. 

  885.     info.parent.status_mask = 1ull<<3 /* npi */;
    886. 

  886.     info.func               = __cvmx_error_display;
    887. 

  887.     info.user_info          = (long)
    888. 

  888.         "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
    889. 

  889.         "    pair.\n";
    890. 

  890.     fail |= cvmx_error_add(&info);
    891. 

  891. 

  892.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    893. 

  893.     info.status_addr        = CVMX_NPI_INT_SUM;
    894. 

  894.     info.status_mask        = 1ull<<35 /* i0_pperr */;
    895. 

  895.     info.enable_addr        = CVMX_NPI_INT_ENB;
    896. 

  896.     info.enable_mask        = 1ull<<35 /* i0_pperr */;
    897. 

  897.     info.flags              = 0;
    898. 

  898.     info.group              = CVMX_ERROR_GROUP_PCI;
    899. 

  899.     info.group_index        = 0;
    900. 

  900.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    901. 

  901.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    902. 

  902.     info.parent.status_mask = 1ull<<3 /* npi */;
    903. 

  903.     info.func               = __cvmx_error_display;
    904. 

  904.     info.user_info          = (long)
    905. 

  905.         "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
    906. 

  906.         "    this bit may be set.\n";
    907. 

  907.     fail |= cvmx_error_add(&info);
    908. 

  908. 

  909.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    910. 

  910.     info.status_addr        = CVMX_NPI_INT_SUM;
    911. 

  911.     info.status_mask        = 1ull<<36 /* i1_pperr */;
    912. 

  912.     info.enable_addr        = CVMX_NPI_INT_ENB;
    913. 

  913.     info.enable_mask        = 1ull<<36 /* i1_pperr */;
    914. 

  914.     info.flags              = 0;
    915. 

  915.     info.group              = CVMX_ERROR_GROUP_PCI;
    916. 

  916.     info.group_index        = 0;
    917. 

  917.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    918. 

  918.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    919. 

  919.     info.parent.status_mask = 1ull<<3 /* npi */;
    920. 

  920.     info.func               = __cvmx_error_display;
    921. 

  921.     info.user_info          = (long)
    922. 

  922.         "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
    923. 

  923.         "    this bit may be set.\n";
    924. 

  924.     fail |= cvmx_error_add(&info);
    925. 

  925. 

  926.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    927. 

  927.     info.status_addr        = CVMX_NPI_INT_SUM;
    928. 

  928.     info.status_mask        = 1ull<<37 /* i2_pperr */;
    929. 

  929.     info.enable_addr        = CVMX_NPI_INT_ENB;
    930. 

  930.     info.enable_mask        = 1ull<<37 /* i2_pperr */;
    931. 

  931.     info.flags              = 0;
    932. 

  932.     info.group              = CVMX_ERROR_GROUP_PCI;
    933. 

  933.     info.group_index        = 0;
    934. 

  934.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    935. 

  935.     info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
    936. 

  936.     info.parent.status_mask = 1ull<<3 /* npi */;
    937. 

  937.     info.func               = __cvmx_error_display;
    938. 

  938.     info.user_info          = (long)
    939. 

  939.         "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
    940. 

  940.         "    this bit may be set.\n";
    941. 

  941.     fail |= cvmx_error_add(&info);
    942. 

  942. 

  943.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    944. 

  944.     info.status_addr        = CVMX_NPI_INT_SUM;
    945. 

  945.     info.status_mask        = 1ull<<38 /* i3_pperr */;
    946. 

  946.     info.enable_addr        = CVMX_NPI_INT_ENB;
    947. 

  947.     info.enable_mask        = 1ull<<38 /* i3_pperr */;
    948. 

  948.     info.flags              = 0;
    949. 

  949.     info.group              = CVMX_ERROR_GROUP_PCI;
    950. 

  950.     info.group_index        = 0;
    951. 

  951.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    952. 

  952.     info.parent.status_addr = CVMX_NPI…
    953.

Large files files are truncated, but you can click here to view the full file