/sys/contrib/octeon-sdk/cvmx-error-init-cn38xx.c
C | 1290 lines | 1071 code | 69 blank | 150 comment | 0 complexity | 8f1c13e12513fe394b77046f44de47f2 MD5 | raw file
Possible License(s): MPL-2.0-no-copyleft-exception, BSD-3-Clause, LGPL-2.0, LGPL-2.1, BSD-2-Clause, 0BSD, JSON, AGPL-1.0, GPL-2.0
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- /***********************license start***************
- * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
- * reserved.
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- * * Neither the name of Cavium Networks nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
- * This Software, including technical data, may be subject to U.S. export control
- * laws, including the U.S. Export Administration Act and its associated
- * regulations, and may be subject to export or import regulations in other
- * countries.
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
- * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
- * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
- * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
- * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
- * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
- * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
- * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
- * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- ***********************license end**************************************/
- /**
- * @file
- *
- * Automatically generated error messages for cn38xx.
- *
- * This file is auto generated. Do not edit.
- *
- * <hr>$Revision$<hr>
- *
- * <hr><h2>Error tree for CN38XX</h2>
- * @dot
- * digraph cn38xx
- * {
- * rankdir=LR;
- * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
- * edge [fontsize=7, font=helvitica];
- * cvmx_root [label="ROOT|<root>root"];
- * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)"];
- * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
- * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1"];
- * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
- * cvmx_npi_rsl_int_blocks [label="NPI_RSL_INT_BLOCKS|<l2c>l2c|<npi>npi|<gmx0>gmx0|<gmx1>gmx1|<ipd>ipd|<spx0>spx0|<pow>pow|<spx1>spx1|<asx0>asx0|<asx1>asx1|<pko>pko|<tim>tim|<key>key|<mio>mio|<pip>pip|<fpa>fpa|<lmc>lmc|<dfa>dfa|<iob>iob|<zip>zip"];
- * cvmx_l2d_err [label="L2D_ERR|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2d_err [label="l2c"];
- * cvmx_l2t_err [label="L2T_ERR|<sec_err>sec_err|<ded_err>ded_err|<lckerr>lckerr|<lckerr2>lckerr2"];
- * cvmx_npi_rsl_int_blocks:l2c:e -> cvmx_l2t_err [label="l2c"];
- * cvmx_npi_int_sum [label="NPI_INT_SUM|<rml_rto>rml_rto|<rml_wto>rml_wto|<po0_2sml>po0_2sml|<po1_2sml>po1_2sml|<po2_2sml>po2_2sml|<po3_2sml>po3_2sml|<i0_rtout>i0_rtout|<i1_rtout>i1_rtout|<i2_rtout>i2_rtout|<i3_rtout>i3_rtout|<i0_overf>i0_overf|<i1_overf>i1_overf|<i2_overf>i2_overf|<i3_overf>i3_overf|<p0_rtout>p0_rtout|<p1_rtout>p1_rtout|<p2_rtout>p2_rtout|<p3_rtout>p3_rtout|<p0_perr>p0_perr|<p1_perr>p1_perr|<p2_perr>p2_perr|<p3_perr>p3_perr|<g0_rtout>g0_rtout|<g1_rtout>g1_rtout|<g2_rtout>g2_rtout|<g3_rtout>g3_rtout|<p0_pperr>p0_pperr|<p1_pperr>p1_pperr|<p2_pperr>p2_pperr|<p3_pperr>p3_pperr|<p0_ptout>p0_ptout|<p1_ptout>p1_ptout|<p2_ptout>p2_ptout|<p3_ptout>p3_ptout|<i0_pperr>i0_pperr|<i1_pperr>i1_pperr|<i2_pperr>i2_pperr|<i3_pperr>i3_pperr|<win_rto>win_rto|<p_dperr>p_dperr|<iobdma>iobdma|<fcr_s_e>fcr_s_e|<fcr_a_f>fcr_a_f|<pcr_s_e>pcr_s_e|<pcr_a_f>pcr_a_f|<q2_s_e>q2_s_e|<q2_a_f>q2_a_f|<q3_s_e>q3_s_e|<q3_a_f>q3_a_f|<com_s_e>com_s_e|<com_a_f>com_a_f|<pnc_s_e>pnc_s_e|<pnc_a_f>pnc_a_f|<rwx_s_e>rwx_s_e|<rdx_s_e>rdx_s_e|<pcf_p_e>pcf_p_e|<pcf_p_f>pcf_p_f|<pdf_p_e>pdf_p_e|<pdf_p_f>pdf_p_f|<q1_s_e>q1_s_e|<q1_a_f>q1_a_f|<pci_rsl>pci_rsl"];
- * cvmx_pci_int_sum2 [label="NPI_PCI_INT_SUM2|<tr_wabt>tr_wabt|<mr_wabt>mr_wabt|<mr_wtto>mr_wtto|<tr_abt>tr_abt|<mr_abt>mr_abt|<mr_tto>mr_tto|<msi_per>msi_per|<msi_tabt>msi_tabt|<msi_mabt>msi_mabt|<msc_msg>msc_msg|<tsr_abt>tsr_abt|<serr>serr|<aperr>aperr|<dperr>dperr|<ill_rwr>ill_rwr|<ill_rrd>ill_rrd|<win_wr>win_wr|<ill_wr>ill_wr|<ill_rd>ill_rd"];
- * cvmx_npi_int_sum:pci_rsl:e -> cvmx_pci_int_sum2 [label="pci_rsl"];
- * cvmx_npi_rsl_int_blocks:npi:e -> cvmx_npi_int_sum [label="npi"];
- * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
- * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
- * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
- * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
- * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
- * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
- * cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_col>out_col|<ncb_ovr>ncb_ovr|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
- * cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
- * cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
- * cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
- * cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<maxerr>maxerr|<alnerr>alnerr|<lenerr>lenerr|<skperr>skperr|<niberr>niberr|<ovrerr>ovrerr"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
- * cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<ncb_nxa>ncb_nxa|<undflw>undflw"];
- * cvmx_npi_rsl_int_blocks:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
- * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
- * cvmx_npi_rsl_int_blocks:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
- * cvmx_spx0_int_reg [label="SPXX_INT_REG(0)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
- * cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_spx0_int_reg [label="spx0"];
- * cvmx_stx0_int_reg [label="STXX_INT_REG(0)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
- * cvmx_npi_rsl_int_blocks:spx0:e -> cvmx_stx0_int_reg [label="spx0"];
- * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
- * cvmx_npi_rsl_int_blocks:pow:e -> cvmx_pow_ecc_err [label="pow"];
- * cvmx_spx1_int_reg [label="SPXX_INT_REG(1)|<prtnxa>prtnxa|<abnorm>abnorm|<spiovr>spiovr|<clserr>clserr|<drwnng>drwnng|<rsverr>rsverr|<tpaovr>tpaovr|<diperr>diperr|<syncerr>syncerr|<calerr>calerr"];
- * cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_spx1_int_reg [label="spx1"];
- * cvmx_stx1_int_reg [label="STXX_INT_REG(1)|<calpar0>calpar0|<calpar1>calpar1|<ovrbst>ovrbst|<datovr>datovr|<diperr>diperr|<nosync>nosync|<unxfrm>unxfrm|<frmerr>frmerr"];
- * cvmx_npi_rsl_int_blocks:spx1:e -> cvmx_stx1_int_reg [label="spx1"];
- * cvmx_asx0_int_reg [label="ASXX_INT_REG(0)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
- * cvmx_npi_rsl_int_blocks:asx0:e -> cvmx_asx0_int_reg [label="asx0"];
- * cvmx_asx1_int_reg [label="ASXX_INT_REG(1)|<txpsh>txpsh|<txpop>txpop|<ovrflw>ovrflw"];
- * cvmx_npi_rsl_int_blocks:asx1:e -> cvmx_asx1_int_reg [label="asx1"];
- * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell"];
- * cvmx_npi_rsl_int_blocks:pko:e -> cvmx_pko_reg_error [label="pko"];
- * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
- * cvmx_npi_rsl_int_blocks:tim:e -> cvmx_tim_reg_error [label="tim"];
- * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
- * cvmx_npi_rsl_int_blocks:key:e -> cvmx_key_int_sum [label="key"];
- * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
- * cvmx_npi_rsl_int_blocks:mio:e -> cvmx_mio_boot_err [label="mio"];
- * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr"];
- * cvmx_npi_rsl_int_blocks:pip:e -> cvmx_pip_int_reg [label="pip"];
- * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
- * cvmx_npi_rsl_int_blocks:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
- * cvmx_lmc0_mem_cfg0 [label="LMCX_MEM_CFG0(0)|<sec_err>sec_err|<ded_err>ded_err"];
- * cvmx_npi_rsl_int_blocks:lmc:e -> cvmx_lmc0_mem_cfg0 [label="lmc"];
- * cvmx_dfa_err [label="DFA_ERR|<cp2sbe>cp2sbe|<cp2dbe>cp2dbe|<dtesbe>dtesbe|<dtedbe>dtedbe|<dteperr>dteperr|<cp2perr>cp2perr|<dblovf>dblovf"];
- * cvmx_npi_rsl_int_blocks:dfa:e -> cvmx_dfa_err [label="dfa"];
- * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop"];
- * cvmx_npi_rsl_int_blocks:iob:e -> cvmx_iob_int_sum [label="iob"];
- * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
- * cvmx_npi_rsl_int_blocks:zip:e -> cvmx_zip_error [label="zip"];
- * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
- * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
- * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
- * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
- * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
- * cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
- * cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
- * cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
- * cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
- * cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
- * cvmx_spx0_int_reg -> cvmx_stx0_int_reg [style=invis];
- * cvmx_spx1_int_reg -> cvmx_stx1_int_reg [style=invis];
- * cvmx_root:root:e -> cvmx_npi_rsl_int_blocks [label="root"];
- * }
- * @enddot
- */
- #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
- #include <asm/octeon/cvmx.h>
- #include <asm/octeon/cvmx-error.h>
- #include <asm/octeon/cvmx-error-custom.h>
- #include <asm/octeon/cvmx-csr-typedefs.h>
- #else
- #include "cvmx.h"
- #include "cvmx-error.h"
- #include "cvmx-error-custom.h"
- #endif
- int cvmx_error_initialize_cn38xx(void);
- int cvmx_error_initialize_cn38xx(void)
- {
- cvmx_error_info_t info;
- int fail = 0;
- /* CVMX_CIU_INTX_SUM0(0) */
- /* CVMX_CIU_INT_SUM1 */
- /* CVMX_NPI_RSL_INT_BLOCKS */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.status_mask = 0;
- info.enable_addr = 0;
- info.enable_mask = 0;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
- info.parent.status_addr = 0;
- info.parent.status_mask = 0;
- info.func = __cvmx_error_decode;
- info.user_info = 0;
- fail |= cvmx_error_add(&info);
- /* CVMX_L2D_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_sec_err;
- info.user_info = (long)
- "ERROR L2D_ERR[SEC_ERR]: L2D Single Error corrected (SEC)\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2D_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2D_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2d_err_ded_err;
- info.user_info = (long)
- "ERROR L2D_ERR[DED_ERR]: L2D Double Error detected (DED)\n";
- fail |= cvmx_error_add(&info);
- /* CVMX_L2T_ERR */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<3 /* sec_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<1 /* sec_intena */;
- info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_sec_err;
- info.user_info = (long)
- "ERROR L2T_ERR[SEC_ERR]: L2T Single Bit Error corrected (SEC)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for single bit errors(SBEs).\n"
- " This bit is set if ANY of the 8 sets contains an SBE.\n"
- " SBEs are auto corrected in HW and generate an\n"
- " interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<4 /* ded_err */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<2 /* ded_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_ded_err;
- info.user_info = (long)
- "ERROR L2T_ERR[DED_ERR]: L2T Double Bit Error detected (DED)\n"
- " During every L2 Tag Probe, all 8 sets Tag's (at a\n"
- " given index) are checked for double bit errors(DBEs).\n"
- " This bit is set if ANY of the 8 sets contains a DBE.\n"
- " DBEs also generated an interrupt(if enabled).\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<24 /* lckerr */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<25 /* lck_intena */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR]: SW attempted to LOCK DOWN the last available set of\n"
- " the INDEX (which is ignored by HW - but reported to SW).\n"
- " The LDD(L1 load-miss) for the LOCK operation is completed\n"
- " successfully, however the address is NOT locked.\n"
- " NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*]\n"
- " into account. For example, if diagnostic PPx has\n"
- " UMSKx defined to only use SETs [1:0], and SET1 had\n"
- " been previously LOCKED, then an attempt to LOCK the\n"
- " last available SET0 would result in a LCKERR. (This\n"
- " is to ensure that at least 1 SET at each INDEX is\n"
- " not LOCKED for general use by other PPs).\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_L2T_ERR;
- info.status_mask = 1ull<<26 /* lckerr2 */;
- info.enable_addr = CVMX_L2T_ERR;
- info.enable_mask = 1ull<<27 /* lck_intena2 */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_INTERNAL;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<16 /* l2c */;
- info.func = __cvmx_error_handle_l2t_err_lckerr2;
- info.user_info = (long)
- "ERROR L2T_ERR[LCKERR2]: HW detected a case where a Rd/Wr Miss from PP#n\n"
- " could not find an available/unlocked set (for\n"
- " replacement).\n"
- " Most likely, this is a result of SW mixing SET\n"
- " PARTITIONING with ADDRESS LOCKING. If SW allows\n"
- " another PP to LOCKDOWN all SETs available to PP#n,\n"
- " then a Rd/Wr Miss from PP#n will be unable\n"
- " to determine a 'valid' replacement set (since LOCKED\n"
- " addresses should NEVER be replaced).\n"
- " If such an event occurs, the HW will select the smallest\n"
- " available SET(specified by UMSK'x)' as the replacement\n"
- " set, and the address is unlocked.\n";
- fail |= cvmx_error_add(&info);
- /* CVMX_NPI_INT_SUM */
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<0 /* rml_rto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<0 /* rml_rto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_RTO]: Set '1' when the RML does not receive read data\n"
- " back from a RSL after sending a read command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<1 /* rml_wto */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<1 /* rml_wto */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[RML_WTO]: Set '1' when the RML does not receive a commit\n"
- " back from a RSL after sending a write command to\n"
- " a RSL.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<3 /* po0_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<3 /* po0_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO0_2SML]: The packet being sent out on Port0 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<4 /* po1_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<4 /* po1_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO1_2SML]: The packet being sent out on Port1 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<5 /* po2_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<5 /* po2_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO2_2SML]: The packet being sent out on Port2 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<6 /* po3_2sml */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<6 /* po3_2sml */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[PO3_2SML]: The packet being sent out on Port3 is smaller\n"
- " than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<7 /* i0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<7 /* i0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<8 /* i1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<8 /* i1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<9 /* i2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<9 /* i2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<10 /* i3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<10 /* i3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read instructions.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<11 /* i0_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<11 /* i0_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_OVERF]: Port-0 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<12 /* i1_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<12 /* i1_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_OVERF]: Port-1 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<13 /* i2_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<13 /* i2_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_OVERF]: Port-2 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<14 /* i3_overf */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<14 /* i3_overf */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I3_OVERF]: Port-3 had a doorbell overflow. Bit[31] of the\n"
- " doorbell count was set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<15 /* p0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<15 /* p0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<16 /* p1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<16 /* p1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<17 /* p2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<17 /* p2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<18 /* p3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<18 /* p3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read packet data.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<19 /* p0_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<19 /* p0_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<20 /* p1_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<20 /* p1_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<21 /* p2_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<21 /* p2_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<22 /* p3_perr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<22 /* p3_perr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PERR]: If a parity error occured on the port's packet\n"
- " data this bit may be set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<23 /* g0_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<23 /* g0_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G0_RTOUT]: Port-0 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<24 /* g1_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<24 /* g1_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G1_RTOUT]: Port-1 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<25 /* g2_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<25 /* g2_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G2_RTOUT]: Port-2 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<26 /* g3_rtout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<26 /* g3_rtout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[G3_RTOUT]: Port-3 had a read timeout while attempting to\n"
- " read a gather list.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<27 /* p0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<27 /* p0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<28 /* p1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<28 /* p1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<29 /* p2_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<29 /* p2_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<30 /* p3_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<30 /* p3_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PPERR]: If a parity error occured on the port DATA/INFO\n"
- " pointer-pair, this bit may be set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<31 /* p0_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<31 /* p0_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P0_PTOUT]: Port-0 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<32 /* p1_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<32 /* p1_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P1_PTOUT]: Port-1 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<33 /* p2_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<33 /* p2_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P2_PTOUT]: Port-2 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<34 /* p3_ptout */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<34 /* p3_ptout */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[P3_PTOUT]: Port-3 output had a read timeout on a DATA/INFO\n"
- " pair.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<35 /* i0_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<35 /* i0_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I0_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<36 /* i1_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<36 /* i1_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I1_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<37 /* i2_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<37 /* i2_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI_RSL_INT_BLOCKS;
- info.parent.status_mask = 1ull<<3 /* npi */;
- info.func = __cvmx_error_display;
- info.user_info = (long)
- "ERROR NPI_INT_SUM[I2_PPERR]: If a parity error occured on the port's instruction\n"
- " this bit may be set.\n";
- fail |= cvmx_error_add(&info);
- info.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.status_addr = CVMX_NPI_INT_SUM;
- info.status_mask = 1ull<<38 /* i3_pperr */;
- info.enable_addr = CVMX_NPI_INT_ENB;
- info.enable_mask = 1ull<<38 /* i3_pperr */;
- info.flags = 0;
- info.group = CVMX_ERROR_GROUP_PCI;
- info.group_index = 0;
- info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
- info.parent.status_addr = CVMX_NPI…
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