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/sys/contrib/octeon-sdk/cvmx-error-init-cn63xx.c

https://bitbucket.org/freebsd/freebsd-head/
C | 1226 lines | 978 code | 59 blank | 189 comment | 0 complexity | 2599f849b6c1cecc46561fd43ec0d950 MD5 | raw file
Possible License(s): MPL-2.0-no-copyleft-exception, BSD-3-Clause, LGPL-2.0, LGPL-2.1, BSD-2-Clause, 0BSD, JSON, AGPL-1.0, GPL-2.0

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  1. /***********************license start***************
    2. 

  2.  * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
    3. 

  3.  * reserved.
    4. 

  4.  *
    5. 

  5.  *
    6. 

  6.  * Redistribution and use in source and binary forms, with or without
    7. 

  7.  * modification, are permitted provided that the following conditions are
    8. 

  8.  * met:
    9. 

  9.  *
    10. 

  10.  *   * Redistributions of source code must retain the above copyright
    11. 

  11.  *     notice, this list of conditions and the following disclaimer.
    12. 

  12.  *
    13. 

  13.  *   * Redistributions in binary form must reproduce the above
    14. 

  14.  *     copyright notice, this list of conditions and the following
    15. 

  15.  *     disclaimer in the documentation and/or other materials provided
    16. 

  16.  *     with the distribution.
    17. 

    18. 

  18.  *   * Neither the name of Cavium Networks nor the names of
    19. 

  19.  *     its contributors may be used to endorse or promote products
    20. 

  20.  *     derived from this software without specific prior written
    21. 

  21.  *     permission.
    22. 

    23. 

  23.  * This Software, including technical data, may be subject to U.S. export  control
    24. 

  24.  * laws, including the U.S. Export Administration Act and its  associated
    25. 

  25.  * regulations, and may be subject to export or import  regulations in other
    26. 

  26.  * countries.
    27. 

    28. 

  28.  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
    29. 

  29.  * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
    30. 

  30.  * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
    31. 

  31.  * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
    32. 

  32.  * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
    33. 

  33.  * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
    34. 

  34.  * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
    35. 

  35.  * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
    36. 

  36.  * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
    37. 

  37.  * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
    38. 

  38.  ***********************license end**************************************/
    39. 

  39. 

  40. 

  41. /**
    42. 

  42.  * @file
    43. 

  43.  *
    44. 

  44.  * Automatically generated error messages for cn63xx.
    45. 

  45.  *
    46. 

  46.  * This file is auto generated. Do not edit.
    47. 

  47.  *
    48. 

  48.  * <hr>$Revision$<hr>
    49. 

  49.  *
    50. 

  50.  * <hr><h2>Error tree for CN63XX</h2>
    51. 

  51.  * @dot
    52. 

  52.  * digraph cn63xx
    53. 

  53.  * {
    54. 

  54.  *     rankdir=LR;
    55. 

  55.  *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
    56. 

  56.  *     edge [fontsize=7, font=helvitica];
    57. 

  57.  *     cvmx_root [label="ROOT|<root>root"];
    58. 

  58.  *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
    59. 

  59.  *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
    60. 

  60.  *     cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
    61. 

  61.  *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
    62. 

  62.  *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
    63. 

  63.  *     cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
    64. 

  64.  *     cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
    65. 

  65.  *     cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
    66. 

  66.  *     cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
    67. 

  67.  *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
    68. 

  68.  *     cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<usb>usb|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<srio1>srio1|<sli>sli|<dpi>dpi"];
    69. 

  69.  *     cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
    70. 

  70.  *     cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
    71. 

  71.  *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
    72. 

  72.  *     cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
    73. 

  73.  *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
    74. 

  74.  *     cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
    75. 

  75.  *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
    76. 

  76.  *     cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
    77. 

  77.  *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
    78. 

  78.  *     cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
    79. 

  79.  *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
    80. 

  80.  *     cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
    81. 

  81.  *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
    82. 

  82.  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
    83. 

  83.  *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
    84. 

  84.  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
    85. 

  85.  *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
    86. 

  86.  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
    87. 

  87.  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
    88. 

  88.  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
    89. 

  89.  *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
    90. 

  90.  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
    91. 

  91.  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
    92. 

  92.  *     cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
    93. 

  93.  *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
    94. 

  94.  *     cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
    95. 

  95.  *     cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
    96. 

  96.  *     cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
    97. 

  97.  *     cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
    98. 

  98.  *     cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
    99. 

  99.  *     cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
    100. 

  100.  *     cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
    101. 

  101.  *     cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
    102. 

  102.  *     cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
    103. 

  103.  *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7"];
    104. 

  104.  *     cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
    105. 

  105.  *     cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
    106. 

  106.  *     cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
    107. 

  107.  *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
    108. 

  108.  *     cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
    109. 

  109.  *     cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
    110. 

  110.  *     cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
    111. 

  111.  *     cvmx_dfm_fnt_stat [label="DFM_FNT_STAT|<sbe_err>sbe_err|<dbe_err>dbe_err"];
    112. 

  112.  *     cvmx_ciu_block_int:dfm:e -> cvmx_dfm_fnt_stat [label="dfm"];
    113. 

  113.  *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
    114. 

  114.  *     cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
    115. 

  115.  *     cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
    116. 

  116.  *     cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
    117. 

  117.  *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
    118. 

  118.  *     cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
    119. 

  119.  *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
    120. 

  120.  *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
    121. 

  121.  *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
    122. 

  122.  *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
    123. 

  123.  *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
    124. 

  124.  *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
    125. 

  125.  *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
    126. 

  126.  *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
    127. 

  127.  *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
    128. 

  128.  *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
    129. 

  129.  *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
    130. 

  130.  *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
    131. 

  131.  *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
    132. 

  132.  *     cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
    133. 

  133.  *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
    134. 

  134.  *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
    135. 

  135.  *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
    136. 

  136.  *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
    137. 

  137.  *     cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
    138. 

  138.  *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
    139. 

  139.  *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
    140. 

  140.  *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
    141. 

  141.  *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
    142. 

  142.  *     cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
    143. 

  143.  *     cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
    144. 

  144.  *     cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
    145. 

  145.  *     cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout"];
    146. 

  146.  *     cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
    147. 

  147.  *     cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout"];
    148. 

  148.  *     cvmx_ciu_block_int:srio1:e -> cvmx_srio1_int_reg [label="srio1"];
    149. 

  149.  *     cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad"];
    150. 

  150.  *     cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
    151. 

  151.  *     cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"];
    152. 

  152.  *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
    153. 

  153.  *     cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
    154. 

  154.  *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
    155. 

  155.  *     cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
    156. 

  156.  *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
    157. 

  157.  *     cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
    158. 

  158.  *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
    159. 

  159.  *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
    160. 

  160.  *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
    161. 

  161.  *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
    162. 

  162.  *     cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
    163. 

  163.  *     cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
    164. 

  164.  *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
    165. 

  165.  *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
    166. 

  166.  *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
    167. 

  167.  *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
    168. 

  168.  *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
    169. 

  169.  *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
    170. 

  170.  *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
    171. 

  171.  *     cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
    172. 

  172.  *     cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
    173. 

  173.  *     cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
    174. 

  174.  *     cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
    175. 

  175.  *     cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
    176. 

  176.  * }
    177. 

  177.  * @enddot
    178. 

  178.  */
    179. 

  179. #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
    180. 

  180. #include <asm/octeon/cvmx.h>
    181. 

  181. #include <asm/octeon/cvmx-error.h>
    182. 

  182. #include <asm/octeon/cvmx-error-custom.h>
    183. 

  183. #include <asm/octeon/cvmx-csr-typedefs.h>
    184. 

  184. #else
    185. 

  185. #include "cvmx.h"
    186. 

  186. #include "cvmx-error.h"
    187. 

  187. #include "cvmx-error-custom.h"
    188. 

  188. #endif
    189. 

  189. 

  190. int cvmx_error_initialize_cn63xx(void);
    191. 

  191. 

  192. int cvmx_error_initialize_cn63xx(void)
    193. 

  193. {
    194. 

  194.     cvmx_error_info_t info;
    195. 

  195.     int fail = 0;
    196. 

  196. 

  197.     /* CVMX_CIU_INTX_SUM0(0) */
    198. 

  198.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    199. 

  199.     info.status_addr        = CVMX_CIU_INTX_SUM0(0);
    200. 

  200.     info.status_mask        = 0;
    201. 

  201.     info.enable_addr        = 0;
    202. 

  202.     info.enable_mask        = 0;
    203. 

  203.     info.flags              = 0;
    204. 

  204.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    205. 

  205.     info.group_index        = 0;
    206. 

  206.     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
    207. 

  207.     info.parent.status_addr = 0;
    208. 

  208.     info.parent.status_mask = 0;
    209. 

  209.     info.func               = __cvmx_error_decode;
    210. 

  210.     info.user_info          = 0;
    211. 

  211.     fail |= cvmx_error_add(&info);
    212. 

  212. 

  213.     /* CVMX_MIXX_ISR(0) */
    214. 

  214.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    215. 

  215.     info.status_addr        = CVMX_MIXX_ISR(0);
    216. 

  216.     info.status_mask        = 1ull<<0 /* odblovf */;
    217. 

  217.     info.enable_addr        = CVMX_MIXX_INTENA(0);
    218. 

  218.     info.enable_mask        = 1ull<<0 /* ovfena */;
    219. 

  219.     info.flags              = 0;
    220. 

  220.     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
    221. 

  221.     info.group_index        = 0;
    222. 

  222.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    223. 

  223.     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
    224. 

  224.     info.parent.status_mask = 1ull<<62 /* mii */;
    225. 

  225.     info.func               = __cvmx_error_display;
    226. 

  226.     info.user_info          = (long)
    227. 

  227.         "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
    228. 

  228.         "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
    229. 

  229.         "    with a value greater than the remaining #of\n"
    230. 

  230.         "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
    231. 

  231.         "    the following occurs:\n"
    232. 

  232.         "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
    233. 

  233.         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
    234. 

  234.         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
    235. 

  235.         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
    236. 

  236.         "    and the local interrupt mask bit(OVFENA) is set, than an\n"
    237. 

  237.         "    interrupt is reported for this event.\n"
    238. 

  238.         "    SW should keep track of the #I-Ring Entries in use\n"
    239. 

  239.         "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
    240. 

  240.         "    future ODBELL writes don't exceed the size of the\n"
    241. 

  241.         "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
    242. 

  242.         "    SW must reclaim O-Ring Entries by writing to the\n"
    243. 

  243.         "    MIX_ORCNT[ORCNT]. .\n"
    244. 

  244.         "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
    245. 

  245.         "    If it occurs, it's an indication that SW has\n"
    246. 

  246.         "    overwritten the O-Ring buffer, and the only recourse\n"
    247. 

  247.         "    is a HW reset.\n";
    248. 

  248.     fail |= cvmx_error_add(&info);
    249. 

  249. 

  250.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    251. 

  251.     info.status_addr        = CVMX_MIXX_ISR(0);
    252. 

  252.     info.status_mask        = 1ull<<1 /* idblovf */;
    253. 

  253.     info.enable_addr        = CVMX_MIXX_INTENA(0);
    254. 

  254.     info.enable_mask        = 1ull<<1 /* ivfena */;
    255. 

  255.     info.flags              = 0;
    256. 

  256.     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
    257. 

  257.     info.group_index        = 0;
    258. 

  258.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    259. 

  259.     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
    260. 

  260.     info.parent.status_mask = 1ull<<62 /* mii */;
    261. 

  261.     info.func               = __cvmx_error_display;
    262. 

  262.     info.user_info          = (long)
    263. 

  263.         "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
    264. 

  264.         "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
    265. 

  265.         "    with a value greater than the remaining #of\n"
    266. 

  266.         "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
    267. 

  267.         "    the following occurs:\n"
    268. 

  268.         "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
    269. 

  269.         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
    270. 

  270.         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
    271. 

  271.         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
    272. 

  272.         "    and the local interrupt mask bit(IVFENA) is set, than an\n"
    273. 

  273.         "    interrupt is reported for this event.\n"
    274. 

  274.         "    SW should keep track of the #I-Ring Entries in use\n"
    275. 

  275.         "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
    276. 

  276.         "    future IDBELL writes don't exceed the size of the\n"
    277. 

  277.         "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
    278. 

  278.         "    SW must reclaim I-Ring Entries by keeping track of the\n"
    279. 

  279.         "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
    280. 

  280.         "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
    281. 

  281.         "    total #packets(not IRing Entries) and SW must further\n"
    282. 

  282.         "    keep track of the # of I-Ring Entries associated with\n"
    283. 

  283.         "    each packet as they are processed.\n"
    284. 

  284.         "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
    285. 

  285.         "    If it occurs, it's an indication that SW has\n"
    286. 

  286.         "    overwritten the I-Ring buffer, and the only recourse\n"
    287. 

  287.         "    is a HW reset.\n";
    288. 

  288.     fail |= cvmx_error_add(&info);
    289. 

  289. 

  290.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    291. 

  291.     info.status_addr        = CVMX_MIXX_ISR(0);
    292. 

  292.     info.status_mask        = 1ull<<4 /* data_drp */;
    293. 

  293.     info.enable_addr        = CVMX_MIXX_INTENA(0);
    294. 

  294.     info.enable_mask        = 1ull<<4 /* data_drpena */;
    295. 

  295.     info.flags              = 0;
    296. 

  296.     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
    297. 

  297.     info.group_index        = 0;
    298. 

  298.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    299. 

  299.     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
    300. 

  300.     info.parent.status_mask = 1ull<<62 /* mii */;
    301. 

  301.     info.func               = __cvmx_error_display;
    302. 

  302.     info.user_info          = (long)
    303. 

  303.         "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
    304. 

  304.         "    If this does occur, the DATA_DRP is set and the\n"
    305. 

  305.         "    CIU_INTx_SUM0,4[MII] bits are set.\n"
    306. 

  306.         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
    307. 

  307.         "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
    308. 

  308.         "    interrupt is reported for this event.\n";
    309. 

  309.     fail |= cvmx_error_add(&info);
    310. 

  310. 

  311.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    312. 

  312.     info.status_addr        = CVMX_MIXX_ISR(0);
    313. 

  313.     info.status_mask        = 1ull<<5 /* irun */;
    314. 

  314.     info.enable_addr        = CVMX_MIXX_INTENA(0);
    315. 

  315.     info.enable_mask        = 1ull<<5 /* irunena */;
    316. 

  316.     info.flags              = 0;
    317. 

  317.     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
    318. 

  318.     info.group_index        = 0;
    319. 

  319.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    320. 

  320.     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
    321. 

  321.     info.parent.status_mask = 1ull<<62 /* mii */;
    322. 

  322.     info.func               = __cvmx_error_display;
    323. 

  323.     info.user_info          = (long)
    324. 

  324.         "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
    325. 

  325.         "    If SW writes a larger value than what is currently\n"
    326. 

  326.         "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
    327. 

  327.         "    underflow condition.\n"
    328. 

  328.         "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
    329. 

  329.         "    NOTE: If an IRUN underflow condition is detected,\n"
    330. 

  330.         "    the integrity of the MIX/AGL HW state has\n"
    331. 

  331.         "    been compromised. To recover, SW must issue a\n"
    332. 

  332.         "    software reset sequence (see: MIX_CTL[RESET]\n";
    333. 

  333.     fail |= cvmx_error_add(&info);
    334. 

  334. 

  335.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    336. 

  336.     info.status_addr        = CVMX_MIXX_ISR(0);
    337. 

  337.     info.status_mask        = 1ull<<6 /* orun */;
    338. 

  338.     info.enable_addr        = CVMX_MIXX_INTENA(0);
    339. 

  339.     info.enable_mask        = 1ull<<6 /* orunena */;
    340. 

  340.     info.flags              = 0;
    341. 

  341.     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
    342. 

  342.     info.group_index        = 0;
    343. 

  343.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    344. 

  344.     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
    345. 

  345.     info.parent.status_mask = 1ull<<62 /* mii */;
    346. 

  346.     info.func               = __cvmx_error_display;
    347. 

  347.     info.user_info          = (long)
    348. 

  348.         "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
    349. 

  349.         "    If SW writes a larger value than what is currently\n"
    350. 

  350.         "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
    351. 

  351.         "    underflow condition.\n"
    352. 

  352.         "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
    353. 

  353.         "    NOTE: If an ORUN underflow condition is detected,\n"
    354. 

  354.         "    the integrity of the MIX/AGL HW state has\n"
    355. 

  355.         "    been compromised. To recover, SW must issue a\n"
    356. 

  356.         "    software reset sequence (see: MIX_CTL[RESET]\n";
    357. 

  357.     fail |= cvmx_error_add(&info);
    358. 

  358. 

  359.     /* CVMX_CIU_INT_SUM1 */
    360. 

  360.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    361. 

  361.     info.status_addr        = CVMX_CIU_INT_SUM1;
    362. 

  362.     info.status_mask        = 0;
    363. 

  363.     info.enable_addr        = 0;
    364. 

  364.     info.enable_mask        = 0;
    365. 

  365.     info.flags              = 0;
    366. 

  366.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    367. 

  367.     info.group_index        = 0;
    368. 

  368.     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
    369. 

  369.     info.parent.status_addr = 0;
    370. 

  370.     info.parent.status_mask = 0;
    371. 

  371.     info.func               = __cvmx_error_decode;
    372. 

  372.     info.user_info          = 0;
    373. 

  373.     fail |= cvmx_error_add(&info);
    374. 

  374. 

  375.     /* CVMX_MIXX_ISR(1) */
    376. 

  376.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    377. 

  377.     info.status_addr        = CVMX_MIXX_ISR(1);
    378. 

  378.     info.status_mask        = 1ull<<0 /* odblovf */;
    379. 

  379.     info.enable_addr        = CVMX_MIXX_INTENA(1);
    380. 

  380.     info.enable_mask        = 1ull<<0 /* ovfena */;
    381. 

  381.     info.flags              = 0;
    382. 

  382.     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
    383. 

  383.     info.group_index        = 1;
    384. 

  384.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    385. 

  385.     info.parent.status_addr = CVMX_CIU_INT_SUM1;
    386. 

  386.     info.parent.status_mask = 1ull<<18 /* mii1 */;
    387. 

  387.     info.func               = __cvmx_error_display;
    388. 

  388.     info.user_info          = (long)
    389. 

  389.         "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
    390. 

  390.         "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
    391. 

  391.         "    with a value greater than the remaining #of\n"
    392. 

  392.         "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
    393. 

  393.         "    the following occurs:\n"
    394. 

  394.         "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
    395. 

  395.         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
    396. 

  396.         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
    397. 

  397.         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
    398. 

  398.         "    and the local interrupt mask bit(OVFENA) is set, than an\n"
    399. 

  399.         "    interrupt is reported for this event.\n"
    400. 

  400.         "    SW should keep track of the #I-Ring Entries in use\n"
    401. 

  401.         "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
    402. 

  402.         "    future ODBELL writes don't exceed the size of the\n"
    403. 

  403.         "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
    404. 

  404.         "    SW must reclaim O-Ring Entries by writing to the\n"
    405. 

  405.         "    MIX_ORCNT[ORCNT]. .\n"
    406. 

  406.         "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
    407. 

  407.         "    If it occurs, it's an indication that SW has\n"
    408. 

  408.         "    overwritten the O-Ring buffer, and the only recourse\n"
    409. 

  409.         "    is a HW reset.\n";
    410. 

  410.     fail |= cvmx_error_add(&info);
    411. 

  411. 

  412.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    413. 

  413.     info.status_addr        = CVMX_MIXX_ISR(1);
    414. 

  414.     info.status_mask        = 1ull<<1 /* idblovf */;
    415. 

  415.     info.enable_addr        = CVMX_MIXX_INTENA(1);
    416. 

  416.     info.enable_mask        = 1ull<<1 /* ivfena */;
    417. 

  417.     info.flags              = 0;
    418. 

  418.     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
    419. 

  419.     info.group_index        = 1;
    420. 

  420.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    421. 

  421.     info.parent.status_addr = CVMX_CIU_INT_SUM1;
    422. 

  422.     info.parent.status_mask = 1ull<<18 /* mii1 */;
    423. 

  423.     info.func               = __cvmx_error_display;
    424. 

  424.     info.user_info          = (long)
    425. 

  425.         "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
    426. 

  426.         "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
    427. 

  427.         "    with a value greater than the remaining #of\n"
    428. 

  428.         "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
    429. 

  429.         "    the following occurs:\n"
    430. 

  430.         "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
    431. 

  431.         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
    432. 

  432.         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
    433. 

  433.         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
    434. 

  434.         "    and the local interrupt mask bit(IVFENA) is set, than an\n"
    435. 

  435.         "    interrupt is reported for this event.\n"
    436. 

  436.         "    SW should keep track of the #I-Ring Entries in use\n"
    437. 

  437.         "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
    438. 

  438.         "    future IDBELL writes don't exceed the size of the\n"
    439. 

  439.         "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
    440. 

  440.         "    SW must reclaim I-Ring Entries by keeping track of the\n"
    441. 

  441.         "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
    442. 

  442.         "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
    443. 

  443.         "    total #packets(not IRing Entries) and SW must further\n"
    444. 

  444.         "    keep track of the # of I-Ring Entries associated with\n"
    445. 

  445.         "    each packet as they are processed.\n"
    446. 

  446.         "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
    447. 

  447.         "    If it occurs, it's an indication that SW has\n"
    448. 

  448.         "    overwritten the I-Ring buffer, and the only recourse\n"
    449. 

  449.         "    is a HW reset.\n";
    450. 

  450.     fail |= cvmx_error_add(&info);
    451. 

  451. 

  452.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    453. 

  453.     info.status_addr        = CVMX_MIXX_ISR(1);
    454. 

  454.     info.status_mask        = 1ull<<4 /* data_drp */;
    455. 

  455.     info.enable_addr        = CVMX_MIXX_INTENA(1);
    456. 

  456.     info.enable_mask        = 1ull<<4 /* data_drpena */;
    457. 

  457.     info.flags              = 0;
    458. 

  458.     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
    459. 

  459.     info.group_index        = 1;
    460. 

  460.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    461. 

  461.     info.parent.status_addr = CVMX_CIU_INT_SUM1;
    462. 

  462.     info.parent.status_mask = 1ull<<18 /* mii1 */;
    463. 

  463.     info.func               = __cvmx_error_display;
    464. 

  464.     info.user_info          = (long)
    465. 

  465.         "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
    466. 

  466.         "    If this does occur, the DATA_DRP is set and the\n"
    467. 

  467.         "    CIU_INTx_SUM0,4[MII] bits are set.\n"
    468. 

  468.         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
    469. 

  469.         "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
    470. 

  470.         "    interrupt is reported for this event.\n";
    471. 

  471.     fail |= cvmx_error_add(&info);
    472. 

  472. 

  473.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    474. 

  474.     info.status_addr        = CVMX_MIXX_ISR(1);
    475. 

  475.     info.status_mask        = 1ull<<5 /* irun */;
    476. 

  476.     info.enable_addr        = CVMX_MIXX_INTENA(1);
    477. 

  477.     info.enable_mask        = 1ull<<5 /* irunena */;
    478. 

  478.     info.flags              = 0;
    479. 

  479.     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
    480. 

  480.     info.group_index        = 1;
    481. 

  481.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    482. 

  482.     info.parent.status_addr = CVMX_CIU_INT_SUM1;
    483. 

  483.     info.parent.status_mask = 1ull<<18 /* mii1 */;
    484. 

  484.     info.func               = __cvmx_error_display;
    485. 

  485.     info.user_info          = (long)
    486. 

  486.         "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
    487. 

  487.         "    If SW writes a larger value than what is currently\n"
    488. 

  488.         "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
    489. 

  489.         "    underflow condition.\n"
    490. 

  490.         "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
    491. 

  491.         "    NOTE: If an IRUN underflow condition is detected,\n"
    492. 

  492.         "    the integrity of the MIX/AGL HW state has\n"
    493. 

  493.         "    been compromised. To recover, SW must issue a\n"
    494. 

  494.         "    software reset sequence (see: MIX_CTL[RESET]\n";
    495. 

  495.     fail |= cvmx_error_add(&info);
    496. 

  496. 

  497.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    498. 

  498.     info.status_addr        = CVMX_MIXX_ISR(1);
    499. 

  499.     info.status_mask        = 1ull<<6 /* orun */;
    500. 

  500.     info.enable_addr        = CVMX_MIXX_INTENA(1);
    501. 

  501.     info.enable_mask        = 1ull<<6 /* orunena */;
    502. 

  502.     info.flags              = 0;
    503. 

  503.     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
    504. 

  504.     info.group_index        = 1;
    505. 

  505.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    506. 

  506.     info.parent.status_addr = CVMX_CIU_INT_SUM1;
    507. 

  507.     info.parent.status_mask = 1ull<<18 /* mii1 */;
    508. 

  508.     info.func               = __cvmx_error_display;
    509. 

  509.     info.user_info          = (long)
    510. 

  510.         "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
    511. 

  511.         "    If SW writes a larger value than what is currently\n"
    512. 

  512.         "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
    513. 

  513.         "    underflow condition.\n"
    514. 

  514.         "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
    515. 

  515.         "    NOTE: If an ORUN underflow condition is detected,\n"
    516. 

  516.         "    the integrity of the MIX/AGL HW state has\n"
    517. 

  517.         "    been compromised. To recover, SW must issue a\n"
    518. 

  518.         "    software reset sequence (see: MIX_CTL[RESET]\n";
    519. 

  519.     fail |= cvmx_error_add(&info);
    520. 

  520. 

  521.     /* CVMX_NDF_INT */
    522. 

  522.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    523. 

  523.     info.status_addr        = CVMX_NDF_INT;
    524. 

  524.     info.status_mask        = 1ull<<2 /* wdog */;
    525. 

  525.     info.enable_addr        = CVMX_NDF_INT_EN;
    526. 

  526.     info.enable_mask        = 1ull<<2 /* wdog */;
    527. 

  527.     info.flags              = 0;
    528. 

  528.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    529. 

  529.     info.group_index        = 0;
    530. 

  530.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    531. 

  531.     info.parent.status_addr = CVMX_CIU_INT_SUM1;
    532. 

  532.     info.parent.status_mask = 1ull<<19 /* nand */;
    533. 

  533.     info.func               = __cvmx_error_display;
    534. 

  534.     info.user_info          = (long)
    535. 

  535.         "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
    536. 

  536.     fail |= cvmx_error_add(&info);
    537. 

  537. 

  538.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    539. 

  539.     info.status_addr        = CVMX_NDF_INT;
    540. 

  540.     info.status_mask        = 1ull<<3 /* sm_bad */;
    541. 

  541.     info.enable_addr        = CVMX_NDF_INT_EN;
    542. 

  542.     info.enable_mask        = 1ull<<3 /* sm_bad */;
    543. 

  543.     info.flags              = 0;
    544. 

  544.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    545. 

  545.     info.group_index        = 0;
    546. 

  546.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    547. 

  547.     info.parent.status_addr = CVMX_CIU_INT_SUM1;
    548. 

  548.     info.parent.status_mask = 1ull<<19 /* nand */;
    549. 

  549.     info.func               = __cvmx_error_display;
    550. 

  550.     info.user_info          = (long)
    551. 

  551.         "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
    552. 

  552.     fail |= cvmx_error_add(&info);
    553. 

  553. 

  554.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    555. 

  555.     info.status_addr        = CVMX_NDF_INT;
    556. 

  556.     info.status_mask        = 1ull<<4 /* ecc_1bit */;
    557. 

  557.     info.enable_addr        = CVMX_NDF_INT_EN;
    558. 

  558.     info.enable_mask        = 1ull<<4 /* ecc_1bit */;
    559. 

  559.     info.flags              = 0;
    560. 

  560.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    561. 

  561.     info.group_index        = 0;
    562. 

  562.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    563. 

  563.     info.parent.status_addr = CVMX_CIU_INT_SUM1;
    564. 

  564.     info.parent.status_mask = 1ull<<19 /* nand */;
    565. 

  565.     info.func               = __cvmx_error_display;
    566. 

  566.     info.user_info          = (long)
    567. 

  567.         "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
    568. 

  568.     fail |= cvmx_error_add(&info);
    569. 

  569. 

  570.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    571. 

  571.     info.status_addr        = CVMX_NDF_INT;
    572. 

  572.     info.status_mask        = 1ull<<5 /* ecc_mult */;
    573. 

  573.     info.enable_addr        = CVMX_NDF_INT_EN;
    574. 

  574.     info.enable_mask        = 1ull<<5 /* ecc_mult */;
    575. 

  575.     info.flags              = 0;
    576. 

  576.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    577. 

  577.     info.group_index        = 0;
    578. 

  578.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    579. 

  579.     info.parent.status_addr = CVMX_CIU_INT_SUM1;
    580. 

  580.     info.parent.status_mask = 1ull<<19 /* nand */;
    581. 

  581.     info.func               = __cvmx_error_display;
    582. 

  582.     info.user_info          = (long)
    583. 

  583.         "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
    584. 

  584.     fail |= cvmx_error_add(&info);
    585. 

  585. 

  586.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    587. 

  587.     info.status_addr        = CVMX_NDF_INT;
    588. 

  588.     info.status_mask        = 1ull<<6 /* ovrf */;
    589. 

  589.     info.enable_addr        = CVMX_NDF_INT_EN;
    590. 

  590.     info.enable_mask        = 1ull<<6 /* ovrf */;
    591. 

  591.     info.flags              = 0;
    592. 

  592.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    593. 

  593.     info.group_index        = 0;
    594. 

  594.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    595. 

  595.     info.parent.status_addr = CVMX_CIU_INT_SUM1;
    596. 

  596.     info.parent.status_mask = 1ull<<19 /* nand */;
    597. 

  597.     info.func               = __cvmx_error_display;
    598. 

  598.     info.user_info          = (long)
    599. 

  599.         "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
    600. 

  600.         "    fatal error.\n";
    601. 

  601.     fail |= cvmx_error_add(&info);
    602. 

  602. 

  603.     /* CVMX_CIU_BLOCK_INT */
    604. 

  604.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    605. 

  605.     info.status_addr        = CVMX_CIU_BLOCK_INT;
    606. 

  606.     info.status_mask        = 0;
    607. 

  607.     info.enable_addr        = 0;
    608. 

  608.     info.enable_mask        = 0;
    609. 

  609.     info.flags              = 0;
    610. 

  610.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    611. 

  611.     info.group_index        = 0;
    612. 

  612.     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
    613. 

  613.     info.parent.status_addr = 0;
    614. 

  614.     info.parent.status_mask = 0;
    615. 

  615.     info.func               = __cvmx_error_decode;
    616. 

  616.     info.user_info          = 0;
    617. 

  617.     fail |= cvmx_error_add(&info);
    618. 

  618. 

  619.     /* CVMX_L2C_INT_REG */
    620. 

  620.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    621. 

  621.     info.status_addr        = CVMX_L2C_INT_REG;
    622. 

  622.     info.status_mask        = 1ull<<0 /* holerd */;
    623. 

  623.     info.enable_addr        = CVMX_L2C_INT_ENA;
    624. 

  624.     info.enable_mask        = 1ull<<0 /* holerd */;
    625. 

  625.     info.flags              = 0;
    626. 

  626.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    627. 

  627.     info.group_index        = 0;
    628. 

  628.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    629. 

  629.     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
    630. 

  630.     info.parent.status_mask = 1ull<<16 /* l2c */;
    631. 

  631.     info.func               = __cvmx_error_display;
    632. 

  632.     info.user_info          = (long)
    633. 

  633.         "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
    634. 

  634.     fail |= cvmx_error_add(&info);
    635. 

  635. 

  636.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    637. 

  637.     info.status_addr        = CVMX_L2C_INT_REG;
    638. 

  638.     info.status_mask        = 1ull<<1 /* holewr */;
    639. 

  639.     info.enable_addr        = CVMX_L2C_INT_ENA;
    640. 

  640.     info.enable_mask        = 1ull<<1 /* holewr */;
    641. 

  641.     info.flags              = 0;
    642. 

  642.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    643. 

  643.     info.group_index        = 0;
    644. 

  644.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    645. 

  645.     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
    646. 

  646.     info.parent.status_mask = 1ull<<16 /* l2c */;
    647. 

  647.     info.func               = __cvmx_error_display;
    648. 

  648.     info.user_info          = (long)
    649. 

  649.         "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
    650. 

  650.     fail |= cvmx_error_add(&info);
    651. 

  651. 

  652.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    653. 

  653.     info.status_addr        = CVMX_L2C_INT_REG;
    654. 

  654.     info.status_mask        = 1ull<<2 /* vrtwr */;
    655. 

  655.     info.enable_addr        = CVMX_L2C_INT_ENA;
    656. 

  656.     info.enable_mask        = 1ull<<2 /* vrtwr */;
    657. 

  657.     info.flags              = 0;
    658. 

  658.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    659. 

  659.     info.group_index        = 0;
    660. 

  660.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    661. 

  661.     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
    662. 

  662.     info.parent.status_mask = 1ull<<16 /* l2c */;
    663. 

  663.     info.func               = __cvmx_error_display;
    664. 

  664.     info.user_info          = (long)
    665. 

  665.         "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
    666. 

  666.         "    Set when L2C_VRT_MEM blocked a store.\n";
    667. 

  667.     fail |= cvmx_error_add(&info);
    668. 

  668. 

  669.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    670. 

  670.     info.status_addr        = CVMX_L2C_INT_REG;
    671. 

  671.     info.status_mask        = 1ull<<3 /* vrtidrng */;
    672. 

  672.     info.enable_addr        = CVMX_L2C_INT_ENA;
    673. 

  673.     info.enable_mask        = 1ull<<3 /* vrtidrng */;
    674. 

  674.     info.flags              = 0;
    675. 

  675.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    676. 

  676.     info.group_index        = 0;
    677. 

  677.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    678. 

  678.     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
    679. 

  679.     info.parent.status_mask = 1ull<<16 /* l2c */;
    680. 

  680.     info.func               = __cvmx_error_display;
    681. 

  681.     info.user_info          = (long)
    682. 

  682.         "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
    683. 

  683.         "    Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
    684. 

  684.         "    store.\n";
    685. 

  685.     fail |= cvmx_error_add(&info);
    686. 

  686. 

  687.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    688. 

  688.     info.status_addr        = CVMX_L2C_INT_REG;
    689. 

  689.     info.status_mask        = 1ull<<4 /* vrtadrng */;
    690. 

  690.     info.enable_addr        = CVMX_L2C_INT_ENA;
    691. 

  691.     info.enable_mask        = 1ull<<4 /* vrtadrng */;
    692. 

  692.     info.flags              = 0;
    693. 

  693.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    694. 

  694.     info.group_index        = 0;
    695. 

  695.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    696. 

  696.     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
    697. 

  697.     info.parent.status_mask = 1ull<<16 /* l2c */;
    698. 

  698.     info.func               = __cvmx_error_display;
    699. 

  699.     info.user_info          = (long)
    700. 

  700.         "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
    701. 

  701.         "    Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
    702. 

  702.         "    store.\n"
    703. 

  703.         "    L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
    704. 

  704.     fail |= cvmx_error_add(&info);
    705. 

  705. 

  706.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    707. 

  707.     info.status_addr        = CVMX_L2C_INT_REG;
    708. 

  708.     info.status_mask        = 1ull<<5 /* vrtpe */;
    709. 

  709.     info.enable_addr        = CVMX_L2C_INT_ENA;
    710. 

  710.     info.enable_mask        = 1ull<<5 /* vrtpe */;
    711. 

  711.     info.flags              = 0;
    712. 

  712.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    713. 

  713.     info.group_index        = 0;
    714. 

  714.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    715. 

  715.     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
    716. 

  716.     info.parent.status_mask = 1ull<<16 /* l2c */;
    717. 

  717.     info.func               = __cvmx_error_display;
    718. 

  718.     info.user_info          = (long)
    719. 

  719.         "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
    720. 

  720.         "    Whenever an L2C_VRT_MEM read finds a parity error,\n"
    721. 

  721.         "    that L2C_VRT_MEM cannot cause stores to be blocked.\n"
    722. 

  722.         "    Software should correct the error.\n";
    723. 

  723.     fail |= cvmx_error_add(&info);
    724. 

  724. 

  725.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    726. 

  726.     info.status_addr        = CVMX_L2C_INT_REG;
    727. 

  727.     info.status_mask        = 1ull<<6 /* bigwr */;
    728. 

  728.     info.enable_addr        = CVMX_L2C_INT_ENA;
    729. 

  729.     info.enable_mask        = 1ull<<6 /* bigwr */;
    730. 

  730.     info.flags              = 0;
    731. 

  731.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    732. 

  732.     info.group_index        = 0;
    733. 

  733.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    734. 

  734.     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
    735. 

  735.     info.parent.status_mask = 1ull<<16 /* l2c */;
    736. 

  736.     info.func               = __cvmx_error_display;
    737. 

  737.     info.user_info          = (long)
    738. 

  738.         "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
    739. 

  739.     fail |= cvmx_error_add(&info);
    740. 

  740. 

  741.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    742. 

  742.     info.status_addr        = CVMX_L2C_INT_REG;
    743. 

  743.     info.status_mask        = 1ull<<7 /* bigrd */;
    744. 

  744.     info.enable_addr        = CVMX_L2C_INT_ENA;
    745. 

  745.     info.enable_mask        = 1ull<<7 /* bigrd */;
    746. 

  746.     info.flags              = 0;
    747. 

  747.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    748. 

  748.     info.group_index        = 0;
    749. 

  749.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    750. 

  750.     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
    751. 

  751.     info.parent.status_mask = 1ull<<16 /* l2c */;
    752. 

  752.     info.func               = __cvmx_error_display;
    753. 

  753.     info.user_info          = (long)
    754. 

  754.         "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
    755. 

  755.     fail |= cvmx_error_add(&info);
    756. 

  756. 

  757.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    758. 

  758.     info.status_addr        = CVMX_L2C_INT_REG;
    759. 

  759.     info.status_mask        = 0;
    760. 

  760.     info.enable_addr        = 0;
    761. 

  761.     info.enable_mask        = 0;
    762. 

  762.     info.flags              = 0;
    763. 

  763.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    764. 

  764.     info.group_index        = 0;
    765. 

  765.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    766. 

  766.     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
    767. 

  767.     info.parent.status_mask = 1ull<<16 /* l2c */;
    768. 

  768.     info.func               = __cvmx_error_decode;
    769. 

  769.     info.user_info          = 0;
    770. 

  770.     fail |= cvmx_error_add(&info);
    771. 

  771. 

  772.     /* CVMX_L2C_ERR_TDTX(0) */
    773. 

  773.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    774. 

  774.     info.status_addr        = CVMX_L2C_ERR_TDTX(0);
    775. 

  775.     info.status_mask        = 1ull<<60 /* vsbe */;
    776. 

  776.     info.enable_addr        = 0;
    777. 

  777.     info.enable_mask        = 0;
    778. 

  778.     info.flags              = 0;
    779. 

  779.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    780. 

  780.     info.group_index        = 0;
    781. 

  781.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    782. 

  782.     info.parent.status_addr = CVMX_L2C_INT_REG;
    783. 

  783.     info.parent.status_mask = 1ull<<16 /* tad0 */;
    784. 

  784.     info.func               = __cvmx_error_display;
    785. 

  785.     info.user_info          = (long)
    786. 

  786.         "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
    787. 

  787.     fail |= cvmx_error_add(&info);
    788. 

  788. 

  789.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    790. 

  790.     info.status_addr        = CVMX_L2C_ERR_TDTX(0);
    791. 

  791.     info.status_mask        = 1ull<<61 /* vdbe */;
    792. 

  792.     info.enable_addr        = 0;
    793. 

  793.     info.enable_mask        = 0;
    794. 

  794.     info.flags              = 0;
    795. 

  795.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    796. 

  796.     info.group_index        = 0;
    797. 

  797.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    798. 

  798.     info.parent.status_addr = CVMX_L2C_INT_REG;
    799. 

  799.     info.parent.status_mask = 1ull<<16 /* tad0 */;
    800. 

  800.     info.func               = __cvmx_error_display;
    801. 

  801.     info.user_info          = (long)
    802. 

  802.         "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
    803. 

  803.     fail |= cvmx_error_add(&info);
    804. 

  804. 

  805.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    806. 

  806.     info.status_addr        = CVMX_L2C_ERR_TDTX(0);
    807. 

  807.     info.status_mask        = 1ull<<62 /* sbe */;
    808. 

  808.     info.enable_addr        = 0;
    809. 

  809.     info.enable_mask        = 0;
    810. 

  810.     info.flags              = 0;
    811. 

  811.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    812. 

  812.     info.group_index        = 0;
    813. 

  813.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    814. 

  814.     info.parent.status_addr = CVMX_L2C_INT_REG;
    815. 

  815.     info.parent.status_mask = 1ull<<16 /* tad0 */;
    816. 

  816.     info.func               = __cvmx_error_display;
    817. 

  817.     info.user_info          = (long)
    818. 

  818.         "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
    819. 

  819.     fail |= cvmx_error_add(&info);
    820. 

  820. 

  821.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    822. 

  822.     info.status_addr        = CVMX_L2C_ERR_TDTX(0);
    823. 

  823.     info.status_mask        = 1ull<<63 /* dbe */;
    824. 

  824.     info.enable_addr        = 0;
    825. 

  825.     info.enable_mask        = 0;
    826. 

  826.     info.flags              = 0;
    827. 

  827.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    828. 

  828.     info.group_index        = 0;
    829. 

  829.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    830. 

  830.     info.parent.status_addr = CVMX_L2C_INT_REG;
    831. 

  831.     info.parent.status_mask = 1ull<<16 /* tad0 */;
    832. 

  832.     info.func               = __cvmx_error_display;
    833. 

  833.     info.user_info          = (long)
    834. 

  834.         "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
    835. 

  835.     fail |= cvmx_error_add(&info);
    836. 

  836. 

  837.     /* CVMX_L2C_ERR_TTGX(0) */
    838. 

  838.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    839. 

  839.     info.status_addr        = CVMX_L2C_ERR_TTGX(0);
    840. 

  840.     info.status_mask        = 1ull<<61 /* noway */;
    841. 

  841.     info.enable_addr        = 0;
    842. 

  842.     info.enable_mask        = 0;
    843. 

  843.     info.flags              = 0;
    844. 

  844.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    845. 

  845.     info.group_index        = 0;
    846. 

  846.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    847. 

  847.     info.parent.status_addr = CVMX_L2C_INT_REG;
    848. 

  848.     info.parent.status_mask = 1ull<<16 /* tad0 */;
    849. 

  849.     info.func               = __cvmx_error_display;
    850. 

  850.     info.user_info          = (long)
    851. 

  851.         "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
    852. 

  852.         "    L2C sets NOWAY during its processing of a\n"
    853. 

  853.         "    transaction whenever it needed/wanted to allocate\n"
    854. 

  854.         "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
    855. 

  855.         "    is (generally) not an indication that L2C failed to\n"
    856. 

  856.         "    complete transactions. Rather, it is a hint of\n"
    857. 

  857.         "    possible performance degradation. (For example, L2C\n"
    858. 

  858.         "    must read-modify-write DRAM for every transaction\n"
    859. 

  859.         "    that updates some, but not all, of the bytes in a\n"
    860. 

  860.         "    cache block, misses in the L2 cache, and cannot\n"
    861. 

  861.         "    allocate a WAY.) There is one \"failure\" case where\n"
    862. 

  862.         "    L2C will set NOWAY: when it cannot leave a block\n"
    863. 

  863.         "    locked in the L2 cache as part of a LCKL2\n"
    864. 

  864.         "    transaction.\n";
    865. 

  865.     fail |= cvmx_error_add(&info);
    866. 

  866. 

  867.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    868. 

  868.     info.status_addr        = CVMX_L2C_ERR_TTGX(0);
    869. 

  869.     info.status_mask        = 1ull<<62 /* sbe */;
    870. 

  870.     info.enable_addr        = 0;
    871. 

  871.     info.enable_mask        = 0;
    872. 

  872.     info.flags              = 0;
    873. 

  873.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    874. 

  874.     info.group_index        = 0;
    875. 

  875.     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
    876. 

  876.     info.parent.status_addr = CVMX_L2C_INT_REG;
    877. 

  877.     info.parent.status_mask = 1ull<<16 /* tad0 */;
    878. 

  878.     info.func               = __cvmx_error_display;
    879. 

  879.     info.user_info          = (long)
    880. 

  880.         "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
    881. 

  881.     fail |= cvmx_error_add(&info);
    882. 

  882. 

  883.     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
    884. 

  884.     info.status_addr        = CVMX_L2C_ERR_TTGX(0);
    885. 

  885.     info.status_mask        = 1ull<<63 /* dbe */;
    886. 

  886.     info.enable_addr        = 0;
    887. 

  887.     info.enable_mask        = 0;
    888. 

  888.     info.flags              = 0;
    889. 

  889.     info.group              = CVMX_ERROR_GROUP_INTERNAL;
    890. 

  890.     info.group_index        = 0;
    891. 

  891.     info.parent.reg_type    = CVMX_ERROR_REGIST…
    892.

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