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/drivers/video/aty/aty128fb.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C | 2570 lines | 1850 code | 425 blank | 295 comment | 232 complexity | 6bbd4576d8c18e46b678dda081a5a1d9 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0

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   1/* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
   2 *  linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
   3 *
   4 *  Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
   5 *  Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
   6 *
   7 *                Ani Joshi / Jeff Garzik
   8 *                      - Code cleanup
   9 *
  10 *                Michel Danzer <michdaen@iiic.ethz.ch>
  11 *                      - 15/16 bit cleanup
  12 *                      - fix panning
  13 *
  14 *                Benjamin Herrenschmidt
  15 *                      - pmac-specific PM stuff
  16 *			- various fixes & cleanups
  17 *
  18 *                Andreas Hundt <andi@convergence.de>
  19 *                      - FB_ACTIVATE fixes
  20 *
  21 *		  Paul Mackerras <paulus@samba.org>
  22 *			- Convert to new framebuffer API,
  23 *			  fix colormap setting at 16 bits/pixel (565)
  24 *
  25 *		  Paul Mundt 
  26 *		  	- PCI hotplug
  27 *
  28 *		  Jon Smirl <jonsmirl@yahoo.com>
  29 * 			- PCI ID update
  30 * 			- replace ROM BIOS search
  31 *
  32 *  Based off of Geert's atyfb.c and vfb.c.
  33 *
  34 *  TODO:
  35 *		- monitor sensing (DDC)
  36 *              - virtual display
  37 *		- other platform support (only ppc/x86 supported)
  38 *		- hardware cursor support
  39 *
  40 *    Please cc: your patches to brad@neruo.com.
  41 */
  42
  43/*
  44 * A special note of gratitude to ATI's devrel for providing documentation,
  45 * example code and hardware. Thanks Nitya.	-atong and brad
  46 */
  47
  48
  49#include <linux/module.h>
  50#include <linux/moduleparam.h>
  51#include <linux/kernel.h>
  52#include <linux/errno.h>
  53#include <linux/string.h>
  54#include <linux/mm.h>
  55#include <linux/vmalloc.h>
  56#include <linux/delay.h>
  57#include <linux/interrupt.h>
  58#include <linux/uaccess.h>
  59#include <linux/fb.h>
  60#include <linux/init.h>
  61#include <linux/pci.h>
  62#include <linux/ioport.h>
  63#include <linux/console.h>
  64#include <linux/backlight.h>
  65#include <asm/io.h>
  66
  67#ifdef CONFIG_PPC_PMAC
  68#include <asm/machdep.h>
  69#include <asm/pmac_feature.h>
  70#include <asm/prom.h>
  71#include <asm/pci-bridge.h>
  72#include "../macmodes.h"
  73#endif
  74
  75#ifdef CONFIG_PMAC_BACKLIGHT
  76#include <asm/backlight.h>
  77#endif
  78
  79#ifdef CONFIG_BOOTX_TEXT
  80#include <asm/btext.h>
  81#endif /* CONFIG_BOOTX_TEXT */
  82
  83#ifdef CONFIG_MTRR
  84#include <asm/mtrr.h>
  85#endif
  86
  87#include <video/aty128.h>
  88
  89/* Debug flag */
  90#undef DEBUG
  91
  92#ifdef DEBUG
  93#define DBG(fmt, args...)		printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args);
  94#else
  95#define DBG(fmt, args...)
  96#endif
  97
  98#ifndef CONFIG_PPC_PMAC
  99/* default mode */
 100static struct fb_var_screeninfo default_var __devinitdata = {
 101	/* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 102	640, 480, 640, 480, 0, 0, 8, 0,
 103	{0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 104	0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 105	0, FB_VMODE_NONINTERLACED
 106};
 107
 108#else /* CONFIG_PPC_PMAC */
 109/* default to 1024x768 at 75Hz on PPC - this will work
 110 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
 111static struct fb_var_screeninfo default_var = {
 112	/* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
 113	1024, 768, 1024, 768, 0, 0, 8, 0,
 114	{0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 115	0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
 116	FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 117	FB_VMODE_NONINTERLACED
 118};
 119#endif /* CONFIG_PPC_PMAC */
 120
 121/* default modedb mode */
 122/* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
 123static struct fb_videomode defaultmode __devinitdata = {
 124	.refresh =	60,
 125	.xres =		640,
 126	.yres =		480,
 127	.pixclock =	39722,
 128	.left_margin =	48,
 129	.right_margin =	16,
 130	.upper_margin =	33,
 131	.lower_margin =	10,
 132	.hsync_len =	96,
 133	.vsync_len =	2,
 134	.sync =		0,
 135	.vmode =	FB_VMODE_NONINTERLACED
 136};
 137
 138/* Chip generations */
 139enum {
 140	rage_128,
 141	rage_128_pci,
 142	rage_128_pro,
 143	rage_128_pro_pci,
 144	rage_M3,
 145	rage_M3_pci,
 146	rage_M4,
 147	rage_128_ultra,
 148};
 149
 150/* Must match above enum */
 151static const char *r128_family[] __devinitdata = {
 152	"AGP",
 153	"PCI",
 154	"PRO AGP",
 155	"PRO PCI",
 156	"M3 AGP",
 157	"M3 PCI",
 158	"M4 AGP",
 159	"Ultra AGP",
 160};
 161
 162/*
 163 * PCI driver prototypes
 164 */
 165static int aty128_probe(struct pci_dev *pdev,
 166                               const struct pci_device_id *ent);
 167static void aty128_remove(struct pci_dev *pdev);
 168static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
 169static int aty128_pci_resume(struct pci_dev *pdev);
 170static int aty128_do_resume(struct pci_dev *pdev);
 171
 172/* supported Rage128 chipsets */
 173static struct pci_device_id aty128_pci_tbl[] = {
 174	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
 175	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
 176	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
 177	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
 178	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
 179	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
 180	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
 181	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
 182	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
 183	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 184	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
 185	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 186	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
 187	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 188	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
 189	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
 190	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
 191	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 192	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
 193	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 194	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
 195	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 196	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
 197	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 198	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
 199	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 200	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
 201	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 202	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
 203	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 204	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
 205	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 206	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
 207	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 208	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
 209	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 210	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
 211	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 212	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
 213	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
 214	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
 215	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 216	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
 217	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
 218	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
 219	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 220	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
 221	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 222	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
 223	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 224	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
 225	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 226	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
 227	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 228	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
 229	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 230	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
 231	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
 232	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
 233	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 234	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
 235	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 236	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
 237	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
 238	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
 239	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 240	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
 241	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 242	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
 243	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
 244	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
 245	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 246	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
 247	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 248	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
 249	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 250	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
 251	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 252	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
 253	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 254	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
 255	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 256	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
 257	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 258	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
 259	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 260	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
 261	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 262	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
 263	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 264	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
 265	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 266	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
 267	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 268	{ 0, }
 269};
 270
 271MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
 272
 273static struct pci_driver aty128fb_driver = {
 274	.name		= "aty128fb",
 275	.id_table	= aty128_pci_tbl,
 276	.probe		= aty128_probe,
 277	.remove		= __devexit_p(aty128_remove),
 278	.suspend	= aty128_pci_suspend,
 279	.resume		= aty128_pci_resume,
 280};
 281
 282/* packed BIOS settings */
 283#ifndef CONFIG_PPC
 284typedef struct {
 285	u8 clock_chip_type;
 286	u8 struct_size;
 287	u8 accelerator_entry;
 288	u8 VGA_entry;
 289	u16 VGA_table_offset;
 290	u16 POST_table_offset;
 291	u16 XCLK;
 292	u16 MCLK;
 293	u8 num_PLL_blocks;
 294	u8 size_PLL_blocks;
 295	u16 PCLK_ref_freq;
 296	u16 PCLK_ref_divider;
 297	u32 PCLK_min_freq;
 298	u32 PCLK_max_freq;
 299	u16 MCLK_ref_freq;
 300	u16 MCLK_ref_divider;
 301	u32 MCLK_min_freq;
 302	u32 MCLK_max_freq;
 303	u16 XCLK_ref_freq;
 304	u16 XCLK_ref_divider;
 305	u32 XCLK_min_freq;
 306	u32 XCLK_max_freq;
 307} __attribute__ ((packed)) PLL_BLOCK;
 308#endif /* !CONFIG_PPC */
 309
 310/* onboard memory information */
 311struct aty128_meminfo {
 312	u8 ML;
 313	u8 MB;
 314	u8 Trcd;
 315	u8 Trp;
 316	u8 Twr;
 317	u8 CL;
 318	u8 Tr2w;
 319	u8 LoopLatency;
 320	u8 DspOn;
 321	u8 Rloop;
 322	const char *name;
 323};
 324
 325/* various memory configurations */
 326static const struct aty128_meminfo sdr_128   =
 327	{ 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
 328static const struct aty128_meminfo sdr_64    =
 329	{ 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
 330static const struct aty128_meminfo sdr_sgram =
 331	{ 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
 332static const struct aty128_meminfo ddr_sgram =
 333	{ 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
 334
 335static struct fb_fix_screeninfo aty128fb_fix __devinitdata = {
 336	.id		= "ATY Rage128",
 337	.type		= FB_TYPE_PACKED_PIXELS,
 338	.visual		= FB_VISUAL_PSEUDOCOLOR,
 339	.xpanstep	= 8,
 340	.ypanstep	= 1,
 341	.mmio_len	= 0x2000,
 342	.accel		= FB_ACCEL_ATI_RAGE128,
 343};
 344
 345static char *mode_option __devinitdata = NULL;
 346
 347#ifdef CONFIG_PPC_PMAC
 348static int default_vmode __devinitdata = VMODE_1024_768_60;
 349static int default_cmode __devinitdata = CMODE_8;
 350#endif
 351
 352static int default_crt_on __devinitdata = 0;
 353static int default_lcd_on __devinitdata = 1;
 354
 355#ifdef CONFIG_MTRR
 356static bool mtrr = true;
 357#endif
 358
 359#ifdef CONFIG_PMAC_BACKLIGHT
 360static int backlight __devinitdata = 1;
 361#else
 362static int backlight __devinitdata = 0;
 363#endif
 364
 365/* PLL constants */
 366struct aty128_constants {
 367	u32 ref_clk;
 368	u32 ppll_min;
 369	u32 ppll_max;
 370	u32 ref_divider;
 371	u32 xclk;
 372	u32 fifo_width;
 373	u32 fifo_depth;
 374};
 375
 376struct aty128_crtc {
 377	u32 gen_cntl;
 378	u32 h_total, h_sync_strt_wid;
 379	u32 v_total, v_sync_strt_wid;
 380	u32 pitch;
 381	u32 offset, offset_cntl;
 382	u32 xoffset, yoffset;
 383	u32 vxres, vyres;
 384	u32 depth, bpp;
 385};
 386
 387struct aty128_pll {
 388	u32 post_divider;
 389	u32 feedback_divider;
 390	u32 vclk;
 391};
 392
 393struct aty128_ddafifo {
 394	u32 dda_config;
 395	u32 dda_on_off;
 396};
 397
 398/* register values for a specific mode */
 399struct aty128fb_par {
 400	struct aty128_crtc crtc;
 401	struct aty128_pll pll;
 402	struct aty128_ddafifo fifo_reg;
 403	u32 accel_flags;
 404	struct aty128_constants constants;  /* PLL and others      */
 405	void __iomem *regbase;              /* remapped mmio       */
 406	u32 vram_size;                      /* onboard video ram   */
 407	int chip_gen;
 408	const struct aty128_meminfo *mem;   /* onboard mem info    */
 409#ifdef CONFIG_MTRR
 410	struct { int vram; int vram_valid; } mtrr;
 411#endif
 412	int blitter_may_be_busy;
 413	int fifo_slots;                 /* free slots in FIFO (64 max) */
 414
 415	int	pm_reg;
 416	int crt_on, lcd_on;
 417	struct pci_dev *pdev;
 418	struct fb_info *next;
 419	int	asleep;
 420	int	lock_blank;
 421
 422	u8	red[32];		/* see aty128fb_setcolreg */
 423	u8	green[64];
 424	u8	blue[32];
 425	u32	pseudo_palette[16];	/* used for TRUECOLOR */
 426};
 427
 428
 429#define round_div(n, d) ((n+(d/2))/d)
 430
 431static int aty128fb_check_var(struct fb_var_screeninfo *var,
 432			      struct fb_info *info);
 433static int aty128fb_set_par(struct fb_info *info);
 434static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 435			      u_int transp, struct fb_info *info);
 436static int aty128fb_pan_display(struct fb_var_screeninfo *var,
 437			   struct fb_info *fb);
 438static int aty128fb_blank(int blank, struct fb_info *fb);
 439static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
 440static int aty128fb_sync(struct fb_info *info);
 441
 442    /*
 443     *  Internal routines
 444     */
 445
 446static int aty128_encode_var(struct fb_var_screeninfo *var,
 447                             const struct aty128fb_par *par);
 448static int aty128_decode_var(struct fb_var_screeninfo *var,
 449                             struct aty128fb_par *par);
 450#if 0
 451static void __devinit aty128_get_pllinfo(struct aty128fb_par *par,
 452				      void __iomem *bios);
 453static void __devinit __iomem *aty128_map_ROM(struct pci_dev *pdev, const struct aty128fb_par *par);
 454#endif
 455static void aty128_timings(struct aty128fb_par *par);
 456static void aty128_init_engine(struct aty128fb_par *par);
 457static void aty128_reset_engine(const struct aty128fb_par *par);
 458static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
 459static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
 460static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
 461static void wait_for_idle(struct aty128fb_par *par);
 462static u32 depth_to_dst(u32 depth);
 463
 464#ifdef CONFIG_FB_ATY128_BACKLIGHT
 465static void aty128_bl_set_power(struct fb_info *info, int power);
 466#endif
 467
 468#define BIOS_IN8(v)  	(readb(bios + (v)))
 469#define BIOS_IN16(v) 	(readb(bios + (v)) | \
 470			  (readb(bios + (v) + 1) << 8))
 471#define BIOS_IN32(v) 	(readb(bios + (v)) | \
 472			  (readb(bios + (v) + 1) << 8) | \
 473			  (readb(bios + (v) + 2) << 16) | \
 474			  (readb(bios + (v) + 3) << 24))
 475
 476
 477static struct fb_ops aty128fb_ops = {
 478	.owner		= THIS_MODULE,
 479	.fb_check_var	= aty128fb_check_var,
 480	.fb_set_par	= aty128fb_set_par,
 481	.fb_setcolreg	= aty128fb_setcolreg,
 482	.fb_pan_display = aty128fb_pan_display,
 483	.fb_blank	= aty128fb_blank,
 484	.fb_ioctl	= aty128fb_ioctl,
 485	.fb_sync	= aty128fb_sync,
 486	.fb_fillrect	= cfb_fillrect,
 487	.fb_copyarea	= cfb_copyarea,
 488	.fb_imageblit	= cfb_imageblit,
 489};
 490
 491    /*
 492     * Functions to read from/write to the mmio registers
 493     *	- endian conversions may possibly be avoided by
 494     *    using the other register aperture. TODO.
 495     */
 496static inline u32 _aty_ld_le32(volatile unsigned int regindex, 
 497			       const struct aty128fb_par *par)
 498{
 499	return readl (par->regbase + regindex);
 500}
 501
 502static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, 
 503				const struct aty128fb_par *par)
 504{
 505	writel (val, par->regbase + regindex);
 506}
 507
 508static inline u8 _aty_ld_8(unsigned int regindex,
 509			   const struct aty128fb_par *par)
 510{
 511	return readb (par->regbase + regindex);
 512}
 513
 514static inline void _aty_st_8(unsigned int regindex, u8 val,
 515			     const struct aty128fb_par *par)
 516{
 517	writeb (val, par->regbase + regindex);
 518}
 519
 520#define aty_ld_le32(regindex)		_aty_ld_le32(regindex, par)
 521#define aty_st_le32(regindex, val)	_aty_st_le32(regindex, val, par)
 522#define aty_ld_8(regindex)		_aty_ld_8(regindex, par)
 523#define aty_st_8(regindex, val)		_aty_st_8(regindex, val, par)
 524
 525    /*
 526     * Functions to read from/write to the pll registers
 527     */
 528
 529#define aty_ld_pll(pll_index)		_aty_ld_pll(pll_index, par)
 530#define aty_st_pll(pll_index, val)	_aty_st_pll(pll_index, val, par)
 531
 532
 533static u32 _aty_ld_pll(unsigned int pll_index,
 534		       const struct aty128fb_par *par)
 535{       
 536	aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
 537	return aty_ld_le32(CLOCK_CNTL_DATA);
 538}
 539
 540    
 541static void _aty_st_pll(unsigned int pll_index, u32 val,
 542			const struct aty128fb_par *par)
 543{
 544	aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
 545	aty_st_le32(CLOCK_CNTL_DATA, val);
 546}
 547
 548
 549/* return true when the PLL has completed an atomic update */
 550static int aty_pll_readupdate(const struct aty128fb_par *par)
 551{
 552	return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
 553}
 554
 555
 556static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
 557{
 558	unsigned long timeout = jiffies + HZ/100; // should be more than enough
 559	int reset = 1;
 560
 561	while (time_before(jiffies, timeout))
 562		if (aty_pll_readupdate(par)) {
 563			reset = 0;
 564			break;
 565		}
 566
 567	if (reset)	/* reset engine?? */
 568		printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
 569}
 570
 571
 572/* tell PLL to update */
 573static void aty_pll_writeupdate(const struct aty128fb_par *par)
 574{
 575	aty_pll_wait_readupdate(par);
 576
 577	aty_st_pll(PPLL_REF_DIV,
 578		   aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
 579}
 580
 581
 582/* write to the scratch register to test r/w functionality */
 583static int __devinit register_test(const struct aty128fb_par *par)
 584{
 585	u32 val;
 586	int flag = 0;
 587
 588	val = aty_ld_le32(BIOS_0_SCRATCH);
 589
 590	aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
 591	if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
 592		aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
 593
 594		if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
 595			flag = 1; 
 596	}
 597
 598	aty_st_le32(BIOS_0_SCRATCH, val);	// restore value
 599	return flag;
 600}
 601
 602
 603/*
 604 * Accelerator engine functions
 605 */
 606static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
 607{
 608	int i;
 609
 610	for (;;) {
 611		for (i = 0; i < 2000000; i++) {
 612			par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
 613			if (par->fifo_slots >= entries)
 614				return;
 615		}
 616		aty128_reset_engine(par);
 617	}
 618}
 619
 620
 621static void wait_for_idle(struct aty128fb_par *par)
 622{
 623	int i;
 624
 625	do_wait_for_fifo(64, par);
 626
 627	for (;;) {
 628		for (i = 0; i < 2000000; i++) {
 629			if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
 630				aty128_flush_pixel_cache(par);
 631				par->blitter_may_be_busy = 0;
 632				return;
 633			}
 634		}
 635		aty128_reset_engine(par);
 636	}
 637}
 638
 639
 640static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
 641{
 642	if (par->fifo_slots < entries)
 643		do_wait_for_fifo(64, par);
 644	par->fifo_slots -= entries;
 645}
 646
 647
 648static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
 649{
 650	int i;
 651	u32 tmp;
 652
 653	tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
 654	tmp &= ~(0x00ff);
 655	tmp |= 0x00ff;
 656	aty_st_le32(PC_NGUI_CTLSTAT, tmp);
 657
 658	for (i = 0; i < 2000000; i++)
 659		if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
 660			break;
 661}
 662
 663
 664static void aty128_reset_engine(const struct aty128fb_par *par)
 665{
 666	u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
 667
 668	aty128_flush_pixel_cache(par);
 669
 670	clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
 671	mclk_cntl = aty_ld_pll(MCLK_CNTL);
 672
 673	aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
 674
 675	gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
 676	aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
 677	aty_ld_le32(GEN_RESET_CNTL);
 678	aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
 679	aty_ld_le32(GEN_RESET_CNTL);
 680
 681	aty_st_pll(MCLK_CNTL, mclk_cntl);
 682	aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
 683	aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
 684
 685	/* use old pio mode */
 686	aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
 687
 688	DBG("engine reset");
 689}
 690
 691
 692static void aty128_init_engine(struct aty128fb_par *par)
 693{
 694	u32 pitch_value;
 695
 696	wait_for_idle(par);
 697
 698	/* 3D scaler not spoken here */
 699	wait_for_fifo(1, par);
 700	aty_st_le32(SCALE_3D_CNTL, 0x00000000);
 701
 702	aty128_reset_engine(par);
 703
 704	pitch_value = par->crtc.pitch;
 705	if (par->crtc.bpp == 24) {
 706		pitch_value = pitch_value * 3;
 707	}
 708
 709	wait_for_fifo(4, par);
 710	/* setup engine offset registers */
 711	aty_st_le32(DEFAULT_OFFSET, 0x00000000);
 712
 713	/* setup engine pitch registers */
 714	aty_st_le32(DEFAULT_PITCH, pitch_value);
 715
 716	/* set the default scissor register to max dimensions */
 717	aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
 718
 719	/* set the drawing controls registers */
 720	aty_st_le32(DP_GUI_MASTER_CNTL,
 721		    GMC_SRC_PITCH_OFFSET_DEFAULT		|
 722		    GMC_DST_PITCH_OFFSET_DEFAULT		|
 723		    GMC_SRC_CLIP_DEFAULT			|
 724		    GMC_DST_CLIP_DEFAULT			|
 725		    GMC_BRUSH_SOLIDCOLOR			|
 726		    (depth_to_dst(par->crtc.depth) << 8)	|
 727		    GMC_SRC_DSTCOLOR			|
 728		    GMC_BYTE_ORDER_MSB_TO_LSB		|
 729		    GMC_DP_CONVERSION_TEMP_6500		|
 730		    ROP3_PATCOPY				|
 731		    GMC_DP_SRC_RECT				|
 732		    GMC_3D_FCN_EN_CLR			|
 733		    GMC_DST_CLR_CMP_FCN_CLEAR		|
 734		    GMC_AUX_CLIP_CLEAR			|
 735		    GMC_WRITE_MASK_SET);
 736
 737	wait_for_fifo(8, par);
 738	/* clear the line drawing registers */
 739	aty_st_le32(DST_BRES_ERR, 0);
 740	aty_st_le32(DST_BRES_INC, 0);
 741	aty_st_le32(DST_BRES_DEC, 0);
 742
 743	/* set brush color registers */
 744	aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
 745	aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
 746
 747	/* set source color registers */
 748	aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF);   /* white */
 749	aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000);   /* black */
 750
 751	/* default write mask */
 752	aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
 753
 754	/* Wait for all the writes to be completed before returning */
 755	wait_for_idle(par);
 756}
 757
 758
 759/* convert depth values to their register representation */
 760static u32 depth_to_dst(u32 depth)
 761{
 762	if (depth <= 8)
 763		return DST_8BPP;
 764	else if (depth <= 15)
 765		return DST_15BPP;
 766	else if (depth == 16)
 767		return DST_16BPP;
 768	else if (depth <= 24)
 769		return DST_24BPP;
 770	else if (depth <= 32)
 771		return DST_32BPP;
 772
 773	return -EINVAL;
 774}
 775
 776/*
 777 * PLL informations retreival
 778 */
 779
 780
 781#ifndef __sparc__
 782static void __iomem * __devinit aty128_map_ROM(const struct aty128fb_par *par, struct pci_dev *dev)
 783{
 784	u16 dptr;
 785	u8 rom_type;
 786	void __iomem *bios;
 787	size_t rom_size;
 788
 789    	/* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
 790    	unsigned int temp;
 791	temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
 792	temp &= 0x00ffffffu;
 793	temp |= 0x04 << 24;
 794	aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
 795	temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
 796
 797	bios = pci_map_rom(dev, &rom_size);
 798
 799	if (!bios) {
 800		printk(KERN_ERR "aty128fb: ROM failed to map\n");
 801		return NULL;
 802	}
 803
 804	/* Very simple test to make sure it appeared */
 805	if (BIOS_IN16(0) != 0xaa55) {
 806		printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
 807			" be 0xaa55\n", BIOS_IN16(0));
 808		goto failed;
 809	}
 810
 811	/* Look for the PCI data to check the ROM type */
 812	dptr = BIOS_IN16(0x18);
 813
 814	/* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
 815	 * for now, until I've verified this works everywhere. The goal here is more
 816	 * to phase out Open Firmware images.
 817	 *
 818	 * Currently, we only look at the first PCI data, we could iteratre and deal with
 819	 * them all, and we should use fb_bios_start relative to start of image and not
 820	 * relative start of ROM, but so far, I never found a dual-image ATI card
 821	 *
 822	 * typedef struct {
 823	 * 	u32	signature;	+ 0x00
 824	 * 	u16	vendor;		+ 0x04
 825	 * 	u16	device;		+ 0x06
 826	 * 	u16	reserved_1;	+ 0x08
 827	 * 	u16	dlen;		+ 0x0a
 828	 * 	u8	drevision;	+ 0x0c
 829	 * 	u8	class_hi;	+ 0x0d
 830	 * 	u16	class_lo;	+ 0x0e
 831	 * 	u16	ilen;		+ 0x10
 832	 * 	u16	irevision;	+ 0x12
 833	 * 	u8	type;		+ 0x14
 834	 * 	u8	indicator;	+ 0x15
 835	 * 	u16	reserved_2;	+ 0x16
 836	 * } pci_data_t;
 837	 */
 838	if (BIOS_IN32(dptr) !=  (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
 839		printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
 840		       BIOS_IN32(dptr));
 841		goto anyway;
 842	}
 843	rom_type = BIOS_IN8(dptr + 0x14);
 844	switch(rom_type) {
 845	case 0:
 846		printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
 847		break;
 848	case 1:
 849		printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
 850		goto failed;
 851	case 2:
 852		printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
 853		goto failed;
 854	default:
 855		printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", rom_type);
 856		goto failed;
 857	}
 858 anyway:
 859	return bios;
 860
 861 failed:
 862	pci_unmap_rom(dev, bios);
 863	return NULL;
 864}
 865
 866static void __devinit aty128_get_pllinfo(struct aty128fb_par *par, unsigned char __iomem *bios)
 867{
 868	unsigned int bios_hdr;
 869	unsigned int bios_pll;
 870
 871	bios_hdr = BIOS_IN16(0x48);
 872	bios_pll = BIOS_IN16(bios_hdr + 0x30);
 873	
 874	par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
 875	par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
 876	par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
 877	par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
 878	par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
 879
 880	DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
 881			par->constants.ppll_max, par->constants.ppll_min,
 882			par->constants.xclk, par->constants.ref_divider,
 883			par->constants.ref_clk);
 884
 885}           
 886
 887#ifdef CONFIG_X86
 888static void __iomem *  __devinit aty128_find_mem_vbios(struct aty128fb_par *par)
 889{
 890	/* I simplified this code as we used to miss the signatures in
 891	 * a lot of case. It's now closer to XFree, we just don't check
 892	 * for signatures at all... Something better will have to be done
 893	 * if we end up having conflicts
 894	 */
 895        u32  segstart;
 896        unsigned char __iomem *rom_base = NULL;
 897                                                
 898        for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
 899                rom_base = ioremap(segstart, 0x10000);
 900		if (rom_base == NULL)
 901			return NULL;
 902		if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
 903	                break;
 904                iounmap(rom_base);
 905		rom_base = NULL;
 906        }
 907	return rom_base;
 908}
 909#endif
 910#endif /* ndef(__sparc__) */
 911
 912/* fill in known card constants if pll_block is not available */
 913static void __devinit aty128_timings(struct aty128fb_par *par)
 914{
 915#ifdef CONFIG_PPC_OF
 916	/* instead of a table lookup, assume OF has properly
 917	 * setup the PLL registers and use their values
 918	 * to set the XCLK values and reference divider values */
 919
 920	u32 x_mpll_ref_fb_div;
 921	u32 xclk_cntl;
 922	u32 Nx, M;
 923	unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
 924#endif
 925
 926	if (!par->constants.ref_clk)
 927		par->constants.ref_clk = 2950;
 928
 929#ifdef CONFIG_PPC_OF
 930	x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
 931	xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
 932	Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
 933	M  = x_mpll_ref_fb_div & 0x0000ff;
 934
 935	par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
 936					(M * PostDivSet[xclk_cntl]));
 937
 938	par->constants.ref_divider =
 939		aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
 940#endif
 941
 942	if (!par->constants.ref_divider) {
 943		par->constants.ref_divider = 0x3b;
 944
 945		aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
 946		aty_pll_writeupdate(par);
 947	}
 948	aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
 949	aty_pll_writeupdate(par);
 950
 951	/* from documentation */
 952	if (!par->constants.ppll_min)
 953		par->constants.ppll_min = 12500;
 954	if (!par->constants.ppll_max)
 955		par->constants.ppll_max = 25000;    /* 23000 on some cards? */
 956	if (!par->constants.xclk)
 957		par->constants.xclk = 0x1d4d;	     /* same as mclk */
 958
 959	par->constants.fifo_width = 128;
 960	par->constants.fifo_depth = 32;
 961
 962	switch (aty_ld_le32(MEM_CNTL) & 0x3) {
 963	case 0:
 964		par->mem = &sdr_128;
 965		break;
 966	case 1:
 967		par->mem = &sdr_sgram;
 968		break;
 969	case 2:
 970		par->mem = &ddr_sgram;
 971		break;
 972	default:
 973		par->mem = &sdr_sgram;
 974	}
 975}
 976
 977
 978
 979/*
 980 * CRTC programming
 981 */
 982
 983/* Program the CRTC registers */
 984static void aty128_set_crtc(const struct aty128_crtc *crtc,
 985			    const struct aty128fb_par *par)
 986{
 987	aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
 988	aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
 989	aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
 990	aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
 991	aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
 992	aty_st_le32(CRTC_PITCH, crtc->pitch);
 993	aty_st_le32(CRTC_OFFSET, crtc->offset);
 994	aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
 995	/* Disable ATOMIC updating.  Is this the right place? */
 996	aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
 997}
 998
 999
1000static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1001			      struct aty128_crtc *crtc,
1002			      const struct aty128fb_par *par)
1003{
1004	u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1005	u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1006	u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1007	u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1008	u32 depth, bytpp;
1009	u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1010
1011	/* input */
1012	xres = var->xres;
1013	yres = var->yres;
1014	vxres   = var->xres_virtual;
1015	vyres   = var->yres_virtual;
1016	xoffset = var->xoffset;
1017	yoffset = var->yoffset;
1018	bpp   = var->bits_per_pixel;
1019	left  = var->left_margin;
1020	right = var->right_margin;
1021	upper = var->upper_margin;
1022	lower = var->lower_margin;
1023	hslen = var->hsync_len;
1024	vslen = var->vsync_len;
1025	sync  = var->sync;
1026	vmode = var->vmode;
1027
1028	if (bpp != 16)
1029		depth = bpp;
1030	else
1031		depth = (var->green.length == 6) ? 16 : 15;
1032
1033	/* check for mode eligibility
1034	 * accept only non interlaced modes */
1035	if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1036		return -EINVAL;
1037
1038	/* convert (and round up) and validate */
1039	xres = (xres + 7) & ~7;
1040	xoffset = (xoffset + 7) & ~7;
1041
1042	if (vxres < xres + xoffset)
1043		vxres = xres + xoffset;
1044
1045	if (vyres < yres + yoffset)
1046		vyres = yres + yoffset;
1047
1048	/* convert depth into ATI register depth */
1049	dst = depth_to_dst(depth);
1050
1051	if (dst == -EINVAL) {
1052		printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1053		return -EINVAL;
1054	}
1055
1056	/* convert register depth to bytes per pixel */
1057	bytpp = mode_bytpp[dst];
1058
1059	/* make sure there is enough video ram for the mode */
1060	if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1061		printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1062		return -EINVAL;
1063	}
1064
1065	h_disp = (xres >> 3) - 1;
1066	h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1067
1068	v_disp = yres - 1;
1069	v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1070
1071	/* check to make sure h_total and v_total are in range */
1072	if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1073		printk(KERN_ERR "aty128fb: invalid width ranges\n");
1074		return -EINVAL;
1075	}
1076
1077	h_sync_wid = (hslen + 7) >> 3;
1078	if (h_sync_wid == 0)
1079		h_sync_wid = 1;
1080	else if (h_sync_wid > 0x3f)        /* 0x3f = max hwidth */
1081		h_sync_wid = 0x3f;
1082
1083	h_sync_strt = (h_disp << 3) + right;
1084
1085	v_sync_wid = vslen;
1086	if (v_sync_wid == 0)
1087		v_sync_wid = 1;
1088	else if (v_sync_wid > 0x1f)        /* 0x1f = max vwidth */
1089		v_sync_wid = 0x1f;
1090    
1091	v_sync_strt = v_disp + lower;
1092
1093	h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1094	v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1095    
1096	c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1097
1098	crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1099
1100	crtc->h_total = h_total | (h_disp << 16);
1101	crtc->v_total = v_total | (v_disp << 16);
1102
1103	crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1104	        (h_sync_pol << 23);
1105	crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1106                (v_sync_pol << 23);
1107
1108	crtc->pitch = vxres >> 3;
1109
1110	crtc->offset = 0;
1111
1112	if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1113		crtc->offset_cntl = 0x00010000;
1114	else
1115		crtc->offset_cntl = 0;
1116
1117	crtc->vxres = vxres;
1118	crtc->vyres = vyres;
1119	crtc->xoffset = xoffset;
1120	crtc->yoffset = yoffset;
1121	crtc->depth = depth;
1122	crtc->bpp = bpp;
1123
1124	return 0;
1125}
1126
1127
1128static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1129{
1130
1131	/* fill in pixel info */
1132	var->red.msb_right = 0;
1133	var->green.msb_right = 0;
1134	var->blue.offset = 0;
1135	var->blue.msb_right = 0;
1136	var->transp.offset = 0;
1137	var->transp.length = 0;
1138	var->transp.msb_right = 0;
1139	switch (pix_width) {
1140	case CRTC_PIX_WIDTH_8BPP:
1141		var->bits_per_pixel = 8;
1142		var->red.offset = 0;
1143		var->red.length = 8;
1144		var->green.offset = 0;
1145		var->green.length = 8;
1146		var->blue.length = 8;
1147		break;
1148	case CRTC_PIX_WIDTH_15BPP:
1149		var->bits_per_pixel = 16;
1150		var->red.offset = 10;
1151		var->red.length = 5;
1152		var->green.offset = 5;
1153		var->green.length = 5;
1154		var->blue.length = 5;
1155		break;
1156	case CRTC_PIX_WIDTH_16BPP:
1157		var->bits_per_pixel = 16;
1158		var->red.offset = 11;
1159		var->red.length = 5;
1160		var->green.offset = 5;
1161		var->green.length = 6;
1162		var->blue.length = 5;
1163		break;
1164	case CRTC_PIX_WIDTH_24BPP:
1165		var->bits_per_pixel = 24;
1166		var->red.offset = 16;
1167		var->red.length = 8;
1168		var->green.offset = 8;
1169		var->green.length = 8;
1170		var->blue.length = 8;
1171		break;
1172	case CRTC_PIX_WIDTH_32BPP:
1173		var->bits_per_pixel = 32;
1174		var->red.offset = 16;
1175		var->red.length = 8;
1176		var->green.offset = 8;
1177		var->green.length = 8;
1178		var->blue.length = 8;
1179		var->transp.offset = 24;
1180		var->transp.length = 8;
1181		break;
1182	default:
1183		printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1184		return -EINVAL;
1185	}
1186
1187	return 0;
1188}
1189
1190
1191static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1192			      struct fb_var_screeninfo *var)
1193{
1194	u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1195	u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1196	u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1197	u32 pix_width;
1198
1199	/* fun with masking */
1200	h_total     = crtc->h_total & 0x1ff;
1201	h_disp      = (crtc->h_total >> 16) & 0xff;
1202	h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1203	h_sync_dly  = crtc->h_sync_strt_wid & 0x7;
1204	h_sync_wid  = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1205	h_sync_pol  = (crtc->h_sync_strt_wid >> 23) & 0x1;
1206	v_total     = crtc->v_total & 0x7ff;
1207	v_disp      = (crtc->v_total >> 16) & 0x7ff;
1208	v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1209	v_sync_wid  = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1210	v_sync_pol  = (crtc->v_sync_strt_wid >> 23) & 0x1;
1211	c_sync      = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1212	pix_width   = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1213
1214	/* do conversions */
1215	xres  = (h_disp + 1) << 3;
1216	yres  = v_disp + 1;
1217	left  = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1218	right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1219	hslen = h_sync_wid << 3;
1220	upper = v_total - v_sync_strt - v_sync_wid;
1221	lower = v_sync_strt - v_disp;
1222	vslen = v_sync_wid;
1223	sync  = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1224		(v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1225		(c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1226
1227	aty128_pix_width_to_var(pix_width, var);
1228
1229	var->xres = xres;
1230	var->yres = yres;
1231	var->xres_virtual = crtc->vxres;
1232	var->yres_virtual = crtc->vyres;
1233	var->xoffset = crtc->xoffset;
1234	var->yoffset = crtc->yoffset;
1235	var->left_margin  = left;
1236	var->right_margin = right;
1237	var->upper_margin = upper;
1238	var->lower_margin = lower;
1239	var->hsync_len = hslen;
1240	var->vsync_len = vslen;
1241	var->sync  = sync;
1242	var->vmode = FB_VMODE_NONINTERLACED;
1243
1244	return 0;
1245}
1246
1247static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1248{
1249	if (on) {
1250		aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1251		aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1252	} else
1253		aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1254}
1255
1256static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1257{
1258	u32 reg;
1259#ifdef CONFIG_FB_ATY128_BACKLIGHT
1260	struct fb_info *info = pci_get_drvdata(par->pdev);
1261#endif
1262
1263	if (on) {
1264		reg = aty_ld_le32(LVDS_GEN_CNTL);
1265		reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1266		reg &= ~LVDS_DISPLAY_DIS;
1267		aty_st_le32(LVDS_GEN_CNTL, reg);
1268#ifdef CONFIG_FB_ATY128_BACKLIGHT
1269		aty128_bl_set_power(info, FB_BLANK_UNBLANK);
1270#endif	
1271	} else {
1272#ifdef CONFIG_FB_ATY128_BACKLIGHT
1273		aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
1274#endif	
1275		reg = aty_ld_le32(LVDS_GEN_CNTL);
1276		reg |= LVDS_DISPLAY_DIS;
1277		aty_st_le32(LVDS_GEN_CNTL, reg);
1278		mdelay(100);
1279		reg &= ~(LVDS_ON /*| LVDS_EN*/);
1280		aty_st_le32(LVDS_GEN_CNTL, reg);
1281	}
1282}
1283
1284static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par)
1285{
1286	u32 div3;
1287
1288	unsigned char post_conv[] =	/* register values for post dividers */
1289        { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1290
1291	/* select PPLL_DIV_3 */
1292	aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1293
1294	/* reset PLL */
1295	aty_st_pll(PPLL_CNTL,
1296		   aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1297
1298	/* write the reference divider */
1299	aty_pll_wait_readupdate(par);
1300	aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1301	aty_pll_writeupdate(par);
1302
1303	div3 = aty_ld_pll(PPLL_DIV_3);
1304	div3 &= ~PPLL_FB3_DIV_MASK;
1305	div3 |= pll->feedback_divider;
1306	div3 &= ~PPLL_POST3_DIV_MASK;
1307	div3 |= post_conv[pll->post_divider] << 16;
1308
1309	/* write feedback and post dividers */
1310	aty_pll_wait_readupdate(par);
1311	aty_st_pll(PPLL_DIV_3, div3);
1312	aty_pll_writeupdate(par);
1313
1314	aty_pll_wait_readupdate(par);
1315	aty_st_pll(HTOTAL_CNTL, 0);	/* no horiz crtc adjustment */
1316	aty_pll_writeupdate(par);
1317
1318	/* clear the reset, just in case */
1319	aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1320}
1321
1322
1323static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1324			     const struct aty128fb_par *par)
1325{
1326	const struct aty128_constants c = par->constants;
1327	unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1328	u32 output_freq;
1329	u32 vclk;        /* in .01 MHz */
1330	int i = 0;
1331	u32 n, d;
1332
1333	vclk = 100000000 / period_in_ps;	/* convert units to 10 kHz */
1334
1335	/* adjust pixel clock if necessary */
1336	if (vclk > c.ppll_max)
1337		vclk = c.ppll_max;
1338	if (vclk * 12 < c.ppll_min)
1339		vclk = c.ppll_min/12;
1340
1341	/* now, find an acceptable divider */
1342	for (i = 0; i < ARRAY_SIZE(post_dividers); i++) {
1343		output_freq = post_dividers[i] * vclk;
1344		if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1345			pll->post_divider = post_dividers[i];
1346			break;
1347		}
1348	}
1349
1350	if (i == ARRAY_SIZE(post_dividers))
1351		return -EINVAL;
1352
1353	/* calculate feedback divider */
1354	n = c.ref_divider * output_freq;
1355	d = c.ref_clk;
1356
1357	pll->feedback_divider = round_div(n, d);
1358	pll->vclk = vclk;
1359
1360	DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1361	    "vclk_per: %d\n", pll->post_divider,
1362	    pll->feedback_divider, vclk, output_freq,
1363	    c.ref_divider, period_in_ps);
1364
1365	return 0;
1366}
1367
1368
1369static int aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var)
1370{
1371	var->pixclock = 100000000 / pll->vclk;
1372
1373	return 0;
1374}
1375
1376
1377static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1378			    const struct aty128fb_par *par)
1379{
1380	aty_st_le32(DDA_CONFIG, dsp->dda_config);
1381	aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1382}
1383
1384
1385static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1386			  const struct aty128_pll *pll,
1387			  u32 depth,
1388			  const struct aty128fb_par *par)
1389{
1390	const struct aty128_meminfo *m = par->mem;
1391	u32 xclk = par->constants.xclk;
1392	u32 fifo_width = par->constants.fifo_width;
1393	u32 fifo_depth = par->constants.fifo_depth;
1394	s32 x, b, p, ron, roff;
1395	u32 n, d, bpp;
1396
1397	/* round up to multiple of 8 */
1398	bpp = (depth+7) & ~7;
1399
1400	n = xclk * fifo_width;
1401	d = pll->vclk * bpp;
1402	x = round_div(n, d);
1403
1404	ron = 4 * m->MB +
1405		3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1406		2 * m->Trp +
1407		m->Twr +
1408		m->CL +
1409		m->Tr2w +
1410		x;
1411
1412	DBG("x %x\n", x);
1413
1414	b = 0;
1415	while (x) {
1416		x >>= 1;
1417		b++;
1418	}
1419	p = b + 1;
1420
1421	ron <<= (11 - p);
1422
1423	n <<= (11 - p);
1424	x = round_div(n, d);
1425	roff = x * (fifo_depth - 4);
1426
1427	if ((ron + m->Rloop) >= roff) {
1428		printk(KERN_ERR "aty128fb: Mode out of range!\n");
1429		return -EINVAL;
1430	}
1431
1432	DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1433	    p, m->Rloop, x, ron, roff);
1434
1435	dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1436	dsp->dda_on_off = ron << 16 | roff;
1437
1438	return 0;
1439}
1440
1441
1442/*
1443 * This actually sets the video mode.
1444 */
1445static int aty128fb_set_par(struct fb_info *info)
1446{ 
1447	struct aty128fb_par *par = info->par;
1448	u32 config;
1449	int err;
1450
1451	if ((err = aty128_decode_var(&info->var, par)) != 0)
1452		return err;
1453
1454	if (par->blitter_may_be_busy)
1455		wait_for_idle(par);
1456
1457	/* clear all registers that may interfere with mode setting */
1458	aty_st_le32(OVR_CLR, 0);
1459	aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1460	aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1461	aty_st_le32(OV0_SCALE_CNTL, 0);
1462	aty_st_le32(MPP_TB_CONFIG, 0);
1463	aty_st_le32(MPP_GP_CONFIG, 0);
1464	aty_st_le32(SUBPIC_CNTL, 0);
1465	aty_st_le32(VIPH_CONTROL, 0);
1466	aty_st_le32(I2C_CNTL_1, 0);         /* turn off i2c */
1467	aty_st_le32(GEN_INT_CNTL, 0);	/* turn off interrupts */
1468	aty_st_le32(CAP0_TRIG_CNTL, 0);
1469	aty_st_le32(CAP1_TRIG_CNTL, 0);
1470
1471	aty_st_8(CRTC_EXT_CNTL + 1, 4);	/* turn video off */
1472
1473	aty128_set_crtc(&par->crtc, par);
1474	aty128_set_pll(&par->pll, par);
1475	aty128_set_fifo(&par->fifo_reg, par);
1476
1477	config = aty_ld_le32(CNFG_CNTL) & ~3;
1478
1479#if defined(__BIG_ENDIAN)
1480	if (par->crtc.bpp == 32)
1481		config |= 2;	/* make aperture do 32 bit swapping */
1482	else if (par->crtc.bpp == 16)
1483		config |= 1;	/* make aperture do 16 bit swapping */
1484#endif
1485
1486	aty_st_le32(CNFG_CNTL, config);
1487	aty_st_8(CRTC_EXT_CNTL + 1, 0);	/* turn the video back on */
1488
1489	info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1490	info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1491		: FB_VISUAL_DIRECTCOLOR;
1492
1493	if (par->chip_gen == rage_M3) {
1494		aty128_set_crt_enable(par, par->crt_on);
1495		aty128_set_lcd_enable(par, par->lcd_on);
1496	}
1497	if (par->accel_flags & FB_ACCELF_TEXT)
1498		aty128_init_engine(par);
1499
1500#ifdef CONFIG_BOOTX_TEXT
1501	btext_update_display(info->fix.smem_start,
1502			     (((par->crtc.h_total>>16) & 0xff)+1)*8,
1503			     ((par->crtc.v_total>>16) & 0x7ff)+1,
1504			     par->crtc.bpp,
1505			     par->crtc.vxres*par->crtc.bpp/8);
1506#endif /* CONFIG_BOOTX_TEXT */
1507
1508	return 0;
1509}
1510
1511/*
1512 *  encode/decode the User Defined Part of the Display
1513 */
1514
1515static int aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par)
1516{
1517	int err;
1518	struct aty128_crtc crtc;
1519	struct aty128_pll pll;
1520	struct aty128_ddafifo fifo_reg;
1521
1522	if ((err = aty128_var_to_crtc(var, &crtc, par)))
1523		return err;
1524
1525	if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1526		return err;
1527
1528	if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1529		return err;
1530
1531	par->crtc = crtc;
1532	par->pll = pll;
1533	par->fifo_reg = fifo_reg;
1534	par->accel_flags = var->accel_flags;
1535
1536	return 0;
1537}
1538
1539
1540static int aty128_encode_var(struct fb_var_screeninfo *var,
1541			     const struct aty128fb_par *par)
1542{
1543	int err;
1544
1545	if ((err = aty128_crtc_to_var(&par->crtc, var)))
1546		return err;
1547
1548	if ((err = aty128_pll_to_var(&par->pll, var)))
1549		return err;
1550
1551	var->nonstd = 0;
1552	var->activate = 0;
1553
1554	var->height = -1;
1555	var->width = -1;
1556	var->accel_flags = par->accel_flags;
1557
1558	return 0;
1559}           
1560
1561
1562static int aty128fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1563{
1564	struct aty128fb_par par;
1565	int err;
1566
1567	par = *(struct aty128fb_par *)info->par;
1568	if ((err = aty128_decode_var(var, &par)) != 0)
1569		return err;
1570	aty128_encode_var(var, &par);
1571	return 0;
1572}
1573
1574
1575/*
1576 *  Pan or Wrap the Display
1577 */
1578static int aty128fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fb) 
1579{
1580	struct aty128fb_par *par = fb->par;
1581	u32 xoffset, yoffset;
1582	u32 offset;
1583	u32 xres, yres;
1584
1585	xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1586	yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1587
1588	xoffset = (var->xoffset +7) & ~7;
1589	yoffset = var->yoffset;
1590
1591	if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1592		return -EINVAL;
1593
1594	par->crtc.xoffset = xoffset;
1595	par->crtc.yoffset = yoffset;
1596
1597	offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7;
1598
1599	if (par->crtc.bpp == 24)
1600		offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1601
1602	aty_st_le32(CRTC_OFFSET, offset);
1603
1604	return 0;
1605}
1606
1607
1608/*
1609 *  Helper function to store a single palette register
1610 */
1611static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1612			  struct aty128fb_par *par)
1613{
1614	if (par->chip_gen == rage_M3) {
1615#if 0
1616		/* Note: For now, on M3, we set palette on both heads, which may
1617		 * be useless. Can someone with a M3 check this ?
1618		 * 
1619		 * This code would still be useful if using the second CRTC to 
1620		 * do mirroring
1621		 */
1622
1623		aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
1624		aty_st_8(PALETTE_INDEX, regno);
1625		aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1626#endif
1627		aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1628	}
1629
1630	aty_st_8(PALETTE_INDEX, regno);
1631	aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1632}
1633
1634static int aty128fb_sync(struct fb_info *info)
1635{
1636	struct aty128fb_par *par = info->par;
1637
1638	if (par->blitter_may_be_busy)
1639		wait_for_idle(par);
1640	return 0;
1641}
1642
1643#ifndef MODULE
1644static int __devinit aty128fb_setup(char *options)
1645{
1646	char *this_opt;
1647
1648	if (!options || !*options)
1649		return 0;
1650
1651	while ((this_opt = strsep(&options, ",")) != NULL) {
1652		if (!strncmp(this_opt, "lcd:", 4)) {
1653			default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1654			continue;
1655		} else if (!strncmp(this_opt, "crt:", 4)) {
1656			default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1657			continue;
1658		} else if (!strncmp(this_opt, "backlight:", 10)) {
1659			backlight = simple_strtoul(this_opt+10, NULL, 0);
1660			continue;
1661		}
1662#ifdef CONFIG_MTRR
1663		if(!strncmp(this_opt, "nomtrr", 6)) {
1664			mtrr = 0;
1665			continue;
1666		}
1667#endif
1668#ifdef CONFIG_PPC_PMAC
1669		/* vmode and cmode deprecated */
1670		if (!strncmp(this_opt, "vmode:", 6)) {
1671			unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1672			if (vmode > 0 && vmode <= VMODE_MAX)
1673				default_vmode = vmode;
1674			continue;
1675		} else if (!strncmp(this_opt, "cmode:", 6)) {
1676			unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1677			switch (cmode) {
1678			case 0:
1679			case 8:
1680				default_cmode = CMODE_8;
1681				break;
1682			case 15:
1683			case 16:
1684				default_cmode = CMODE_16;
1685				break;
1686			case 24:
1687			case 32:
1688				default_cmode = CMODE_32;
1689				break;
1690			}
1691			continue;
1692		}
1693#endif /* CONFIG_PPC_PMAC */
1694		mode_option = this_opt;
1695	}
1696	return 0;
1697}
1698#endif  /*  MODULE  */
1699
1700/* Backlight */
1701#ifdef CONFIG_FB_ATY128_BACKLIGHT
1702#define MAX_LEVEL 0xFF
1703
1704static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1705		int level)
1706{
1707	struct fb_info *info = pci_get_drvdata(par->pdev);
1708	int atylevel;
1709
1710	/* Get and convert the value */
1711	/* No locking of bl_curve since we read a single value */
1712	atylevel = MAX_LEVEL -
1713		(info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
1714
1715	if (atylevel < 0)
1716		atylevel = 0;
1717	else if (atylevel > MAX_LEVEL)
1718		atylevel = MAX_LEVEL;
1719
1720	return atylevel;
1721}
1722
1723/* We turn off the LCD completely instead of just dimming the backlight.
1724 * This provides greater power saving and the display is useless without
1725 * backlight anyway
1726 */
1727#define BACKLIGHT_LVDS_OFF
1728/* That one prevents proper CRT output with LCD off */
1729#undef BACKLIGHT_DAC_OFF
1730
1731static int aty128_bl_update_status(struct backlight_device *bd)
1732{
1733	struct aty128fb_par *par = bl_get_data(bd);
1734	unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1735	int level;
1736
1737	if (bd->props.power != FB_BLANK_UNBLANK ||
1738	    bd->props.fb_blank != FB_BLANK_UNBLANK ||
1739	    !par->lcd_on)
1740		level = 0;
1741	else
1742		level = bd->props.brightness;
1743
1744	reg |= LVDS_BL_MOD_EN | LVDS_BLON;
1745	if (level > 0) {
1746		reg |= LVDS_DIGION;
1747		if (!(reg & LVDS_ON)) {
1748			reg &= ~LVDS_BLON;
1749			aty_st_le32(LVDS_GEN_CNTL, reg);
1750			aty_ld_le32(LVDS_GEN_CNTL);
1751			mdelay(10);
1752			reg |= LVDS_BLON;
1753			aty_st_le32(LVDS_GEN_CNTL, reg);
1754		}
1755		reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1756		reg |= (aty128_bl_get_level_brightness(par, level) << LVDS_BL_MOD_LEVEL_SHIFT);
1757#ifdef BACKLIGHT_LVDS_OFF
1758		reg |= LVDS_ON | LVDS_EN;
1759		reg &= ~LVDS_DISPLAY_DIS;
1760#endif
1761		aty_st_le32(LVDS_GEN_CNTL, reg);
1762#ifdef BACKLIGHT_DAC_OFF
1763		aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1764#endif
1765	} else {
1766		reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1767		reg |= (aty128_bl_get_level_brightness(par, 0) << LVDS_BL_MOD_LEVEL_SHIFT);
1768#ifdef BACKLIGHT_LVDS_OFF
1769		reg |= LVDS_DISPLAY_DIS;
1770		aty_st_le32(LVDS_GEN_CNTL, reg);
1771		aty_ld_le32(LVDS_GEN_CNTL);
1772		udelay(10);
1773		reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
1774#endif
1775		aty_st_le32(LVDS_GEN_CNTL, reg);
1776#ifdef BACKLIGHT_DAC_OFF
1777		aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1778#endif
1779	}
1780
1781	return 0;
1782}
1783
1784static int aty128_bl_get_brightness(struct backlight_device *bd)
1785{
1786	return bd->props.brightness;
1787}
1788
1789static const struct backlight_ops aty128_bl_data = {
1790	.get_brightness	= aty128_bl_get_brightness,
1791	.update_status	= aty128_bl_update_status,
1792};
1793
1794static void aty128_bl_set_power(struct fb_info *info, int power)
1795{
1796	if (info->bl_dev) {
1797		info->bl_dev->props.power = power;
1798		backlight_update_status(info->bl_dev);
1799	}
1800}
1801
1802static void aty128_bl_init(struct aty128fb_par *par)
1803{
1804	struct backlight_properties props;
1805	struct fb_info *info = pci_get_drvdata(par->pdev);
1806	struct backlight_device *bd;
1807	char name[12];
1808
1809	/* Could be extended to Rage128Pro LVDS output too */
1810	if (par->chip_gen != rage_M3)
1811		return;
1812
1813#ifdef CONFIG_PMAC_BACKLIGHT
1814	if (!pmac_has_backlight_type("ati"))
1815		return;
1816#endif
1817
1818	snprintf(name, sizeof(name), "aty128bl%d", info->node);
1819
1820	memset(&props, 0, sizeof(struct backlight_properties));
1821	props.type = BACKLIGHT_RAW;
1822	props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
1823	bd = backlight_device_register(name, info->dev, par, &aty128_bl_data,
1824				       &props);
1825	if (IS_ERR(bd)) {
1826		info->bl_dev = NULL;
1827		printk(KERN_WARNING "aty128: Backlight registration failed\n");
1828		goto error;
1829	}
1830
1831	info->bl_dev = bd;
1832	fb_bl_default_curve(info, 0,
1833		 63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
1834		219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
1835
1836	bd->props.brightness = bd->props.max_brightness;
1837	bd->props.power = FB_BLANK_UNBLANK;
1838	backlight_update_status(bd);
1839
1840	printk("aty128: Backlight initialized (%s)\n", name);
1841
1842	return;
1843
1844error:
1845	return;
1846}
1847
1848static void aty128_bl_exit(struct backlight_device *bd)
1849{
1850	backlight_device_unregister(bd);
1851	printk("aty128: Backlight unloaded\n");
1852}
1853#endif /* CONFIG_FB_ATY128_BACKLIGHT */
1854
1855/*
1856 *  Initialisation
1857 */
1858
1859#ifdef CONFIG_PPC_PMAC__disabled
1860static void aty128_early_resume(void *data)
1861{
1862        struct aty128fb_par *par = data;
1863
1864	if (!console_trylock())
1865		return;
1866	pci_restore_state(par->pdev);
1867	aty128_do_resume(par->pdev);
1868	console_unlock();
1869}
1870#endif /* CONFIG_PPC_PMAC */
1871
1872static int __devinit aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1873{
1874	struct fb_info *info = pci_get_drvdata(pdev);
1875	struct aty128fb_par *par = info->par;
1876	struct fb_var_screeninfo var;
1877	char video_card[50];
1878	u8 chip_rev;
1879	u32 dac;
1880
1881	/* Get the chip revision */
1882	chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
1883
1884	strcpy(video_card, "Rage128 XX ");
1885	video_card[8] = ent->device >> 8;
1886	video_card[9] = ent->device & 0xFF;
1887
1888	/* range check to make sure */
1889	if (ent->driver_data < ARRAY_SIZE(r128

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