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/drivers/usb/musb/tusb6010.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C | 1280 lines | 881 code | 212 blank | 187 comment | 142 complexity | c47f426a125b86b7e6dc16162079912b MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * TUSB6010 USB 2.0 OTG Dual Role controller
  3. *
  4. * Copyright (C) 2006 Nokia Corporation
  5. * Tony Lindgren <tony@atomide.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Notes:
  12. * - Driver assumes that interface to external host (main CPU) is
  13. * configured for NOR FLASH interface instead of VLYNQ serial
  14. * interface.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/errno.h>
  19. #include <linux/init.h>
  20. #include <linux/usb.h>
  21. #include <linux/irq.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/dma-mapping.h>
  24. #include "musb_core.h"
  25. struct tusb6010_glue {
  26. struct device *dev;
  27. struct platform_device *musb;
  28. };
  29. static void tusb_musb_set_vbus(struct musb *musb, int is_on);
  30. #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
  31. #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
  32. /*
  33. * Checks the revision. We need to use the DMA register as 3.0 does not
  34. * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
  35. */
  36. u8 tusb_get_revision(struct musb *musb)
  37. {
  38. void __iomem *tbase = musb->ctrl_base;
  39. u32 die_id;
  40. u8 rev;
  41. rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
  42. if (TUSB_REV_MAJOR(rev) == 3) {
  43. die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
  44. TUSB_DIDR1_HI));
  45. if (die_id >= TUSB_DIDR1_HI_REV_31)
  46. rev |= 1;
  47. }
  48. return rev;
  49. }
  50. static int tusb_print_revision(struct musb *musb)
  51. {
  52. void __iomem *tbase = musb->ctrl_base;
  53. u8 rev;
  54. rev = tusb_get_revision(musb);
  55. pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
  56. "prcm",
  57. TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
  58. TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
  59. "int",
  60. TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
  61. TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
  62. "gpio",
  63. TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
  64. TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
  65. "dma",
  66. TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
  67. TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
  68. "dieid",
  69. TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
  70. "rev",
  71. TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
  72. return tusb_get_revision(musb);
  73. }
  74. #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
  75. | TUSB_PHY_OTG_CTRL_TESTM0)
  76. /*
  77. * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
  78. * Disables power detection in PHY for the duration of idle.
  79. */
  80. static void tusb_wbus_quirk(struct musb *musb, int enabled)
  81. {
  82. void __iomem *tbase = musb->ctrl_base;
  83. static u32 phy_otg_ctrl, phy_otg_ena;
  84. u32 tmp;
  85. if (enabled) {
  86. phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
  87. phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
  88. tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
  89. | phy_otg_ena | WBUS_QUIRK_MASK;
  90. musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
  91. tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
  92. tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
  93. musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
  94. dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
  95. musb_readl(tbase, TUSB_PHY_OTG_CTRL),
  96. musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
  97. } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
  98. & TUSB_PHY_OTG_CTRL_TESTM2) {
  99. tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
  100. musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
  101. tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
  102. musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
  103. dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
  104. musb_readl(tbase, TUSB_PHY_OTG_CTRL),
  105. musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
  106. phy_otg_ctrl = 0;
  107. phy_otg_ena = 0;
  108. }
  109. }
  110. /*
  111. * TUSB 6010 may use a parallel bus that doesn't support byte ops;
  112. * so both loading and unloading FIFOs need explicit byte counts.
  113. */
  114. static inline void
  115. tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
  116. {
  117. u32 val;
  118. int i;
  119. if (len > 4) {
  120. for (i = 0; i < (len >> 2); i++) {
  121. memcpy(&val, buf, 4);
  122. musb_writel(fifo, 0, val);
  123. buf += 4;
  124. }
  125. len %= 4;
  126. }
  127. if (len > 0) {
  128. /* Write the rest 1 - 3 bytes to FIFO */
  129. memcpy(&val, buf, len);
  130. musb_writel(fifo, 0, val);
  131. }
  132. }
  133. static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
  134. void __iomem *buf, u16 len)
  135. {
  136. u32 val;
  137. int i;
  138. if (len > 4) {
  139. for (i = 0; i < (len >> 2); i++) {
  140. val = musb_readl(fifo, 0);
  141. memcpy(buf, &val, 4);
  142. buf += 4;
  143. }
  144. len %= 4;
  145. }
  146. if (len > 0) {
  147. /* Read the rest 1 - 3 bytes from FIFO */
  148. val = musb_readl(fifo, 0);
  149. memcpy(buf, &val, len);
  150. }
  151. }
  152. void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
  153. {
  154. struct musb *musb = hw_ep->musb;
  155. void __iomem *ep_conf = hw_ep->conf;
  156. void __iomem *fifo = hw_ep->fifo;
  157. u8 epnum = hw_ep->epnum;
  158. prefetch(buf);
  159. dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
  160. 'T', epnum, fifo, len, buf);
  161. if (epnum)
  162. musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
  163. TUSB_EP_CONFIG_XFR_SIZE(len));
  164. else
  165. musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
  166. TUSB_EP0_CONFIG_XFR_SIZE(len));
  167. if (likely((0x01 & (unsigned long) buf) == 0)) {
  168. /* Best case is 32bit-aligned destination address */
  169. if ((0x02 & (unsigned long) buf) == 0) {
  170. if (len >= 4) {
  171. writesl(fifo, buf, len >> 2);
  172. buf += (len & ~0x03);
  173. len &= 0x03;
  174. }
  175. } else {
  176. if (len >= 2) {
  177. u32 val;
  178. int i;
  179. /* Cannot use writesw, fifo is 32-bit */
  180. for (i = 0; i < (len >> 2); i++) {
  181. val = (u32)(*(u16 *)buf);
  182. buf += 2;
  183. val |= (*(u16 *)buf) << 16;
  184. buf += 2;
  185. musb_writel(fifo, 0, val);
  186. }
  187. len &= 0x03;
  188. }
  189. }
  190. }
  191. if (len > 0)
  192. tusb_fifo_write_unaligned(fifo, buf, len);
  193. }
  194. void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
  195. {
  196. struct musb *musb = hw_ep->musb;
  197. void __iomem *ep_conf = hw_ep->conf;
  198. void __iomem *fifo = hw_ep->fifo;
  199. u8 epnum = hw_ep->epnum;
  200. dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
  201. 'R', epnum, fifo, len, buf);
  202. if (epnum)
  203. musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
  204. TUSB_EP_CONFIG_XFR_SIZE(len));
  205. else
  206. musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
  207. if (likely((0x01 & (unsigned long) buf) == 0)) {
  208. /* Best case is 32bit-aligned destination address */
  209. if ((0x02 & (unsigned long) buf) == 0) {
  210. if (len >= 4) {
  211. readsl(fifo, buf, len >> 2);
  212. buf += (len & ~0x03);
  213. len &= 0x03;
  214. }
  215. } else {
  216. if (len >= 2) {
  217. u32 val;
  218. int i;
  219. /* Cannot use readsw, fifo is 32-bit */
  220. for (i = 0; i < (len >> 2); i++) {
  221. val = musb_readl(fifo, 0);
  222. *(u16 *)buf = (u16)(val & 0xffff);
  223. buf += 2;
  224. *(u16 *)buf = (u16)(val >> 16);
  225. buf += 2;
  226. }
  227. len &= 0x03;
  228. }
  229. }
  230. }
  231. if (len > 0)
  232. tusb_fifo_read_unaligned(fifo, buf, len);
  233. }
  234. static struct musb *the_musb;
  235. #ifdef CONFIG_USB_GADGET_MUSB_HDRC
  236. /* This is used by gadget drivers, and OTG transceiver logic, allowing
  237. * at most mA current to be drawn from VBUS during a Default-B session
  238. * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
  239. * mode), or low power Default-B sessions, something else supplies power.
  240. * Caller must take care of locking.
  241. */
  242. static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
  243. {
  244. struct musb *musb = the_musb;
  245. void __iomem *tbase = musb->ctrl_base;
  246. u32 reg;
  247. /* tps65030 seems to consume max 100mA, with maybe 60mA available
  248. * (measured on one board) for things other than tps and tusb.
  249. *
  250. * Boards sharing the CPU clock with CLKIN will need to prevent
  251. * certain idle sleep states while the USB link is active.
  252. *
  253. * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
  254. * The actual current usage would be very board-specific. For now,
  255. * it's simpler to just use an aggregate (also board-specific).
  256. */
  257. if (x->default_a || mA < (musb->min_power << 1))
  258. mA = 0;
  259. reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
  260. if (mA) {
  261. musb->is_bus_powered = 1;
  262. reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
  263. } else {
  264. musb->is_bus_powered = 0;
  265. reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
  266. }
  267. musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
  268. dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
  269. return 0;
  270. }
  271. #else
  272. #define tusb_draw_power NULL
  273. #endif
  274. /* workaround for issue 13: change clock during chip idle
  275. * (to be fixed in rev3 silicon) ... symptoms include disconnect
  276. * or looping suspend/resume cycles
  277. */
  278. static void tusb_set_clock_source(struct musb *musb, unsigned mode)
  279. {
  280. void __iomem *tbase = musb->ctrl_base;
  281. u32 reg;
  282. reg = musb_readl(tbase, TUSB_PRCM_CONF);
  283. reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
  284. /* 0 = refclk (clkin, XI)
  285. * 1 = PHY 60 MHz (internal PLL)
  286. * 2 = not supported
  287. * 3 = what?
  288. */
  289. if (mode > 0)
  290. reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
  291. musb_writel(tbase, TUSB_PRCM_CONF, reg);
  292. /* FIXME tusb6010_platform_retime(mode == 0); */
  293. }
  294. /*
  295. * Idle TUSB6010 until next wake-up event; NOR access always wakes.
  296. * Other code ensures that we idle unless we're connected _and_ the
  297. * USB link is not suspended ... and tells us the relevant wakeup
  298. * events. SW_EN for voltage is handled separately.
  299. */
  300. static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
  301. {
  302. void __iomem *tbase = musb->ctrl_base;
  303. u32 reg;
  304. if ((wakeup_enables & TUSB_PRCM_WBUS)
  305. && (tusb_get_revision(musb) == TUSB_REV_30))
  306. tusb_wbus_quirk(musb, 1);
  307. tusb_set_clock_source(musb, 0);
  308. wakeup_enables |= TUSB_PRCM_WNORCS;
  309. musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
  310. /* REVISIT writeup of WID implies that if WID set and ID is grounded,
  311. * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
  312. * Presumably that's mostly to save power, hence WID is immaterial ...
  313. */
  314. reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
  315. /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
  316. if (is_host_active(musb)) {
  317. reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
  318. reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
  319. } else {
  320. reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
  321. reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
  322. }
  323. reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
  324. musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
  325. dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
  326. }
  327. /*
  328. * Updates cable VBUS status. Caller must take care of locking.
  329. */
  330. static int tusb_musb_vbus_status(struct musb *musb)
  331. {
  332. void __iomem *tbase = musb->ctrl_base;
  333. u32 otg_stat, prcm_mngmt;
  334. int ret = 0;
  335. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  336. prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
  337. /* Temporarily enable VBUS detection if it was disabled for
  338. * suspend mode. Unless it's enabled otg_stat and devctl will
  339. * not show correct VBUS state.
  340. */
  341. if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
  342. u32 tmp = prcm_mngmt;
  343. tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
  344. musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
  345. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  346. musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
  347. }
  348. if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
  349. ret = 1;
  350. return ret;
  351. }
  352. static struct timer_list musb_idle_timer;
  353. static void musb_do_idle(unsigned long _musb)
  354. {
  355. struct musb *musb = (void *)_musb;
  356. unsigned long flags;
  357. spin_lock_irqsave(&musb->lock, flags);
  358. switch (musb->xceiv->state) {
  359. case OTG_STATE_A_WAIT_BCON:
  360. if ((musb->a_wait_bcon != 0)
  361. && (musb->idle_timeout == 0
  362. || time_after(jiffies, musb->idle_timeout))) {
  363. dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
  364. otg_state_string(musb->xceiv->state));
  365. }
  366. /* FALLTHROUGH */
  367. case OTG_STATE_A_IDLE:
  368. tusb_musb_set_vbus(musb, 0);
  369. default:
  370. break;
  371. }
  372. if (!musb->is_active) {
  373. u32 wakeups;
  374. /* wait until khubd handles port change status */
  375. if (is_host_active(musb) && (musb->port1_status >> 16))
  376. goto done;
  377. #ifdef CONFIG_USB_GADGET_MUSB_HDRC
  378. if (is_peripheral_enabled(musb) && !musb->gadget_driver)
  379. wakeups = 0;
  380. else {
  381. wakeups = TUSB_PRCM_WHOSTDISCON
  382. | TUSB_PRCM_WBUS
  383. | TUSB_PRCM_WVBUS;
  384. if (is_otg_enabled(musb))
  385. wakeups |= TUSB_PRCM_WID;
  386. }
  387. #else
  388. wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS;
  389. #endif
  390. tusb_allow_idle(musb, wakeups);
  391. }
  392. done:
  393. spin_unlock_irqrestore(&musb->lock, flags);
  394. }
  395. /*
  396. * Maybe put TUSB6010 into idle mode mode depending on USB link status,
  397. * like "disconnected" or "suspended". We'll be woken out of it by
  398. * connect, resume, or disconnect.
  399. *
  400. * Needs to be called as the last function everywhere where there is
  401. * register access to TUSB6010 because of NOR flash wake-up.
  402. * Caller should own controller spinlock.
  403. *
  404. * Delay because peripheral enables D+ pullup 3msec after SE0, and
  405. * we don't want to treat that full speed J as a wakeup event.
  406. * ... peripherals must draw only suspend current after 10 msec.
  407. */
  408. static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
  409. {
  410. unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
  411. static unsigned long last_timer;
  412. if (timeout == 0)
  413. timeout = default_timeout;
  414. /* Never idle if active, or when VBUS timeout is not set as host */
  415. if (musb->is_active || ((musb->a_wait_bcon == 0)
  416. && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
  417. dev_dbg(musb->controller, "%s active, deleting timer\n",
  418. otg_state_string(musb->xceiv->state));
  419. del_timer(&musb_idle_timer);
  420. last_timer = jiffies;
  421. return;
  422. }
  423. if (time_after(last_timer, timeout)) {
  424. if (!timer_pending(&musb_idle_timer))
  425. last_timer = timeout;
  426. else {
  427. dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
  428. return;
  429. }
  430. }
  431. last_timer = timeout;
  432. dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
  433. otg_state_string(musb->xceiv->state),
  434. (unsigned long)jiffies_to_msecs(timeout - jiffies));
  435. mod_timer(&musb_idle_timer, timeout);
  436. }
  437. /* ticks of 60 MHz clock */
  438. #define DEVCLOCK 60000000
  439. #define OTG_TIMER_MS(msecs) ((msecs) \
  440. ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
  441. | TUSB_DEV_OTG_TIMER_ENABLE) \
  442. : 0)
  443. static void tusb_musb_set_vbus(struct musb *musb, int is_on)
  444. {
  445. void __iomem *tbase = musb->ctrl_base;
  446. u32 conf, prcm, timer;
  447. u8 devctl;
  448. /* HDRC controls CPEN, but beware current surges during device
  449. * connect. They can trigger transient overcurrent conditions
  450. * that must be ignored.
  451. */
  452. prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
  453. conf = musb_readl(tbase, TUSB_DEV_CONF);
  454. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  455. if (is_on) {
  456. timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
  457. musb->xceiv->default_a = 1;
  458. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  459. devctl |= MUSB_DEVCTL_SESSION;
  460. conf |= TUSB_DEV_CONF_USB_HOST_MODE;
  461. MUSB_HST_MODE(musb);
  462. } else {
  463. u32 otg_stat;
  464. timer = 0;
  465. /* If ID pin is grounded, we want to be a_idle */
  466. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  467. if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
  468. switch (musb->xceiv->state) {
  469. case OTG_STATE_A_WAIT_VRISE:
  470. case OTG_STATE_A_WAIT_BCON:
  471. musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
  472. break;
  473. case OTG_STATE_A_WAIT_VFALL:
  474. musb->xceiv->state = OTG_STATE_A_IDLE;
  475. break;
  476. default:
  477. musb->xceiv->state = OTG_STATE_A_IDLE;
  478. }
  479. musb->is_active = 0;
  480. musb->xceiv->default_a = 1;
  481. MUSB_HST_MODE(musb);
  482. } else {
  483. musb->is_active = 0;
  484. musb->xceiv->default_a = 0;
  485. musb->xceiv->state = OTG_STATE_B_IDLE;
  486. MUSB_DEV_MODE(musb);
  487. }
  488. devctl &= ~MUSB_DEVCTL_SESSION;
  489. conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
  490. }
  491. prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
  492. musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
  493. musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
  494. musb_writel(tbase, TUSB_DEV_CONF, conf);
  495. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  496. dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
  497. otg_state_string(musb->xceiv->state),
  498. musb_readb(musb->mregs, MUSB_DEVCTL),
  499. musb_readl(tbase, TUSB_DEV_OTG_STAT),
  500. conf, prcm);
  501. }
  502. /*
  503. * Sets the mode to OTG, peripheral or host by changing the ID detection.
  504. * Caller must take care of locking.
  505. *
  506. * Note that if a mini-A cable is plugged in the ID line will stay down as
  507. * the weak ID pull-up is not able to pull the ID up.
  508. *
  509. * REVISIT: It would be possible to add support for changing between host
  510. * and peripheral modes in non-OTG configurations by reconfiguring hardware
  511. * and then setting musb->board_mode. For now, only support OTG mode.
  512. */
  513. static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
  514. {
  515. void __iomem *tbase = musb->ctrl_base;
  516. u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
  517. if (musb->board_mode != MUSB_OTG) {
  518. ERR("Changing mode currently only supported in OTG mode\n");
  519. return -EINVAL;
  520. }
  521. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  522. phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
  523. phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
  524. dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
  525. switch (musb_mode) {
  526. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  527. case MUSB_HOST: /* Disable PHY ID detect, ground ID */
  528. phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  529. phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  530. dev_conf |= TUSB_DEV_CONF_ID_SEL;
  531. dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
  532. break;
  533. #endif
  534. #ifdef CONFIG_USB_GADGET_MUSB_HDRC
  535. case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
  536. phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  537. phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  538. dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
  539. break;
  540. #endif
  541. #ifdef CONFIG_USB_MUSB_OTG
  542. case MUSB_OTG: /* Use PHY ID detection */
  543. phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  544. phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  545. dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
  546. break;
  547. #endif
  548. default:
  549. dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
  550. return -EINVAL;
  551. }
  552. musb_writel(tbase, TUSB_PHY_OTG_CTRL,
  553. TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
  554. musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
  555. TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
  556. musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
  557. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  558. if ((musb_mode == MUSB_PERIPHERAL) &&
  559. !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
  560. INFO("Cannot be peripheral with mini-A cable "
  561. "otg_stat: %08x\n", otg_stat);
  562. return 0;
  563. }
  564. static inline unsigned long
  565. tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
  566. {
  567. u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  568. unsigned long idle_timeout = 0;
  569. /* ID pin */
  570. if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
  571. int default_a;
  572. if (is_otg_enabled(musb))
  573. default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
  574. else
  575. default_a = is_host_enabled(musb);
  576. dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
  577. musb->xceiv->default_a = default_a;
  578. tusb_musb_set_vbus(musb, default_a);
  579. /* Don't allow idling immediately */
  580. if (default_a)
  581. idle_timeout = jiffies + (HZ * 3);
  582. }
  583. /* VBUS state change */
  584. if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
  585. /* B-dev state machine: no vbus ~= disconnect */
  586. if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
  587. || !is_host_enabled(musb)) {
  588. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  589. /* ? musb_root_disconnect(musb); */
  590. musb->port1_status &=
  591. ~(USB_PORT_STAT_CONNECTION
  592. | USB_PORT_STAT_ENABLE
  593. | USB_PORT_STAT_LOW_SPEED
  594. | USB_PORT_STAT_HIGH_SPEED
  595. | USB_PORT_STAT_TEST
  596. );
  597. #endif
  598. if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
  599. dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
  600. if (musb->xceiv->state != OTG_STATE_B_IDLE) {
  601. /* INTR_DISCONNECT can hide... */
  602. musb->xceiv->state = OTG_STATE_B_IDLE;
  603. musb->int_usb |= MUSB_INTR_DISCONNECT;
  604. }
  605. musb->is_active = 0;
  606. }
  607. dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
  608. otg_state_string(musb->xceiv->state), otg_stat);
  609. idle_timeout = jiffies + (1 * HZ);
  610. schedule_work(&musb->irq_work);
  611. } else /* A-dev state machine */ {
  612. dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
  613. otg_state_string(musb->xceiv->state), otg_stat);
  614. switch (musb->xceiv->state) {
  615. case OTG_STATE_A_IDLE:
  616. dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
  617. musb_platform_set_vbus(musb, 1);
  618. /* CONNECT can wake if a_wait_bcon is set */
  619. if (musb->a_wait_bcon != 0)
  620. musb->is_active = 0;
  621. else
  622. musb->is_active = 1;
  623. /*
  624. * OPT FS A TD.4.6 needs few seconds for
  625. * A_WAIT_VRISE
  626. */
  627. idle_timeout = jiffies + (2 * HZ);
  628. break;
  629. case OTG_STATE_A_WAIT_VRISE:
  630. /* ignore; A-session-valid < VBUS_VALID/2,
  631. * we monitor this with the timer
  632. */
  633. break;
  634. case OTG_STATE_A_WAIT_VFALL:
  635. /* REVISIT this irq triggers during short
  636. * spikes caused by enumeration ...
  637. */
  638. if (musb->vbuserr_retry) {
  639. musb->vbuserr_retry--;
  640. tusb_musb_set_vbus(musb, 1);
  641. } else {
  642. musb->vbuserr_retry
  643. = VBUSERR_RETRY_COUNT;
  644. tusb_musb_set_vbus(musb, 0);
  645. }
  646. break;
  647. default:
  648. break;
  649. }
  650. }
  651. }
  652. /* OTG timer expiration */
  653. if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
  654. u8 devctl;
  655. dev_dbg(musb->controller, "%s timer, %03x\n",
  656. otg_state_string(musb->xceiv->state), otg_stat);
  657. switch (musb->xceiv->state) {
  658. case OTG_STATE_A_WAIT_VRISE:
  659. /* VBUS has probably been valid for a while now,
  660. * but may well have bounced out of range a bit
  661. */
  662. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  663. if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
  664. if ((devctl & MUSB_DEVCTL_VBUS)
  665. != MUSB_DEVCTL_VBUS) {
  666. dev_dbg(musb->controller, "devctl %02x\n", devctl);
  667. break;
  668. }
  669. musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
  670. musb->is_active = 0;
  671. idle_timeout = jiffies
  672. + msecs_to_jiffies(musb->a_wait_bcon);
  673. } else {
  674. /* REVISIT report overcurrent to hub? */
  675. ERR("vbus too slow, devctl %02x\n", devctl);
  676. tusb_musb_set_vbus(musb, 0);
  677. }
  678. break;
  679. case OTG_STATE_A_WAIT_BCON:
  680. if (musb->a_wait_bcon != 0)
  681. idle_timeout = jiffies
  682. + msecs_to_jiffies(musb->a_wait_bcon);
  683. break;
  684. case OTG_STATE_A_SUSPEND:
  685. break;
  686. case OTG_STATE_B_WAIT_ACON:
  687. break;
  688. default:
  689. break;
  690. }
  691. }
  692. schedule_work(&musb->irq_work);
  693. return idle_timeout;
  694. }
  695. static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
  696. {
  697. struct musb *musb = __hci;
  698. void __iomem *tbase = musb->ctrl_base;
  699. unsigned long flags, idle_timeout = 0;
  700. u32 int_mask, int_src;
  701. spin_lock_irqsave(&musb->lock, flags);
  702. /* Mask all interrupts to allow using both edge and level GPIO irq */
  703. int_mask = musb_readl(tbase, TUSB_INT_MASK);
  704. musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
  705. int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
  706. dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
  707. musb->int_usb = (u8) int_src;
  708. /* Acknowledge wake-up source interrupts */
  709. if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
  710. u32 reg;
  711. u32 i;
  712. if (tusb_get_revision(musb) == TUSB_REV_30)
  713. tusb_wbus_quirk(musb, 0);
  714. /* there are issues re-locking the PLL on wakeup ... */
  715. /* work around issue 8 */
  716. for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
  717. musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
  718. musb_writel(tbase, TUSB_SCRATCH_PAD, i);
  719. reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
  720. if (reg == i)
  721. break;
  722. dev_dbg(musb->controller, "TUSB NOR not ready\n");
  723. }
  724. /* work around issue 13 (2nd half) */
  725. tusb_set_clock_source(musb, 1);
  726. reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
  727. musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
  728. if (reg & ~TUSB_PRCM_WNORCS) {
  729. musb->is_active = 1;
  730. schedule_work(&musb->irq_work);
  731. }
  732. dev_dbg(musb->controller, "wake %sactive %02x\n",
  733. musb->is_active ? "" : "in", reg);
  734. /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
  735. }
  736. if (int_src & TUSB_INT_SRC_USB_IP_CONN)
  737. del_timer(&musb_idle_timer);
  738. /* OTG state change reports (annoyingly) not issued by Mentor core */
  739. if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
  740. | TUSB_INT_SRC_OTG_TIMEOUT
  741. | TUSB_INT_SRC_ID_STATUS_CHNG))
  742. idle_timeout = tusb_otg_ints(musb, int_src, tbase);
  743. /* TX dma callback must be handled here, RX dma callback is
  744. * handled in tusb_omap_dma_cb.
  745. */
  746. if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
  747. u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
  748. u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
  749. dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
  750. real_dma_src = ~real_dma_src & dma_src;
  751. if (tusb_dma_omap() && real_dma_src) {
  752. int tx_source = (real_dma_src & 0xffff);
  753. int i;
  754. for (i = 1; i <= 15; i++) {
  755. if (tx_source & (1 << i)) {
  756. dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
  757. musb_dma_completion(musb, i, 1);
  758. }
  759. }
  760. }
  761. musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
  762. }
  763. /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
  764. if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
  765. u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
  766. musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
  767. musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
  768. musb->int_tx = (musb_src & 0xffff);
  769. } else {
  770. musb->int_rx = 0;
  771. musb->int_tx = 0;
  772. }
  773. if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
  774. musb_interrupt(musb);
  775. /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
  776. musb_writel(tbase, TUSB_INT_SRC_CLEAR,
  777. int_src & ~TUSB_INT_MASK_RESERVED_BITS);
  778. tusb_musb_try_idle(musb, idle_timeout);
  779. musb_writel(tbase, TUSB_INT_MASK, int_mask);
  780. spin_unlock_irqrestore(&musb->lock, flags);
  781. return IRQ_HANDLED;
  782. }
  783. static int dma_off;
  784. /*
  785. * Enables TUSB6010. Caller must take care of locking.
  786. * REVISIT:
  787. * - Check what is unnecessary in MGC_HdrcStart()
  788. */
  789. static void tusb_musb_enable(struct musb *musb)
  790. {
  791. void __iomem *tbase = musb->ctrl_base;
  792. /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
  793. * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
  794. musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
  795. /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
  796. musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
  797. musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
  798. musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
  799. /* Clear all subsystem interrups */
  800. musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
  801. musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
  802. musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
  803. /* Acknowledge pending interrupt(s) */
  804. musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
  805. /* Only 0 clock cycles for minimum interrupt de-assertion time and
  806. * interrupt polarity active low seems to work reliably here */
  807. musb_writel(tbase, TUSB_INT_CTRL_CONF,
  808. TUSB_INT_CTRL_CONF_INT_RELCYC(0));
  809. irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
  810. /* maybe force into the Default-A OTG state machine */
  811. if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
  812. & TUSB_DEV_OTG_STAT_ID_STATUS))
  813. musb_writel(tbase, TUSB_INT_SRC_SET,
  814. TUSB_INT_SRC_ID_STATUS_CHNG);
  815. if (is_dma_capable() && dma_off)
  816. printk(KERN_WARNING "%s %s: dma not reactivated\n",
  817. __FILE__, __func__);
  818. else
  819. dma_off = 1;
  820. }
  821. /*
  822. * Disables TUSB6010. Caller must take care of locking.
  823. */
  824. static void tusb_musb_disable(struct musb *musb)
  825. {
  826. void __iomem *tbase = musb->ctrl_base;
  827. /* FIXME stop DMA, IRQs, timers, ... */
  828. /* disable all IRQs */
  829. musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
  830. musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
  831. musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
  832. musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
  833. del_timer(&musb_idle_timer);
  834. if (is_dma_capable() && !dma_off) {
  835. printk(KERN_WARNING "%s %s: dma still active\n",
  836. __FILE__, __func__);
  837. dma_off = 1;
  838. }
  839. }
  840. /*
  841. * Sets up TUSB6010 CPU interface specific signals and registers
  842. * Note: Settings optimized for OMAP24xx
  843. */
  844. static void tusb_setup_cpu_interface(struct musb *musb)
  845. {
  846. void __iomem *tbase = musb->ctrl_base;
  847. /*
  848. * Disable GPIO[5:0] pullups (used as output DMA requests)
  849. * Don't disable GPIO[7:6] as they are needed for wake-up.
  850. */
  851. musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
  852. /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
  853. musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
  854. /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
  855. musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
  856. /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
  857. * de-assertion time 2 system clocks p 62 */
  858. musb_writel(tbase, TUSB_DMA_REQ_CONF,
  859. TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
  860. TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
  861. TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
  862. /* Set 0 wait count for synchronous burst access */
  863. musb_writel(tbase, TUSB_WAIT_COUNT, 1);
  864. }
  865. static int tusb_musb_start(struct musb *musb)
  866. {
  867. void __iomem *tbase = musb->ctrl_base;
  868. int ret = 0;
  869. unsigned long flags;
  870. u32 reg;
  871. if (musb->board_set_power)
  872. ret = musb->board_set_power(1);
  873. if (ret != 0) {
  874. printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
  875. return ret;
  876. }
  877. spin_lock_irqsave(&musb->lock, flags);
  878. if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
  879. TUSB_PROD_TEST_RESET_VAL) {
  880. printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
  881. goto err;
  882. }
  883. ret = tusb_print_revision(musb);
  884. if (ret < 2) {
  885. printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
  886. ret);
  887. goto err;
  888. }
  889. /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
  890. * NOR FLASH interface is used */
  891. musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
  892. /* Select PHY free running 60MHz as a system clock */
  893. tusb_set_clock_source(musb, 1);
  894. /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
  895. * power saving, enable VBus detect and session end comparators,
  896. * enable IDpullup, enable VBus charging */
  897. musb_writel(tbase, TUSB_PRCM_MNGMT,
  898. TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
  899. TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
  900. TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
  901. TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
  902. TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
  903. tusb_setup_cpu_interface(musb);
  904. /* simplify: always sense/pullup ID pins, as if in OTG mode */
  905. reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
  906. reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  907. musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
  908. reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
  909. reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  910. musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
  911. spin_unlock_irqrestore(&musb->lock, flags);
  912. return 0;
  913. err:
  914. spin_unlock_irqrestore(&musb->lock, flags);
  915. if (musb->board_set_power)
  916. musb->board_set_power(0);
  917. return -ENODEV;
  918. }
  919. static int tusb_musb_init(struct musb *musb)
  920. {
  921. struct platform_device *pdev;
  922. struct resource *mem;
  923. void __iomem *sync = NULL;
  924. int ret;
  925. usb_nop_xceiv_register();
  926. musb->xceiv = otg_get_transceiver();
  927. if (!musb->xceiv)
  928. return -ENODEV;
  929. pdev = to_platform_device(musb->controller);
  930. /* dma address for async dma */
  931. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  932. musb->async = mem->start;
  933. /* dma address for sync dma */
  934. mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  935. if (!mem) {
  936. pr_debug("no sync dma resource?\n");
  937. ret = -ENODEV;
  938. goto done;
  939. }
  940. musb->sync = mem->start;
  941. sync = ioremap(mem->start, resource_size(mem));
  942. if (!sync) {
  943. pr_debug("ioremap for sync failed\n");
  944. ret = -ENOMEM;
  945. goto done;
  946. }
  947. musb->sync_va = sync;
  948. /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
  949. * FIFOs at 0x600, TUSB at 0x800
  950. */
  951. musb->mregs += TUSB_BASE_OFFSET;
  952. ret = tusb_musb_start(musb);
  953. if (ret) {
  954. printk(KERN_ERR "Could not start tusb6010 (%d)\n",
  955. ret);
  956. goto done;
  957. }
  958. musb->isr = tusb_musb_interrupt;
  959. if (is_peripheral_enabled(musb)) {
  960. musb->xceiv->set_power = tusb_draw_power;
  961. the_musb = musb;
  962. }
  963. setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
  964. done:
  965. if (ret < 0) {
  966. if (sync)
  967. iounmap(sync);
  968. otg_put_transceiver(musb->xceiv);
  969. usb_nop_xceiv_unregister();
  970. }
  971. return ret;
  972. }
  973. static int tusb_musb_exit(struct musb *musb)
  974. {
  975. del_timer_sync(&musb_idle_timer);
  976. the_musb = NULL;
  977. if (musb->board_set_power)
  978. musb->board_set_power(0);
  979. iounmap(musb->sync_va);
  980. otg_put_transceiver(musb->xceiv);
  981. usb_nop_xceiv_unregister();
  982. return 0;
  983. }
  984. static const struct musb_platform_ops tusb_ops = {
  985. .init = tusb_musb_init,
  986. .exit = tusb_musb_exit,
  987. .enable = tusb_musb_enable,
  988. .disable = tusb_musb_disable,
  989. .set_mode = tusb_musb_set_mode,
  990. .try_idle = tusb_musb_try_idle,
  991. .vbus_status = tusb_musb_vbus_status,
  992. .set_vbus = tusb_musb_set_vbus,
  993. };
  994. static u64 tusb_dmamask = DMA_BIT_MASK(32);
  995. static int __init tusb_probe(struct platform_device *pdev)
  996. {
  997. struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
  998. struct platform_device *musb;
  999. struct tusb6010_glue *glue;
  1000. int ret = -ENOMEM;
  1001. glue = kzalloc(sizeof(*glue), GFP_KERNEL);
  1002. if (!glue) {
  1003. dev_err(&pdev->dev, "failed to allocate glue context\n");
  1004. goto err0;
  1005. }
  1006. musb = platform_device_alloc("musb-hdrc", -1);
  1007. if (!musb) {
  1008. dev_err(&pdev->dev, "failed to allocate musb device\n");
  1009. goto err1;
  1010. }
  1011. musb->dev.parent = &pdev->dev;
  1012. musb->dev.dma_mask = &tusb_dmamask;
  1013. musb->dev.coherent_dma_mask = tusb_dmamask;
  1014. glue->dev = &pdev->dev;
  1015. glue->musb = musb;
  1016. pdata->platform_ops = &tusb_ops;
  1017. platform_set_drvdata(pdev, glue);
  1018. ret = platform_device_add_resources(musb, pdev->resource,
  1019. pdev->num_resources);
  1020. if (ret) {
  1021. dev_err(&pdev->dev, "failed to add resources\n");
  1022. goto err2;
  1023. }
  1024. ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
  1025. if (ret) {
  1026. dev_err(&pdev->dev, "failed to add platform_data\n");
  1027. goto err2;
  1028. }
  1029. ret = platform_device_add(musb);
  1030. if (ret) {
  1031. dev_err(&pdev->dev, "failed to register musb device\n");
  1032. goto err1;
  1033. }
  1034. return 0;
  1035. err2:
  1036. platform_device_put(musb);
  1037. err1:
  1038. kfree(glue);
  1039. err0:
  1040. return ret;
  1041. }
  1042. static int __exit tusb_remove(struct platform_device *pdev)
  1043. {
  1044. struct tusb6010_glue *glue = platform_get_drvdata(pdev);
  1045. platform_device_del(glue->musb);
  1046. platform_device_put(glue->musb);
  1047. kfree(glue);
  1048. return 0;
  1049. }
  1050. static struct platform_driver tusb_driver = {
  1051. .remove = __exit_p(tusb_remove),
  1052. .driver = {
  1053. .name = "musb-tusb",
  1054. },
  1055. };
  1056. MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
  1057. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  1058. MODULE_LICENSE("GPL v2");
  1059. static int __init tusb_init(void)
  1060. {
  1061. return platform_driver_probe(&tusb_driver, tusb_probe);
  1062. }
  1063. subsys_initcall(tusb_init);
  1064. static void __exit tusb_exit(void)
  1065. {
  1066. platform_driver_unregister(&tusb_driver);
  1067. }
  1068. module_exit(tusb_exit);