/drivers/staging/westbridge/astoria/include/linux/westbridge/cyasregs.h

https://bitbucket.org/slukk/jb-tsm-kernel-4.2 · C Header · 201 lines · 150 code · 31 blank · 20 comment · 0 complexity · 96844602bbd1325a4b6aa0523d8e2080 MD5 · raw file 

    

  1. /* Cypress West Bridge API header file (cyasregs.h)
    2. 

  2. ## ===========================
    3. 

  3. ## Copyright (C) 2010  Cypress Semiconductor
    4. 

  4. ##
    5. 

  5. ## This program is free software; you can redistribute it and/or
    6. 

  6. ## modify it under the terms of the GNU General Public License
    7. 

  7. ## as published by the Free Software Foundation; either version 2
    8. 

  8. ## of the License, or (at your option) any later version.
    9. 

  9. ##
    10. 

  10. ## This program is distributed in the hope that it will be useful,
    11. 

  11. ## but WITHOUT ANY WARRANTY; without even the implied warranty of
    12. 

  12. ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    13. 

  13. ## GNU General Public License for more details.
    14. 

  14. ##
    15. 

  15. ## You should have received a copy of the GNU General Public License
    16. 

  16. ## along with this program; if not, write to the Free Software
    17. 

  17. ## Foundation, Inc., 51 Franklin Street
    18. 

  18. ## Fifth Floor, Boston, MA  02110-1301, USA.
    19. 

  19. ## ===========================
    20. 

  20. */
    21. 

  21. 

  22. #ifndef _INCLUDED_CYASREG_H_
    23. 

  23. #define _INCLUDED_CYASREG_H_
    24. 

  24. 

  25. #if !defined(__doxygen__)
    26. 

  26. 

  27. #define CY_AS_MEM_CM_WB_CFG_ID (0x80)
    28. 

  28. #define		CY_AS_MEM_CM_WB_CFG_ID_VER_MASK	(0x000F)
    29. 

  29. #define		CY_AS_MEM_CM_WB_CFG_ID_HDID_MASK (0xFFF0)
    30. 

  30. #define		CY_AS_MEM_CM_WB_CFG_ID_HDID_ANTIOCH_VALUE (0xA100)
    31. 

  31. #define		CY_AS_MEM_CM_WB_CFG_ID_HDID_ASTORIA_FPGA_VALUE (0x6800)
    32. 

  32. #define		CY_AS_MEM_CM_WB_CFG_ID_HDID_ASTORIA_VALUE (0xA200)
    33. 

  33. 

  34. 

  35. #define CY_AS_MEM_RST_CTRL_REG (0x81)
    36. 

  36. #define		CY_AS_MEM_RST_CTRL_REG_HARD (0x0003)
    37. 

  37. #define		CY_AS_MEM_RST_CTRL_REG_SOFT (0x0001)
    38. 

  38. #define		CY_AS_MEM_RST_RSTCMPT (0x0004)
    39. 

  39. 

  40. #define CY_AS_MEM_P0_ENDIAN	(0x82)
    41. 

  41. #define		CY_AS_LITTLE_ENDIAN	(0x0000)
    42. 

  42. #define		CY_AS_BIG_ENDIAN (0x0101)
    43. 

  43. 

  44. #define CY_AS_MEM_P0_VM_SET	(0x83)
    45. 

  45. #define		CY_AS_MEM_P0_VM_SET_VMTYPE_MASK (0x0007)
    46. 

  46. #define		CY_AS_MEM_P0_VM_SET_VMTYPE_RAM (0x0005)
    47. 

  47. #define		CY_AS_MEM_P0_VM_SET_VMTYPE_SRAM	(0x0007)
    48. 

  48. #define		CY_AS_MEM_P0_VM_SET_VMTYPE_VMWIDTH (0x0008)
    49. 

  49. #define		CY_AS_MEM_P0_VM_SET_VMTYPE_FLOWCTRL (0x0010)
    50. 

  50. #define		CY_AS_MEM_P0_VM_SET_IFMODE (0x0020)
    51. 

  51. #define		CY_AS_MEM_P0_VM_SET_CFGMODE (0x0040)
    52. 

  52. #define		CY_AS_MEM_P0_VM_SET_DACKEOB (0x0080)
    53. 

  53. #define		CY_AS_MEM_P0_VM_SET_OVERRIDE (0x0100)
    54. 

  54. #define		CY_AS_MEM_P0_VM_SET_INTOVERD (0x0200)
    55. 

  55. #define		CY_AS_MEM_P0_VM_SET_DRQOVERD (0x0400)
    56. 

  56. #define		CY_AS_MEM_P0_VM_SET_DRQPOL (0x0800)
    57. 

  57. #define		CY_AS_MEM_P0_VM_SET_DACKPOL	(0x1000)
    58. 

  58. 

  59. 

  60. #define CY_AS_MEM_P0_NV_SET	(0x84)
    61. 

  61. #define		CY_AS_MEM_P0_NV_SET_WPSWEN	(0x0001)
    62. 

  62. #define		CY_AS_MEM_P0_NV_SET_WPPOLAR	(0x0002)
    63. 

  63. 

  64. #define CY_AS_MEM_PMU_UPDATE (0x85)
    65. 

  65. #define		CY_AS_MEM_PMU_UPDATE_UVALID (0x0001)
    66. 

  66. #define		CY_AS_MEM_PMU_UPDATE_USBUPDATE (0x0002)
    67. 

  67. #define		CY_AS_MEM_PMU_UPDATE_SDIOUPDATE (0x0004)
    68. 

  68. 

  69. #define CY_AS_MEM_P0_INTR_REG (0x90)
    70. 

  70. #define		CY_AS_MEM_P0_INTR_REG_MCUINT (0x0020)
    71. 

  71. #define		CY_AS_MEM_P0_INTR_REG_DRQINT (0x0800)
    72. 

  72. #define		CY_AS_MEM_P0_INTR_REG_MBINT	(0x1000)
    73. 

  73. #define		CY_AS_MEM_P0_INTR_REG_PMINT (0x2000)
    74. 

  74. #define		 CY_AS_MEM_P0_INTR_REG_PLLLOCKINT (0x4000)
    75. 

  75. 

  76. #define CY_AS_MEM_P0_INT_MASK_REG (0x91)
    77. 

  77. #define		CY_AS_MEM_P0_INT_MASK_REG_MMCUINT (0x0020)
    78. 

  78. #define		CY_AS_MEM_P0_INT_MASK_REG_MDRQINT (0x0800)
    79. 

  79. #define		CY_AS_MEM_P0_INT_MASK_REG_MMBINT (0x1000)
    80. 

  80. #define		CY_AS_MEM_P0_INT_MASK_REG_MPMINT (0x2000)
    81. 

  81. #define		 CY_AS_MEM_P0_INT_MASK_REG_MPLLLOCKINT (0x4000)
    82. 

  82. 

  83. #define CY_AS_MEM_MCU_MB_STAT (0x92)
    84. 

  84. #define		CY_AS_MEM_P0_MCU_MBNOTRD (0x0001)
    85. 

  85. 

  86. #define CY_AS_MEM_P0_MCU_STAT (0x94)
    87. 

  87. #define		CY_AS_MEM_P0_MCU_STAT_CARDINS (0x0001)
    88. 

  88. #define		CY_AS_MEM_P0_MCU_STAT_CARDREM (0x0002)
    89. 

  89. 

  90. #define CY_AS_MEM_PWR_MAGT_STAT	(0x95)
    91. 

  91. #define		CY_AS_MEM_PWR_MAGT_STAT_WAKEUP (0x0001)
    92. 

  92. 

  93. #define CY_AS_MEM_P0_RSE_ALLOCATE (0x98)
    94. 

  94. #define		CY_AS_MEM_P0_RSE_ALLOCATE_SDIOAVI (0x0001)
    95. 

  95. #define		CY_AS_MEM_P0_RSE_ALLOCATE_SDIOALLO (0x0002)
    96. 

  96. #define		CY_AS_MEM_P0_RSE_ALLOCATE_NANDAVI (0x0004)
    97. 

  97. #define		CY_AS_MEM_P0_RSE_ALLOCATE_NANDALLO (0x0008)
    98. 

  98. #define		CY_AS_MEM_P0_RSE_ALLOCATE_USBAVI (0x0010)
    99. 

  99. #define		CY_AS_MEM_P0_RSE_ALLOCATE_USBALLO (0x0020)
    100. 

  100. 

  101. #define CY_AS_MEM_P0_RSE_MASK				(0x9A)
    102. 

  102. #define		CY_AS_MEM_P0_RSE_MASK_MSDIOBUS_RW (0x0003)
    103. 

  103. #define		CY_AS_MEM_P0_RSE_MASK_MNANDBUS_RW (0x00C0)
    104. 

  104. #define		CY_AS_MEM_P0_RSE_MASK_MUSBBUS_RW (0x0030)
    105. 

  105. 

  106. #define CY_AS_MEM_P0_DRQ (0xA0)
    107. 

  107. #define		CY_AS_MEM_P0_DRQ_EP2DRQ	(0x0004)
    108. 

  108. #define		CY_AS_MEM_P0_DRQ_EP3DRQ	(0x0008)
    109. 

  109. #define		CY_AS_MEM_P0_DRQ_EP4DRQ	(0x0010)
    110. 

  110. #define		CY_AS_MEM_P0_DRQ_EP5DRQ	(0x0020)
    111. 

  111. #define		CY_AS_MEM_P0_DRQ_EP6DRQ	(0x0040)
    112. 

  112. #define		CY_AS_MEM_P0_DRQ_EP7DRQ	(0x0080)
    113. 

  113. #define		CY_AS_MEM_P0_DRQ_EP8DRQ	(0x0100)
    114. 

  114. #define		CY_AS_MEM_P0_DRQ_EP9DRQ	(0x0200)
    115. 

  115. #define		CY_AS_MEM_P0_DRQ_EP10DRQ (0x0400)
    116. 

  116. #define		CY_AS_MEM_P0_DRQ_EP11DRQ (0x0800)
    117. 

  117. #define		CY_AS_MEM_P0_DRQ_EP12DRQ (0x1000)
    118. 

  118. #define		CY_AS_MEM_P0_DRQ_EP13DRQ (0x2000)
    119. 

  119. #define		CY_AS_MEM_P0_DRQ_EP14DRQ (0x4000)
    120. 

  120. #define		CY_AS_MEM_P0_DRQ_EP15DRQ (0x8000)
    121. 

  121. 

  122. #define CY_AS_MEM_P0_DRQ_MASK (0xA1)
    123. 

  123. #define		CY_AS_MEM_P0_DRQ_MASK_MEP2DRQ (0x0004)
    124. 

  124. #define		CY_AS_MEM_P0_DRQ_MASK_MEP3DRQ (0x0008)
    125. 

  125. #define		CY_AS_MEM_P0_DRQ_MASK_MEP4DRQ (0x0010)
    126. 

  126. #define		CY_AS_MEM_P0_DRQ_MASK_MEP5DRQ (0x0020)
    127. 

  127. #define		CY_AS_MEM_P0_DRQ_MASK_MEP6DRQ (0x0040)
    128. 

  128. #define		CY_AS_MEM_P0_DRQ_MASK_MEP7DRQ (0x0080)
    129. 

  129. #define		CY_AS_MEM_P0_DRQ_MASK_MEP8DRQ (0x0100)
    130. 

  130. #define		CY_AS_MEM_P0_DRQ_MASK_MEP9DRQ (0x0200)
    131. 

  131. #define		CY_AS_MEM_P0_DRQ_MASK_MEP10DRQ (0x0400)
    132. 

  132. #define		CY_AS_MEM_P0_DRQ_MASK_MEP11DRQ (0x0800)
    133. 

  133. #define		CY_AS_MEM_P0_DRQ_MASK_MEP12DRQ (0x1000)
    134. 

  134. #define		CY_AS_MEM_P0_DRQ_MASK_MEP13DRQ (0x2000)
    135. 

  135. #define		CY_AS_MEM_P0_DRQ_MASK_MEP14DRQ	(0x4000)
    136. 

  136. #define		CY_AS_MEM_P0_DRQ_MASK_MEP15DRQ	(0x8000)
    137. 

  137. 

  138. #define CY_AS_MEM_P0_EP2_DMA_REG (0xA2)
    139. 

  139. #define		CY_AS_MEM_P0_E_pn_DMA_REG_COUNT_MASK (0x7FF)
    140. 

  140. #define		CY_AS_MEM_P0_E_pn_DMA_REG_DMAVAL (1 << 12)
    141. 

  141. #define CY_AS_MEM_P0_EP3_DMA_REG (0xA3)
    142. 

  142. #define CY_AS_MEM_P0_EP4_DMA_REG (0xA4)
    143. 

  143. #define CY_AS_MEM_P0_EP5_DMA_REG (0xA5)
    144. 

  144. #define CY_AS_MEM_P0_EP6_DMA_REG (0xA6)
    145. 

  145. #define CY_AS_MEM_P0_EP7_DMA_REG (0xA7)
    146. 

  146. #define CY_AS_MEM_P0_EP8_DMA_REG (0xA8)
    147. 

  147. #define CY_AS_MEM_P0_EP9_DMA_REG (0xA9)
    148. 

  148. #define CY_AS_MEM_P0_EP10_DMA_REG (0xAA)
    149. 

  149. #define CY_AS_MEM_P0_EP11_DMA_REG (0xAB)
    150. 

  150. #define CY_AS_MEM_P0_EP12_DMA_REG (0xAC)
    151. 

  151. #define CY_AS_MEM_P0_EP13_DMA_REG (0xAD)
    152. 

  152. #define CY_AS_MEM_P0_EP14_DMA_REG (0xAE)
    153. 

  153. #define CY_AS_MEM_P0_EP15_DMA_REG (0xAF)
    154. 

  154. 

  155. #define CY_AS_MEM_IROS_SLB_DATARET (0xC0)
    156. 

  156. 

  157. #define CY_AS_MEM_IROS_IO_CFG (0xC1)
    158. 

  158. #define	 CY_AS_MEM_IROS_IO_CFG_GPIODRVST_MASK (0x0003)
    159. 

  159. #define		CY_AS_MEM_IROS_IO_CFG_GPIOSLEW_MASK (0x0004)
    160. 

  160. #define	 CY_AS_MEM_IROS_IO_CFG_PPIODRVST_MASK (0x0018)
    161. 

  161. #define	 CY_AS_MEM_IROS_IO_CFG_PPIOSLEW_MASK (0x0020)
    162. 

  162. #define		CY_AS_MEM_IROS_IO_CFG_SSIODRVST_MASK (0x0300)
    163. 

  163. #define	 CY_AS_MEM_IROS_IO_CFG_SSIOSLEW_MASK (0x0400)
    164. 

  164. #define	 CY_AS_MEM_IROS_IO_CFG_SNIODRVST_MASK (0x1800)
    165. 

  165. #define		CY_AS_MEM_IROS_IO_CFG_SNIOSLEW_MASK (0x2000)
    166. 

  166. 

  167. #define CY_AS_MEM_IROS_PLL_CFG (0xC2)
    168. 

  168. 

  169. #define CY_AS_MEM_IROS_PXB_DATARET (0xC3)
    170. 

  170. 

  171. #define CY_AS_MEM_PLL_LOCK_LOSS_STAT (0xC4)
    172. 

  172. #define		 CY_AS_MEM_PLL_LOCK_LOSS_STAT_PLLSTAT (0x0800)
    173. 

  173. 

  174. #define CY_AS_MEM_IROS_SLEEP_CFG (0xC5)
    175. 

  175. 

  176. #define CY_AS_MEM_PNAND_CFG	 (0xDA)
    177. 

  177. #define CY_AS_MEM_PNAND_CFG_IOWIDTH_MASK (0x0001)
    178. 

  178. #define CY_AS_MEM_PNAND_CFG_IOWIDTH_8BIT (0x0000)
    179. 

  179. #define CY_AS_MEM_PNAND_CFG_IOWIDTH_16BIT (0x0001)
    180. 

  180. #define CY_AS_MEM_PNAND_CFG_BLKTYPE_MASK (0x0002)
    181. 

  181. #define CY_AS_MEM_PNAND_CFG_BLKTYPE_SMALL (0x0002)
    182. 

  182. #define CY_AS_MEM_PNAND_CFG_BLKTYPE_LARGE (0x0000)
    183. 

  183. #define CY_AS_MEM_PNAND_CFG_EPABYTE_POS	(4)
    184. 

  184. #define CY_AS_MEM_PNAND_CFG_EPABYTE_MASK (0x0030)
    185. 

  185. #define CY_AS_MEM_PNAND_CFG_EPABIT_POS	(6)
    186. 

  186. #define CY_AS_MEM_PNAND_CFG_EPABIT_MASK	(0x00C0)
    187. 

  187. #define CY_AS_MEM_PNAND_CFG_LNAEN_MASK	(0x0100)
    188. 

  188. 

  189. #define CY_AS_MEM_P0_MAILBOX0	(0xF0)
    190. 

  190. #define CY_AS_MEM_P0_MAILBOX1	(0xF1)
    191. 

  191. #define CY_AS_MEM_P0_MAILBOX2	(0xF2)
    192. 

  192. #define CY_AS_MEM_P0_MAILBOX3	(0xF3)
    193. 

  193. 

  194. #define CY_AS_MEM_MCU_MAILBOX0	(0xF8)
    195. 

  195. #define CY_AS_MEM_MCU_MAILBOX1	(0xF9)
    196. 

  196. #define CY_AS_MEM_MCU_MAILBOX2	(0xFA)
    197. 

  197. #define CY_AS_MEM_MCU_MAILBOX3	(0xFB)
    198. 

  198. 

  199. #endif				/* !defined(__doxygen__) */
    200. 

  200. 

  201. #endif				/* _INCLUDED_CYASREG_H_ */
    202.