/drivers/staging/sbe-2t3e3/exar7250.c
C | 217 lines | 166 code | 27 blank | 24 comment | 6 complexity | 18a7324bf0e4964e0f99dffc6f411b08 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/*
2 * SBE 2T3E3 synchronous serial card driver for Linux
3 *
4 * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * This code is based on a driver written by SBE Inc.
11 */
12
13#include "2t3e3.h"
14#include "ctrl.h"
15
16void exar7250_init(struct channel *sc)
17{
18 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE,
19 SBE_2T3E3_FRAMER_VAL_T3_CBIT |
20 SBE_2T3E3_FRAMER_VAL_INTERRUPT_ENABLE_RESET |
21 SBE_2T3E3_FRAMER_VAL_TIMING_ASYNCH_TXINCLK);
22
23 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_IO_CONTROL,
24 SBE_2T3E3_FRAMER_VAL_DISABLE_TX_LOSS_OF_CLOCK |
25 SBE_2T3E3_FRAMER_VAL_DISABLE_RX_LOSS_OF_CLOCK |
26 SBE_2T3E3_FRAMER_VAL_AMI_LINE_CODE |
27 SBE_2T3E3_FRAMER_VAL_RX_LINE_CLOCK_INVERT);
28
29 exar7250_set_frame_type(sc, SBE_2T3E3_FRAME_TYPE_T3_CBIT);
30}
31
32void exar7250_set_frame_type(struct channel *sc, u32 type)
33{
34 u32 val;
35
36 switch (type) {
37 case SBE_2T3E3_FRAME_TYPE_E3_G751:
38 case SBE_2T3E3_FRAME_TYPE_E3_G832:
39 case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
40 case SBE_2T3E3_FRAME_TYPE_T3_M13:
41 break;
42 default:
43 return;
44 }
45
46 exar7250_stop_intr(sc, type);
47
48 val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE);
49 val &= ~(SBE_2T3E3_FRAMER_VAL_LOCAL_LOOPBACK_MODE |
50 SBE_2T3E3_FRAMER_VAL_T3_E3_SELECT |
51 SBE_2T3E3_FRAMER_VAL_FRAME_FORMAT_SELECT);
52 switch (type) {
53 case SBE_2T3E3_FRAME_TYPE_E3_G751:
54 val |= SBE_2T3E3_FRAMER_VAL_E3_G751;
55 break;
56 case SBE_2T3E3_FRAME_TYPE_E3_G832:
57 val |= SBE_2T3E3_FRAMER_VAL_E3_G832;
58 break;
59 case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
60 val |= SBE_2T3E3_FRAMER_VAL_T3_CBIT;
61 break;
62 case SBE_2T3E3_FRAME_TYPE_T3_M13:
63 val |= SBE_2T3E3_FRAMER_VAL_T3_M13;
64 break;
65 default:
66 return;
67 }
68 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE, val);
69 exar7250_start_intr(sc, type);
70}
71
72
73void exar7250_start_intr(struct channel *sc, u32 type)
74{
75 u32 val;
76
77 switch (type) {
78 case SBE_2T3E3_FRAME_TYPE_E3_G751:
79 case SBE_2T3E3_FRAME_TYPE_E3_G832:
80 val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2);
81#if 0
82 sc->s.LOS = val & SBE_2T3E3_FRAMER_VAL_E3_RX_LOS ? 1 : 0;
83#else
84 cpld_LOS_update(sc);
85#endif
86 sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF ? 1 : 0;
87 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1);
88 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1,
89 SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE |
90 SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE);
91#if 0
92 /*SBE_2T3E3_FRAMER_VAL_E3_RX_COFA_INTERRUPT_ENABLE |
93 SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE |
94 SBE_2T3E3_FRAMER_VAL_E3_RX_LOF_INTERRUPT_ENABLE |
95 SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE |
96 SBE_2T3E3_FRAMER_VAL_E3_RX_AIS_INTERRUPT_ENABLE);*/
97#endif
98
99 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2);
100#if 0
101 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2,
102 SBE_2T3E3_FRAMER_VAL_E3_RX_FEBE_INTERRUPT_ENABLE |
103 SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_INTERRUPT_ENABLE |
104 SBE_2T3E3_FRAMER_VAL_E3_RX_FRAMING_BYTE_ERROR_INTERRUPT_ENABLE);
105#endif
106 break;
107
108 case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
109 case SBE_2T3E3_FRAME_TYPE_T3_M13:
110 val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS);
111#if 0
112 sc->s.LOS = val & SBE_2T3E3_FRAMER_VAL_T3_RX_LOS ? 1 : 0;
113#else
114 cpld_LOS_update(sc);
115#endif
116 sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF ? 1 : 0;
117
118 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS);
119 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE,
120 SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE |
121 SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE);
122#if 0
123 /* SBE_2T3E3_FRAMER_VAL_T3_RX_CP_BIT_ERROR_INTERRUPT_ENABLE |
124 SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE |
125 SBE_2T3E3_FRAMER_VAL_T3_RX_AIS_INTERRUPT_ENABLE |
126 SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE_INTERRUPT_ENABLE |
127 SBE_2T3E3_FRAMER_VAL_T3_RX_FERF_INTERRUPT_ENABLE |
128 SBE_2T3E3_FRAMER_VAL_T3_RX_AIC_INTERRUPT_ENABLE |
129 SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE |
130 SBE_2T3E3_FRAMER_VAL_T3_RX_P_BIT_INTERRUPT_ENABLE);*/
131#endif
132
133 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS);
134#if 0
135 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS,
136 SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_REMOVE_INTERRUPT_ENABLE |
137 SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID_INTERRUPT_ENABLE);
138#endif
139
140 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL, 0);
141 break;
142
143 default:
144 return;
145 }
146
147 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS);
148 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE,
149 SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_ENABLE |
150 SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_ENABLE);
151}
152
153
154void exar7250_stop_intr(struct channel *sc, u32 type)
155{
156 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE, 0);
157 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS);
158
159 switch (type) {
160 case SBE_2T3E3_FRAME_TYPE_E3_G751:
161 case SBE_2T3E3_FRAME_TYPE_E3_G832:
162 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1, 0);
163 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1);
164 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2, 0);
165 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2);
166 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_LAPD_CONTROL, 0);
167 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_LAPD_CONTROL);
168 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS, 0);
169 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS);
170 break;
171
172 case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
173 case SBE_2T3E3_FRAME_TYPE_T3_M13:
174 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE, 0);
175 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS);
176 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS, 0);
177 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS);
178 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL, 0);
179 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL);
180 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS, 0);
181 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS);
182 exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS, 0);
183 exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS);
184 break;
185 }
186}
187
188
189
190
191void exar7250_unipolar_onoff(struct channel *sc, u32 mode)
192{
193 switch (mode) {
194 case SBE_2T3E3_OFF:
195 exar7300_clear_bit(sc, SBE_2T3E3_FRAMER_REG_IO_CONTROL,
196 SBE_2T3E3_FRAMER_VAL_UNIPOLAR);
197 break;
198 case SBE_2T3E3_ON:
199 exar7300_set_bit(sc, SBE_2T3E3_FRAMER_REG_IO_CONTROL,
200 SBE_2T3E3_FRAMER_VAL_UNIPOLAR);
201 break;
202 }
203}
204
205void exar7250_set_loopback(struct channel *sc, u32 mode)
206{
207 switch (mode) {
208 case SBE_2T3E3_FRAMER_VAL_LOOPBACK_OFF:
209 exar7300_clear_bit(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE,
210 SBE_2T3E3_FRAMER_VAL_LOCAL_LOOPBACK_MODE);
211 break;
212 case SBE_2T3E3_FRAMER_VAL_LOOPBACK_ON:
213 exar7300_set_bit(sc, SBE_2T3E3_FRAMER_REG_OPERATING_MODE,
214 SBE_2T3E3_FRAMER_VAL_LOCAL_LOOPBACK_MODE);
215 break;
216 }
217}