/drivers/staging/rts_pstor/rtsx_card.h

https://bitbucket.org/slukk/jb-tsm-kernel-4.2 · C Header · 1093 lines · 922 code · 149 blank · 22 comment · 4 complexity · 58f9dbbdd1c572d2a41abdc348ec0196 MD5 · raw file

  1. /* Driver for Realtek PCI-Express card reader
  2. * Header file
  3. *
  4. * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2, or (at your option) any
  9. * later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program; if not, see <http://www.gnu.org/licenses/>.
  18. *
  19. * Author:
  20. * wwang (wei_wang@realsil.com.cn)
  21. * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  22. */
  23. #ifndef __REALTEK_RTSX_CARD_H
  24. #define __REALTEK_RTSX_CARD_H
  25. #include "debug.h"
  26. #include "rtsx.h"
  27. #include "rtsx_chip.h"
  28. #include "rtsx_transport.h"
  29. #include "sd.h"
  30. #define SSC_POWER_DOWN 0x01
  31. #define SD_OC_POWER_DOWN 0x02
  32. #define MS_OC_POWER_DOWN 0x04
  33. #define ALL_POWER_DOWN 0x07
  34. #define OC_POWER_DOWN 0x06
  35. #define PMOS_STRG_MASK 0x10
  36. #define PMOS_STRG_800mA 0x10
  37. #define PMOS_STRG_400mA 0x00
  38. #define POWER_OFF 0x03
  39. #define PARTIAL_POWER_ON 0x01
  40. #define POWER_ON 0x00
  41. #define MS_POWER_OFF 0x0C
  42. #define MS_PARTIAL_POWER_ON 0x04
  43. #define MS_POWER_ON 0x00
  44. #define MS_POWER_MASK 0x0C
  45. #define SD_POWER_OFF 0x03
  46. #define SD_PARTIAL_POWER_ON 0x01
  47. #define SD_POWER_ON 0x00
  48. #define SD_POWER_MASK 0x03
  49. #define XD_OUTPUT_EN 0x02
  50. #define SD_OUTPUT_EN 0x04
  51. #define MS_OUTPUT_EN 0x08
  52. #define SPI_OUTPUT_EN 0x10
  53. #define CLK_LOW_FREQ 0x01
  54. #define CLK_DIV_1 0x01
  55. #define CLK_DIV_2 0x02
  56. #define CLK_DIV_4 0x03
  57. #define CLK_DIV_8 0x04
  58. #define SSC_80 0
  59. #define SSC_100 1
  60. #define SSC_120 2
  61. #define SSC_150 3
  62. #define SSC_200 4
  63. #define XD_CLK_EN 0x02
  64. #define SD_CLK_EN 0x04
  65. #define MS_CLK_EN 0x08
  66. #define SPI_CLK_EN 0x10
  67. #define XD_MOD_SEL 1
  68. #define SD_MOD_SEL 2
  69. #define MS_MOD_SEL 3
  70. #define SPI_MOD_SEL 4
  71. #define CHANGE_CLK 0x01
  72. #define SD_CRC7_ERR 0x80
  73. #define SD_CRC16_ERR 0x40
  74. #define SD_CRC_WRITE_ERR 0x20
  75. #define SD_CRC_WRITE_ERR_MASK 0x1C
  76. #define GET_CRC_TIME_OUT 0x02
  77. #define SD_TUNING_COMPARE_ERR 0x01
  78. #define SD_RSP_80CLK_TIMEOUT 0x01
  79. #define SD_CLK_TOGGLE_EN 0x80
  80. #define SD_CLK_FORCE_STOP 0x40
  81. #define SD_DAT3_STATUS 0x10
  82. #define SD_DAT2_STATUS 0x08
  83. #define SD_DAT1_STATUS 0x04
  84. #define SD_DAT0_STATUS 0x02
  85. #define SD_CMD_STATUS 0x01
  86. #define SD_IO_USING_1V8 0x80
  87. #define SD_IO_USING_3V3 0x7F
  88. #define TYPE_A_DRIVING 0x00
  89. #define TYPE_B_DRIVING 0x01
  90. #define TYPE_C_DRIVING 0x02
  91. #define TYPE_D_DRIVING 0x03
  92. #define DDR_FIX_RX_DAT 0x00
  93. #define DDR_VAR_RX_DAT 0x80
  94. #define DDR_FIX_RX_DAT_EDGE 0x00
  95. #define DDR_FIX_RX_DAT_14_DELAY 0x40
  96. #define DDR_FIX_RX_CMD 0x00
  97. #define DDR_VAR_RX_CMD 0x20
  98. #define DDR_FIX_RX_CMD_POS_EDGE 0x00
  99. #define DDR_FIX_RX_CMD_14_DELAY 0x10
  100. #define SD20_RX_POS_EDGE 0x00
  101. #define SD20_RX_14_DELAY 0x08
  102. #define SD20_RX_SEL_MASK 0x08
  103. #define DDR_FIX_TX_CMD_DAT 0x00
  104. #define DDR_VAR_TX_CMD_DAT 0x80
  105. #define DDR_FIX_TX_DAT_14_TSU 0x00
  106. #define DDR_FIX_TX_DAT_12_TSU 0x40
  107. #define DDR_FIX_TX_CMD_NEG_EDGE 0x00
  108. #define DDR_FIX_TX_CMD_14_AHEAD 0x20
  109. #define SD20_TX_NEG_EDGE 0x00
  110. #define SD20_TX_14_AHEAD 0x10
  111. #define SD20_TX_SEL_MASK 0x10
  112. #define DDR_VAR_SDCLK_POL_SWAP 0x01
  113. #define SD_TRANSFER_START 0x80
  114. #define SD_TRANSFER_END 0x40
  115. #define SD_STAT_IDLE 0x20
  116. #define SD_TRANSFER_ERR 0x10
  117. #define SD_TM_NORMAL_WRITE 0x00
  118. #define SD_TM_AUTO_WRITE_3 0x01
  119. #define SD_TM_AUTO_WRITE_4 0x02
  120. #define SD_TM_AUTO_READ_3 0x05
  121. #define SD_TM_AUTO_READ_4 0x06
  122. #define SD_TM_CMD_RSP 0x08
  123. #define SD_TM_AUTO_WRITE_1 0x09
  124. #define SD_TM_AUTO_WRITE_2 0x0A
  125. #define SD_TM_NORMAL_READ 0x0C
  126. #define SD_TM_AUTO_READ_1 0x0D
  127. #define SD_TM_AUTO_READ_2 0x0E
  128. #define SD_TM_AUTO_TUNING 0x0F
  129. #define PHASE_CHANGE 0x80
  130. #define PHASE_NOT_RESET 0x40
  131. #define DCMPS_CHANGE 0x80
  132. #define DCMPS_CHANGE_DONE 0x40
  133. #define DCMPS_ERROR 0x20
  134. #define DCMPS_CURRENT_PHASE 0x1F
  135. #define SD_CLK_DIVIDE_0 0x00
  136. #define SD_CLK_DIVIDE_256 0xC0
  137. #define SD_CLK_DIVIDE_128 0x80
  138. #define SD_BUS_WIDTH_1 0x00
  139. #define SD_BUS_WIDTH_4 0x01
  140. #define SD_BUS_WIDTH_8 0x02
  141. #define SD_ASYNC_FIFO_NOT_RST 0x10
  142. #define SD_20_MODE 0x00
  143. #define SD_DDR_MODE 0x04
  144. #define SD_30_MODE 0x08
  145. #define SD_CLK_DIVIDE_MASK 0xC0
  146. #define SD_CMD_IDLE 0x80
  147. #define SD_DATA_IDLE 0x80
  148. #define DCM_RESET 0x08
  149. #define DCM_LOCKED 0x04
  150. #define DCM_208M 0x00
  151. #define DCM_TX 0x01
  152. #define DCM_RX 0x02
  153. #define DRP_START 0x80
  154. #define DRP_DONE 0x40
  155. #define DRP_WRITE 0x80
  156. #define DRP_READ 0x00
  157. #define DCM_WRITE_ADDRESS_50 0x50
  158. #define DCM_WRITE_ADDRESS_51 0x51
  159. #define DCM_READ_ADDRESS_00 0x00
  160. #define DCM_READ_ADDRESS_51 0x51
  161. #define SD_CALCULATE_CRC7 0x00
  162. #define SD_NO_CALCULATE_CRC7 0x80
  163. #define SD_CHECK_CRC16 0x00
  164. #define SD_NO_CHECK_CRC16 0x40
  165. #define SD_NO_CHECK_WAIT_CRC_TO 0x20
  166. #define SD_WAIT_BUSY_END 0x08
  167. #define SD_NO_WAIT_BUSY_END 0x00
  168. #define SD_CHECK_CRC7 0x00
  169. #define SD_NO_CHECK_CRC7 0x04
  170. #define SD_RSP_LEN_0 0x00
  171. #define SD_RSP_LEN_6 0x01
  172. #define SD_RSP_LEN_17 0x02
  173. #define SD_RSP_TYPE_R0 0x04
  174. #define SD_RSP_TYPE_R1 0x01
  175. #define SD_RSP_TYPE_R1b 0x09
  176. #define SD_RSP_TYPE_R2 0x02
  177. #define SD_RSP_TYPE_R3 0x05
  178. #define SD_RSP_TYPE_R4 0x05
  179. #define SD_RSP_TYPE_R5 0x01
  180. #define SD_RSP_TYPE_R6 0x01
  181. #define SD_RSP_TYPE_R7 0x01
  182. #define SD_RSP_80CLK_TIMEOUT_EN 0x01
  183. #define SAMPLE_TIME_RISING 0x00
  184. #define SAMPLE_TIME_FALLING 0x80
  185. #define PUSH_TIME_DEFAULT 0x00
  186. #define PUSH_TIME_ODD 0x40
  187. #define NO_EXTEND_TOGGLE 0x00
  188. #define EXTEND_TOGGLE_CHK 0x20
  189. #define MS_BUS_WIDTH_1 0x00
  190. #define MS_BUS_WIDTH_4 0x10
  191. #define MS_BUS_WIDTH_8 0x18
  192. #define MS_2K_SECTOR_MODE 0x04
  193. #define MS_512_SECTOR_MODE 0x00
  194. #define MS_TOGGLE_TIMEOUT_EN 0x00
  195. #define MS_TOGGLE_TIMEOUT_DISEN 0x01
  196. #define MS_NO_CHECK_INT 0x02
  197. #define WAIT_INT 0x80
  198. #define NO_WAIT_INT 0x00
  199. #define NO_AUTO_READ_INT_REG 0x00
  200. #define AUTO_READ_INT_REG 0x40
  201. #define MS_CRC16_ERR 0x20
  202. #define MS_RDY_TIMEOUT 0x10
  203. #define MS_INT_CMDNK 0x08
  204. #define MS_INT_BREQ 0x04
  205. #define MS_INT_ERR 0x02
  206. #define MS_INT_CED 0x01
  207. #define MS_TRANSFER_START 0x80
  208. #define MS_TRANSFER_END 0x40
  209. #define MS_TRANSFER_ERR 0x20
  210. #define MS_BS_STATE 0x10
  211. #define MS_TM_READ_BYTES 0x00
  212. #define MS_TM_NORMAL_READ 0x01
  213. #define MS_TM_WRITE_BYTES 0x04
  214. #define MS_TM_NORMAL_WRITE 0x05
  215. #define MS_TM_AUTO_READ 0x08
  216. #define MS_TM_AUTO_WRITE 0x0C
  217. #define CARD_SHARE_MASK 0x0F
  218. #define CARD_SHARE_MULTI_LUN 0x00
  219. #define CARD_SHARE_NORMAL 0x00
  220. #define CARD_SHARE_48_XD 0x02
  221. #define CARD_SHARE_48_SD 0x04
  222. #define CARD_SHARE_48_MS 0x08
  223. #define CARD_SHARE_BAROSSA_XD 0x00
  224. #define CARD_SHARE_BAROSSA_SD 0x01
  225. #define CARD_SHARE_BAROSSA_MS 0x02
  226. #define MS_DRIVE_8 0x00
  227. #define MS_DRIVE_4 0x40
  228. #define MS_DRIVE_12 0x80
  229. #define SD_DRIVE_8 0x00
  230. #define SD_DRIVE_4 0x10
  231. #define SD_DRIVE_12 0x20
  232. #define XD_DRIVE_8 0x00
  233. #define XD_DRIVE_4 0x04
  234. #define XD_DRIVE_12 0x08
  235. #define SPI_STOP 0x01
  236. #define XD_STOP 0x02
  237. #define SD_STOP 0x04
  238. #define MS_STOP 0x08
  239. #define SPI_CLR_ERR 0x10
  240. #define XD_CLR_ERR 0x20
  241. #define SD_CLR_ERR 0x40
  242. #define MS_CLR_ERR 0x80
  243. #define CRC_FIX_CLK (0x00 << 0)
  244. #define CRC_VAR_CLK0 (0x01 << 0)
  245. #define CRC_VAR_CLK1 (0x02 << 0)
  246. #define SD30_FIX_CLK (0x00 << 2)
  247. #define SD30_VAR_CLK0 (0x01 << 2)
  248. #define SD30_VAR_CLK1 (0x02 << 2)
  249. #define SAMPLE_FIX_CLK (0x00 << 4)
  250. #define SAMPLE_VAR_CLK0 (0x01 << 4)
  251. #define SAMPLE_VAR_CLK1 (0x02 << 4)
  252. #define SDIO_VER_20 0x80
  253. #define SDIO_VER_10 0x00
  254. #define SDIO_VER_CHG 0x40
  255. #define SDIO_BUS_AUTO_SWITCH 0x10
  256. #define PINGPONG_BUFFER 0x01
  257. #define RING_BUFFER 0x00
  258. #define RB_FLUSH 0x80
  259. #define DMA_DONE_INT_EN 0x80
  260. #define SUSPEND_INT_EN 0x40
  261. #define LINK_RDY_INT_EN 0x20
  262. #define LINK_DOWN_INT_EN 0x10
  263. #define DMA_DONE_INT 0x80
  264. #define SUSPEND_INT 0x40
  265. #define LINK_RDY_INT 0x20
  266. #define LINK_DOWN_INT 0x10
  267. #define MRD_ERR_INT_EN 0x40
  268. #define MWR_ERR_INT_EN 0x20
  269. #define SCSI_CMD_INT_EN 0x10
  270. #define TLP_RCV_INT_EN 0x08
  271. #define TLP_TRSMT_INT_EN 0x04
  272. #define MRD_COMPLETE_INT_EN 0x02
  273. #define MWR_COMPLETE_INT_EN 0x01
  274. #define MRD_ERR_INT 0x40
  275. #define MWR_ERR_INT 0x20
  276. #define SCSI_CMD_INT 0x10
  277. #define TLP_RX_INT 0x08
  278. #define TLP_TX_INT 0x04
  279. #define MRD_COMPLETE_INT 0x02
  280. #define MWR_COMPLETE_INT 0x01
  281. #define MSG_RX_INT_EN 0x08
  282. #define MRD_RX_INT_EN 0x04
  283. #define MWR_RX_INT_EN 0x02
  284. #define CPLD_RX_INT_EN 0x01
  285. #define MSG_RX_INT 0x08
  286. #define MRD_RX_INT 0x04
  287. #define MWR_RX_INT 0x02
  288. #define CPLD_RX_INT 0x01
  289. #define MSG_TX_INT_EN 0x08
  290. #define MRD_TX_INT_EN 0x04
  291. #define MWR_TX_INT_EN 0x02
  292. #define CPLD_TX_INT_EN 0x01
  293. #define MSG_TX_INT 0x08
  294. #define MRD_TX_INT 0x04
  295. #define MWR_TX_INT 0x02
  296. #define CPLD_TX_INT 0x01
  297. #define DMA_RST 0x80
  298. #define DMA_BUSY 0x04
  299. #define DMA_DIR_TO_CARD 0x00
  300. #define DMA_DIR_FROM_CARD 0x02
  301. #define DMA_EN 0x01
  302. #define DMA_128 (0 << 4)
  303. #define DMA_256 (1 << 4)
  304. #define DMA_512 (2 << 4)
  305. #define DMA_1024 (3 << 4)
  306. #define DMA_PACK_SIZE_MASK 0x30
  307. #define XD_PWR_OFF_DELAY0 0x00
  308. #define XD_PWR_OFF_DELAY1 0x02
  309. #define XD_PWR_OFF_DELAY2 0x04
  310. #define XD_PWR_OFF_DELAY3 0x06
  311. #define XD_AUTO_PWR_OFF_EN 0xF7
  312. #define XD_NO_AUTO_PWR_OFF 0x08
  313. #define XD_TIME_RWN_1 0x00
  314. #define XD_TIME_RWN_STEP 0x20
  315. #define XD_TIME_RW_1 0x00
  316. #define XD_TIME_RW_STEP 0x04
  317. #define XD_TIME_SETUP_1 0x00
  318. #define XD_TIME_SETUP_STEP 0x01
  319. #define XD_ECC2_UNCORRECTABLE 0x80
  320. #define XD_ECC2_ERROR 0x40
  321. #define XD_ECC1_UNCORRECTABLE 0x20
  322. #define XD_ECC1_ERROR 0x10
  323. #define XD_RDY 0x04
  324. #define XD_CE_EN 0xFD
  325. #define XD_CE_DISEN 0x02
  326. #define XD_WP_EN 0xFE
  327. #define XD_WP_DISEN 0x01
  328. #define XD_TRANSFER_START 0x80
  329. #define XD_TRANSFER_END 0x40
  330. #define XD_PPB_EMPTY 0x20
  331. #define XD_RESET 0x00
  332. #define XD_ERASE 0x01
  333. #define XD_READ_STATUS 0x02
  334. #define XD_READ_ID 0x03
  335. #define XD_READ_REDUNDANT 0x04
  336. #define XD_READ_PAGES 0x05
  337. #define XD_SET_CMD 0x06
  338. #define XD_NORMAL_READ 0x07
  339. #define XD_WRITE_PAGES 0x08
  340. #define XD_NORMAL_WRITE 0x09
  341. #define XD_WRITE_REDUNDANT 0x0A
  342. #define XD_SET_ADDR 0x0B
  343. #define XD_PPB_TO_SIE 0x80
  344. #define XD_TO_PPB_ONLY 0x00
  345. #define XD_BA_TRANSFORM 0x40
  346. #define XD_BA_NO_TRANSFORM 0x00
  347. #define XD_NO_CALC_ECC 0x20
  348. #define XD_CALC_ECC 0x00
  349. #define XD_IGNORE_ECC 0x10
  350. #define XD_CHECK_ECC 0x00
  351. #define XD_DIRECT_TO_RB 0x08
  352. #define XD_ADDR_LENGTH_0 0x00
  353. #define XD_ADDR_LENGTH_1 0x01
  354. #define XD_ADDR_LENGTH_2 0x02
  355. #define XD_ADDR_LENGTH_3 0x03
  356. #define XD_ADDR_LENGTH_4 0x04
  357. #define XD_GPG 0xFF
  358. #define XD_BPG 0x00
  359. #define XD_GBLK 0xFF
  360. #define XD_LATER_BBLK 0xF0
  361. #define XD_ECC2_ALL1 0x80
  362. #define XD_ECC1_ALL1 0x40
  363. #define XD_BA2_ALL0 0x20
  364. #define XD_BA1_ALL0 0x10
  365. #define XD_BA1_BA2_EQL 0x04
  366. #define XD_BA2_VALID 0x02
  367. #define XD_BA1_VALID 0x01
  368. #define XD_PGSTS_ZEROBIT_OVER4 0x00
  369. #define XD_PGSTS_NOT_FF 0x02
  370. #define XD_AUTO_CHK_DATA_STATUS 0x01
  371. #define RSTB_MODE_DETECT 0x80
  372. #define MODE_OUT_VLD 0x40
  373. #define MODE_OUT_0_NONE 0x00
  374. #define MODE_OUT_10_NONE 0x04
  375. #define MODE_OUT_10_47 0x05
  376. #define MODE_OUT_10_180 0x06
  377. #define MODE_OUT_10_680 0x07
  378. #define MODE_OUT_16_NONE 0x08
  379. #define MODE_OUT_16_47 0x09
  380. #define MODE_OUT_16_180 0x0A
  381. #define MODE_OUT_16_680 0x0B
  382. #define MODE_OUT_NONE_NONE 0x0C
  383. #define MODE_OUT_NONE_47 0x0D
  384. #define MODE_OUT_NONE_180 0x0E
  385. #define MODE_OUT_NONE_680 0x0F
  386. #define CARD_OC_INT_EN 0x20
  387. #define CARD_DETECT_EN 0x08
  388. #define MS_DETECT_EN 0x80
  389. #define MS_OCP_INT_EN 0x40
  390. #define MS_OCP_INT_CLR 0x20
  391. #define MS_OC_CLR 0x10
  392. #define SD_DETECT_EN 0x08
  393. #define SD_OCP_INT_EN 0x04
  394. #define SD_OCP_INT_CLR 0x02
  395. #define SD_OC_CLR 0x01
  396. #define CARD_OCP_DETECT 0x80
  397. #define CARD_OC_NOW 0x08
  398. #define CARD_OC_EVER 0x04
  399. #define MS_OCP_DETECT 0x80
  400. #define MS_OC_NOW 0x40
  401. #define MS_OC_EVER 0x20
  402. #define SD_OCP_DETECT 0x08
  403. #define SD_OC_NOW 0x04
  404. #define SD_OC_EVER 0x02
  405. #define CARD_OC_INT_CLR 0x08
  406. #define CARD_OC_CLR 0x02
  407. #define SD_OCP_GLITCH_MASK 0x07
  408. #define SD_OCP_GLITCH_6_4 0x00
  409. #define SD_OCP_GLITCH_64 0x01
  410. #define SD_OCP_GLITCH_640 0x02
  411. #define SD_OCP_GLITCH_1000 0x03
  412. #define SD_OCP_GLITCH_2000 0x04
  413. #define SD_OCP_GLITCH_4000 0x05
  414. #define SD_OCP_GLITCH_8000 0x06
  415. #define SD_OCP_GLITCH_10000 0x07
  416. #define MS_OCP_GLITCH_MASK 0x70
  417. #define MS_OCP_GLITCH_6_4 (0x00 << 4)
  418. #define MS_OCP_GLITCH_64 (0x01 << 4)
  419. #define MS_OCP_GLITCH_640 (0x02 << 4)
  420. #define MS_OCP_GLITCH_1000 (0x03 << 4)
  421. #define MS_OCP_GLITCH_2000 (0x04 << 4)
  422. #define MS_OCP_GLITCH_4000 (0x05 << 4)
  423. #define MS_OCP_GLITCH_8000 (0x06 << 4)
  424. #define MS_OCP_GLITCH_10000 (0x07 << 4)
  425. #define OCP_TIME_60 0x00
  426. #define OCP_TIME_100 (0x01 << 3)
  427. #define OCP_TIME_200 (0x02 << 3)
  428. #define OCP_TIME_400 (0x03 << 3)
  429. #define OCP_TIME_600 (0x04 << 3)
  430. #define OCP_TIME_800 (0x05 << 3)
  431. #define OCP_TIME_1100 (0x06 << 3)
  432. #define OCP_TIME_MASK 0x38
  433. #define MS_OCP_TIME_60 0x00
  434. #define MS_OCP_TIME_100 (0x01 << 4)
  435. #define MS_OCP_TIME_200 (0x02 << 4)
  436. #define MS_OCP_TIME_400 (0x03 << 4)
  437. #define MS_OCP_TIME_600 (0x04 << 4)
  438. #define MS_OCP_TIME_800 (0x05 << 4)
  439. #define MS_OCP_TIME_1100 (0x06 << 4)
  440. #define MS_OCP_TIME_MASK 0x70
  441. #define SD_OCP_TIME_60 0x00
  442. #define SD_OCP_TIME_100 0x01
  443. #define SD_OCP_TIME_200 0x02
  444. #define SD_OCP_TIME_400 0x03
  445. #define SD_OCP_TIME_600 0x04
  446. #define SD_OCP_TIME_800 0x05
  447. #define SD_OCP_TIME_1100 0x06
  448. #define SD_OCP_TIME_MASK 0x07
  449. #define OCP_THD_315_417 0x00
  450. #define OCP_THD_283_783 (0x01 << 6)
  451. #define OCP_THD_244_946 (0x02 << 6)
  452. #define OCP_THD_191_1080 (0x03 << 6)
  453. #define OCP_THD_MASK 0xC0
  454. #define MS_OCP_THD_450 0x00
  455. #define MS_OCP_THD_550 (0x01 << 4)
  456. #define MS_OCP_THD_650 (0x02 << 4)
  457. #define MS_OCP_THD_750 (0x03 << 4)
  458. #define MS_OCP_THD_850 (0x04 << 4)
  459. #define MS_OCP_THD_950 (0x05 << 4)
  460. #define MS_OCP_THD_1050 (0x06 << 4)
  461. #define MS_OCP_THD_1150 (0x07 << 4)
  462. #define MS_OCP_THD_MASK 0x70
  463. #define SD_OCP_THD_450 0x00
  464. #define SD_OCP_THD_550 0x01
  465. #define SD_OCP_THD_650 0x02
  466. #define SD_OCP_THD_750 0x03
  467. #define SD_OCP_THD_850 0x04
  468. #define SD_OCP_THD_950 0x05
  469. #define SD_OCP_THD_1050 0x06
  470. #define SD_OCP_THD_1150 0x07
  471. #define SD_OCP_THD_MASK 0x07
  472. #define FPGA_MS_PULL_CTL_EN 0xEF
  473. #define FPGA_SD_PULL_CTL_EN 0xF7
  474. #define FPGA_XD_PULL_CTL_EN1 0xFE
  475. #define FPGA_XD_PULL_CTL_EN2 0xFD
  476. #define FPGA_XD_PULL_CTL_EN3 0xFB
  477. #define FPGA_MS_PULL_CTL_BIT 0x10
  478. #define FPGA_SD_PULL_CTL_BIT 0x08
  479. #define BLINK_EN 0x08
  480. #define LED_GPIO0 (0 << 4)
  481. #define LED_GPIO1 (1 << 4)
  482. #define LED_GPIO2 (2 << 4)
  483. #define SDIO_BUS_CTRL 0x01
  484. #define SDIO_CD_CTRL 0x02
  485. #define SSC_RSTB 0x80
  486. #define SSC_8X_EN 0x40
  487. #define SSC_FIX_FRAC 0x20
  488. #define SSC_SEL_1M 0x00
  489. #define SSC_SEL_2M 0x08
  490. #define SSC_SEL_4M 0x10
  491. #define SSC_SEL_8M 0x18
  492. #define SSC_DEPTH_MASK 0x07
  493. #define SSC_DEPTH_DISALBE 0x00
  494. #define SSC_DEPTH_4M 0x01
  495. #define SSC_DEPTH_2M 0x02
  496. #define SSC_DEPTH_1M 0x03
  497. #define SSC_DEPTH_512K 0x04
  498. #define SSC_DEPTH_256K 0x05
  499. #define SSC_DEPTH_128K 0x06
  500. #define SSC_DEPTH_64K 0x07
  501. #define XD_D3_NP 0x00
  502. #define XD_D3_PD (0x01 << 6)
  503. #define XD_D3_PU (0x02 << 6)
  504. #define XD_D2_NP 0x00
  505. #define XD_D2_PD (0x01 << 4)
  506. #define XD_D2_PU (0x02 << 4)
  507. #define XD_D1_NP 0x00
  508. #define XD_D1_PD (0x01 << 2)
  509. #define XD_D1_PU (0x02 << 2)
  510. #define XD_D0_NP 0x00
  511. #define XD_D0_PD 0x01
  512. #define XD_D0_PU 0x02
  513. #define SD_D7_NP 0x00
  514. #define SD_D7_PD (0x01 << 4)
  515. #define SD_DAT7_PU (0x02 << 4)
  516. #define SD_CLK_NP 0x00
  517. #define SD_CLK_PD (0x01 << 2)
  518. #define SD_CLK_PU (0x02 << 2)
  519. #define SD_D5_NP 0x00
  520. #define SD_D5_PD 0x01
  521. #define SD_D5_PU 0x02
  522. #define MS_D1_NP 0x00
  523. #define MS_D1_PD (0x01 << 6)
  524. #define MS_D1_PU (0x02 << 6)
  525. #define MS_D2_NP 0x00
  526. #define MS_D2_PD (0x01 << 4)
  527. #define MS_D2_PU (0x02 << 4)
  528. #define MS_CLK_NP 0x00
  529. #define MS_CLK_PD (0x01 << 2)
  530. #define MS_CLK_PU (0x02 << 2)
  531. #define MS_D6_NP 0x00
  532. #define MS_D6_PD 0x01
  533. #define MS_D6_PU 0x02
  534. #define XD_D7_NP 0x00
  535. #define XD_D7_PD (0x01 << 6)
  536. #define XD_D7_PU (0x02 << 6)
  537. #define XD_D6_NP 0x00
  538. #define XD_D6_PD (0x01 << 4)
  539. #define XD_D6_PU (0x02 << 4)
  540. #define XD_D5_NP 0x00
  541. #define XD_D5_PD (0x01 << 2)
  542. #define XD_D5_PU (0x02 << 2)
  543. #define XD_D4_NP 0x00
  544. #define XD_D4_PD 0x01
  545. #define XD_D4_PU 0x02
  546. #define SD_D6_NP 0x00
  547. #define SD_D6_PD (0x01 << 6)
  548. #define SD_D6_PU (0x02 << 6)
  549. #define SD_D0_NP 0x00
  550. #define SD_D0_PD (0x01 << 4)
  551. #define SD_D0_PU (0x02 << 4)
  552. #define SD_D1_NP 0x00
  553. #define SD_D1_PD 0x01
  554. #define SD_D1_PU 0x02
  555. #define MS_D3_NP 0x00
  556. #define MS_D3_PD (0x01 << 6)
  557. #define MS_D3_PU (0x02 << 6)
  558. #define MS_D0_NP 0x00
  559. #define MS_D0_PD (0x01 << 4)
  560. #define MS_D0_PU (0x02 << 4)
  561. #define MS_BS_NP 0x00
  562. #define MS_BS_PD (0x01 << 2)
  563. #define MS_BS_PU (0x02 << 2)
  564. #define XD_WP_NP 0x00
  565. #define XD_WP_PD (0x01 << 6)
  566. #define XD_WP_PU (0x02 << 6)
  567. #define XD_CE_NP 0x00
  568. #define XD_CE_PD (0x01 << 3)
  569. #define XD_CE_PU (0x02 << 3)
  570. #define XD_CLE_NP 0x00
  571. #define XD_CLE_PD (0x01 << 1)
  572. #define XD_CLE_PU (0x02 << 1)
  573. #define XD_CD_PD 0x00
  574. #define XD_CD_PU 0x01
  575. #define SD_D4_NP 0x00
  576. #define SD_D4_PD (0x01 << 6)
  577. #define SD_D4_PU (0x02 << 6)
  578. #define MS_D7_NP 0x00
  579. #define MS_D7_PD (0x01 << 6)
  580. #define MS_D7_PU (0x02 << 6)
  581. #define XD_RDY_NP 0x00
  582. #define XD_RDY_PD (0x01 << 6)
  583. #define XD_RDY_PU (0x02 << 6)
  584. #define XD_WE_NP 0x00
  585. #define XD_WE_PD (0x01 << 4)
  586. #define XD_WE_PU (0x02 << 4)
  587. #define XD_RE_NP 0x00
  588. #define XD_RE_PD (0x01 << 2)
  589. #define XD_RE_PU (0x02 << 2)
  590. #define XD_ALE_NP 0x00
  591. #define XD_ALE_PD 0x01
  592. #define XD_ALE_PU 0x02
  593. #define SD_D3_NP 0x00
  594. #define SD_D3_PD (0x01 << 4)
  595. #define SD_D3_PU (0x02 << 4)
  596. #define SD_D2_NP 0x00
  597. #define SD_D2_PD (0x01 << 2)
  598. #define SD_D2_PU (0x02 << 2)
  599. #define MS_INS_PD 0x00
  600. #define MS_INS_PU (0x01 << 7)
  601. #define SD_WP_NP 0x00
  602. #define SD_WP_PD (0x01 << 5)
  603. #define SD_WP_PU (0x02 << 5)
  604. #define SD_CD_PD 0x00
  605. #define SD_CD_PU (0x01 << 4)
  606. #define SD_CMD_NP 0x00
  607. #define SD_CMD_PD (0x01 << 2)
  608. #define SD_CMD_PU (0x02 << 2)
  609. #define MS_D5_NP 0x00
  610. #define MS_D5_PD (0x01 << 2)
  611. #define MS_D5_PU (0x02 << 2)
  612. #define MS_D4_NP 0x00
  613. #define MS_D4_PD 0x01
  614. #define MS_D4_PU 0x02
  615. #define FORCE_PM_CLOCK 0x10
  616. #define EN_CLOCK_PM 0x01
  617. #define HOST_ENTER_S3 0x02
  618. #define HOST_ENTER_S1 0x01
  619. #define AUX_PWR_DETECTED 0x01
  620. #define PHY_DEBUG_MODE 0x01
  621. #define SPI_COMMAND_BIT_8 0xE0
  622. #define SPI_ADDRESS_BIT_24 0x17
  623. #define SPI_ADDRESS_BIT_32 0x1F
  624. #define SPI_TRANSFER0_START 0x80
  625. #define SPI_TRANSFER0_END 0x40
  626. #define SPI_C_MODE0 0x00
  627. #define SPI_CA_MODE0 0x01
  628. #define SPI_CDO_MODE0 0x02
  629. #define SPI_CDI_MODE0 0x03
  630. #define SPI_CADO_MODE0 0x04
  631. #define SPI_CADI_MODE0 0x05
  632. #define SPI_POLLING_MODE0 0x06
  633. #define SPI_TRANSFER1_START 0x80
  634. #define SPI_TRANSFER1_END 0x40
  635. #define SPI_DO_MODE1 0x00
  636. #define SPI_DI_MODE1 0x01
  637. #define CS_POLARITY_HIGH 0x40
  638. #define CS_POLARITY_LOW 0x00
  639. #define DTO_MSB_FIRST 0x00
  640. #define DTO_LSB_FIRST 0x20
  641. #define SPI_MASTER 0x00
  642. #define SPI_SLAVE 0x10
  643. #define SPI_MODE0 0x00
  644. #define SPI_MODE1 0x04
  645. #define SPI_MODE2 0x08
  646. #define SPI_MODE3 0x0C
  647. #define SPI_MANUAL 0x00
  648. #define SPI_HALF_AUTO 0x01
  649. #define SPI_AUTO 0x02
  650. #define SPI_EEPROM_AUTO 0x03
  651. #define EDO_TIMING_MASK 0x03
  652. #define SAMPLE_RISING 0x00
  653. #define SAMPLE_DELAY_HALF 0x01
  654. #define SAMPLE_DELAY_ONE 0x02
  655. #define SAPMLE_DELAY_ONE_HALF 0x03
  656. #define TCS_MASK 0x0C
  657. #define NOT_BYPASS_SD 0x02
  658. #define DISABLE_SDIO_FUNC 0x04
  659. #define SELECT_1LUN 0x08
  660. #define PWR_GATE_EN 0x01
  661. #define LDO3318_PWR_MASK 0x06
  662. #define LDO_ON 0x00
  663. #define LDO_SUSPEND 0x04
  664. #define LDO_OFF 0x06
  665. #define SD_CFG1 0xFDA0
  666. #define SD_CFG2 0xFDA1
  667. #define SD_CFG3 0xFDA2
  668. #define SD_STAT1 0xFDA3
  669. #define SD_STAT2 0xFDA4
  670. #define SD_BUS_STAT 0xFDA5
  671. #define SD_PAD_CTL 0xFDA6
  672. #define SD_SAMPLE_POINT_CTL 0xFDA7
  673. #define SD_PUSH_POINT_CTL 0xFDA8
  674. #define SD_CMD0 0xFDA9
  675. #define SD_CMD1 0xFDAA
  676. #define SD_CMD2 0xFDAB
  677. #define SD_CMD3 0xFDAC
  678. #define SD_CMD4 0xFDAD
  679. #define SD_CMD5 0xFDAE
  680. #define SD_BYTE_CNT_L 0xFDAF
  681. #define SD_BYTE_CNT_H 0xFDB0
  682. #define SD_BLOCK_CNT_L 0xFDB1
  683. #define SD_BLOCK_CNT_H 0xFDB2
  684. #define SD_TRANSFER 0xFDB3
  685. #define SD_CMD_STATE 0xFDB5
  686. #define SD_DATA_STATE 0xFDB6
  687. #define DCM_DRP_CTL 0xFC23
  688. #define DCM_DRP_TRIG 0xFC24
  689. #define DCM_DRP_CFG 0xFC25
  690. #define DCM_DRP_WR_DATA_L 0xFC26
  691. #define DCM_DRP_WR_DATA_H 0xFC27
  692. #define DCM_DRP_RD_DATA_L 0xFC28
  693. #define DCM_DRP_RD_DATA_H 0xFC29
  694. #define SD_VPCLK0_CTL 0xFC2A
  695. #define SD_VPCLK1_CTL 0xFC2B
  696. #define SD_DCMPS0_CTL 0xFC2C
  697. #define SD_DCMPS1_CTL 0xFC2D
  698. #define SD_VPTX_CTL SD_VPCLK0_CTL
  699. #define SD_VPRX_CTL SD_VPCLK1_CTL
  700. #define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
  701. #define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
  702. #define CARD_CLK_SOURCE 0xFC2E
  703. #define CARD_PWR_CTL 0xFD50
  704. #define CARD_CLK_SWITCH 0xFD51
  705. #define CARD_SHARE_MODE 0xFD52
  706. #define CARD_DRIVE_SEL 0xFD53
  707. #define CARD_STOP 0xFD54
  708. #define CARD_OE 0xFD55
  709. #define CARD_AUTO_BLINK 0xFD56
  710. #define CARD_GPIO_DIR 0xFD57
  711. #define CARD_GPIO 0xFD58
  712. #define CARD_DATA_SOURCE 0xFD5B
  713. #define CARD_SELECT 0xFD5C
  714. #define SD30_DRIVE_SEL 0xFD5E
  715. #define CARD_CLK_EN 0xFD69
  716. #define SDIO_CTRL 0xFD6B
  717. #define FPDCTL 0xFC00
  718. #define PDINFO 0xFC01
  719. #define CLK_CTL 0xFC02
  720. #define CLK_DIV 0xFC03
  721. #define CLK_SEL 0xFC04
  722. #define SSC_DIV_N_0 0xFC0F
  723. #define SSC_DIV_N_1 0xFC10
  724. #define RCCTL 0xFC14
  725. #define FPGA_PULL_CTL 0xFC1D
  726. #define CARD_PULL_CTL1 0xFD60
  727. #define CARD_PULL_CTL2 0xFD61
  728. #define CARD_PULL_CTL3 0xFD62
  729. #define CARD_PULL_CTL4 0xFD63
  730. #define CARD_PULL_CTL5 0xFD64
  731. #define CARD_PULL_CTL6 0xFD65
  732. #define IRQEN0 0xFE20
  733. #define IRQSTAT0 0xFE21
  734. #define IRQEN1 0xFE22
  735. #define IRQSTAT1 0xFE23
  736. #define TLPRIEN 0xFE24
  737. #define TLPRISTAT 0xFE25
  738. #define TLPTIEN 0xFE26
  739. #define TLPTISTAT 0xFE27
  740. #define DMATC0 0xFE28
  741. #define DMATC1 0xFE29
  742. #define DMATC2 0xFE2A
  743. #define DMATC3 0xFE2B
  744. #define DMACTL 0xFE2C
  745. #define BCTL 0xFE2D
  746. #define RBBC0 0xFE2E
  747. #define RBBC1 0xFE2F
  748. #define RBDAT 0xFE30
  749. #define RBCTL 0xFE34
  750. #define CFGADDR0 0xFE35
  751. #define CFGADDR1 0xFE36
  752. #define CFGDATA0 0xFE37
  753. #define CFGDATA1 0xFE38
  754. #define CFGDATA2 0xFE39
  755. #define CFGDATA3 0xFE3A
  756. #define CFGRWCTL 0xFE3B
  757. #define PHYRWCTL 0xFE3C
  758. #define PHYDATA0 0xFE3D
  759. #define PHYDATA1 0xFE3E
  760. #define PHYADDR 0xFE3F
  761. #define MSGRXDATA0 0xFE40
  762. #define MSGRXDATA1 0xFE41
  763. #define MSGRXDATA2 0xFE42
  764. #define MSGRXDATA3 0xFE43
  765. #define MSGTXDATA0 0xFE44
  766. #define MSGTXDATA1 0xFE45
  767. #define MSGTXDATA2 0xFE46
  768. #define MSGTXDATA3 0xFE47
  769. #define MSGTXCTL 0xFE48
  770. #define PETXCFG 0xFE49
  771. #define CDRESUMECTL 0xFE52
  772. #define WAKE_SEL_CTL 0xFE54
  773. #define PME_FORCE_CTL 0xFE56
  774. #define ASPM_FORCE_CTL 0xFE57
  775. #define PM_CLK_FORCE_CTL 0xFE58
  776. #define PERST_GLITCH_WIDTH 0xFE5C
  777. #define CHANGE_LINK_STATE 0xFE5B
  778. #define RESET_LOAD_REG 0xFE5E
  779. #define HOST_SLEEP_STATE 0xFE60
  780. #define MAIN_PWR_OFF_CTL 0xFE70 /* RTS5208 */
  781. #define SDIO_CFG 0xFE70 /* RTS5209 */
  782. #define NFTS_TX_CTRL 0xFE72
  783. #define PWR_GATE_CTRL 0xFE75
  784. #define PWD_SUSPEND_EN 0xFE76
  785. #define EFUSE_CONTENT 0xFE5F
  786. #define XD_INIT 0xFD10
  787. #define XD_DTCTL 0xFD11
  788. #define XD_CTL 0xFD12
  789. #define XD_TRANSFER 0xFD13
  790. #define XD_CFG 0xFD14
  791. #define XD_ADDRESS0 0xFD15
  792. #define XD_ADDRESS1 0xFD16
  793. #define XD_ADDRESS2 0xFD17
  794. #define XD_ADDRESS3 0xFD18
  795. #define XD_ADDRESS4 0xFD19
  796. #define XD_DAT 0xFD1A
  797. #define XD_PAGE_CNT 0xFD1B
  798. #define XD_PAGE_STATUS 0xFD1C
  799. #define XD_BLOCK_STATUS 0xFD1D
  800. #define XD_BLOCK_ADDR1_L 0xFD1E
  801. #define XD_BLOCK_ADDR1_H 0xFD1F
  802. #define XD_BLOCK_ADDR2_L 0xFD20
  803. #define XD_BLOCK_ADDR2_H 0xFD21
  804. #define XD_BYTE_CNT_L 0xFD22
  805. #define XD_BYTE_CNT_H 0xFD23
  806. #define XD_PARITY 0xFD24
  807. #define XD_ECC_BIT1 0xFD25
  808. #define XD_ECC_BYTE1 0xFD26
  809. #define XD_ECC_BIT2 0xFD27
  810. #define XD_ECC_BYTE2 0xFD28
  811. #define XD_RESERVED0 0xFD29
  812. #define XD_RESERVED1 0xFD2A
  813. #define XD_RESERVED2 0xFD2B
  814. #define XD_RESERVED3 0xFD2C
  815. #define XD_CHK_DATA_STATUS 0xFD2D
  816. #define XD_CATCTL 0xFD2E
  817. #define MS_CFG 0xFD40
  818. #define MS_TPC 0xFD41
  819. #define MS_TRANS_CFG 0xFD42
  820. #define MS_TRANSFER 0xFD43
  821. #define MS_INT_REG 0xFD44
  822. #define MS_BYTE_CNT 0xFD45
  823. #define MS_SECTOR_CNT_L 0xFD46
  824. #define MS_SECTOR_CNT_H 0xFD47
  825. #define MS_DBUS_H 0xFD48
  826. #define SSC_CTL1 0xFC11
  827. #define SSC_CTL2 0xFC12
  828. #define OCPCTL 0xFC15
  829. #define OCPSTAT 0xFC16
  830. #define OCPCLR 0xFC17 /* 5208 */
  831. #define OCPGLITCH 0xFC17 /* 5209 */
  832. #define OCPPARA1 0xFC18
  833. #define OCPPARA2 0xFC19
  834. #define EFUSE_OP 0xFC20
  835. #define EFUSE_CTRL 0xFC21
  836. #define EFUSE_DATA 0xFC22
  837. #define SPI_COMMAND 0xFD80
  838. #define SPI_ADDR0 0xFD81
  839. #define SPI_ADDR1 0xFD82
  840. #define SPI_ADDR2 0xFD83
  841. #define SPI_ADDR3 0xFD84
  842. #define SPI_CA_NUMBER 0xFD85
  843. #define SPI_LENGTH0 0xFD86
  844. #define SPI_LENGTH1 0xFD87
  845. #define SPI_DATA 0xFD88
  846. #define SPI_DATA_NUMBER 0xFD89
  847. #define SPI_TRANSFER0 0xFD90
  848. #define SPI_TRANSFER1 0xFD91
  849. #define SPI_CONTROL 0xFD92
  850. #define SPI_SIG 0xFD93
  851. #define SPI_TCTL 0xFD94
  852. #define SPI_SLAVE_NUM 0xFD95
  853. #define SPI_CLK_DIVIDER0 0xFD96
  854. #define SPI_CLK_DIVIDER1 0xFD97
  855. #define SRAM_BASE 0xE600
  856. #define RBUF_BASE 0xF400
  857. #define PPBUF_BASE1 0xF800
  858. #define PPBUF_BASE2 0xFA00
  859. #define IMAGE_FLAG_ADDR0 0xCE80
  860. #define IMAGE_FLAG_ADDR1 0xCE81
  861. #define READ_OP 1
  862. #define WRITE_OP 2
  863. #define LCTLR 0x80
  864. #define POLLING_WAIT_CNT 1
  865. #define IDLE_MAX_COUNT 10
  866. #define SDIO_IDLE_COUNT 10
  867. #define DEBOUNCE_CNT 5
  868. void do_remaining_work(struct rtsx_chip *chip);
  869. void try_to_switch_sdio_ctrl(struct rtsx_chip *chip);
  870. void do_reset_sd_card(struct rtsx_chip *chip);
  871. void do_reset_xd_card(struct rtsx_chip *chip);
  872. void do_reset_ms_card(struct rtsx_chip *chip);
  873. void rtsx_power_off_card(struct rtsx_chip *chip);
  874. void rtsx_release_cards(struct rtsx_chip *chip);
  875. void rtsx_reset_cards(struct rtsx_chip *chip);
  876. void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip);
  877. void rtsx_init_cards(struct rtsx_chip *chip);
  878. int switch_ssc_clock(struct rtsx_chip *chip, int clk);
  879. int switch_normal_clock(struct rtsx_chip *chip, int clk);
  880. int enable_card_clock(struct rtsx_chip *chip, u8 card);
  881. int disable_card_clock(struct rtsx_chip *chip, u8 card);
  882. int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 sec_addr, u16 sec_cnt);
  883. void trans_dma_enable(enum dma_data_direction dir, struct rtsx_chip *chip, u32 byte_cnt, u8 pack_size);
  884. void toggle_gpio(struct rtsx_chip *chip, u8 gpio);
  885. void turn_on_led(struct rtsx_chip *chip, u8 gpio);
  886. void turn_off_led(struct rtsx_chip *chip, u8 gpio);
  887. int card_share_mode(struct rtsx_chip *chip, int card);
  888. int select_card(struct rtsx_chip *chip, int card);
  889. int detect_card_cd(struct rtsx_chip *chip, int card);
  890. int check_card_exist(struct rtsx_chip *chip, unsigned int lun);
  891. int check_card_ready(struct rtsx_chip *chip, unsigned int lun);
  892. int check_card_wp(struct rtsx_chip *chip, unsigned int lun);
  893. int check_card_fail(struct rtsx_chip *chip, unsigned int lun);
  894. int check_card_ejected(struct rtsx_chip *chip, unsigned int lun);
  895. void eject_card(struct rtsx_chip *chip, unsigned int lun);
  896. u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun);
  897. static inline u32 get_card_size(struct rtsx_chip *chip, unsigned int lun)
  898. {
  899. #ifdef SUPPORT_SD_LOCK
  900. struct sd_info *sd_card = &(chip->sd_card);
  901. if ((get_lun_card(chip, lun) == SD_CARD) && (sd_card->sd_lock_status & SD_LOCKED))
  902. return 0;
  903. else
  904. return chip->capacity[lun];
  905. #else
  906. return chip->capacity[lun];
  907. #endif
  908. }
  909. static inline int switch_clock(struct rtsx_chip *chip, int clk)
  910. {
  911. int retval = 0;
  912. if (chip->asic_code)
  913. retval = switch_ssc_clock(chip, clk);
  914. else
  915. retval = switch_normal_clock(chip, clk);
  916. return retval;
  917. }
  918. int card_power_on(struct rtsx_chip *chip, u8 card);
  919. int card_power_off(struct rtsx_chip *chip, u8 card);
  920. static inline int card_power_off_all(struct rtsx_chip *chip)
  921. {
  922. RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0x0F, 0x0F);
  923. return STATUS_SUCCESS;
  924. }
  925. static inline void rtsx_clear_xd_error(struct rtsx_chip *chip)
  926. {
  927. rtsx_write_register(chip, CARD_STOP, XD_STOP | XD_CLR_ERR, XD_STOP | XD_CLR_ERR);
  928. }
  929. static inline void rtsx_clear_sd_error(struct rtsx_chip *chip)
  930. {
  931. rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
  932. }
  933. static inline void rtsx_clear_ms_error(struct rtsx_chip *chip)
  934. {
  935. rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR);
  936. }
  937. static inline void rtsx_clear_spi_error(struct rtsx_chip *chip)
  938. {
  939. rtsx_write_register(chip, CARD_STOP, SPI_STOP | SPI_CLR_ERR, SPI_STOP | SPI_CLR_ERR);
  940. }
  941. #ifdef SUPPORT_SDIO_ASPM
  942. void dynamic_configure_sdio_aspm(struct rtsx_chip *chip);
  943. #endif
  944. #endif /* __REALTEK_RTSX_CARD_H */