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/drivers/staging/rts_pstor/rtsx_card.h

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C Header | 1093 lines | 922 code | 149 blank | 22 comment | 4 complexity | 58f9dbbdd1c572d2a41abdc348ec0196 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
   1/* Driver for Realtek PCI-Express card reader
   2 * Header file
   3 *
   4 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of the GNU General Public License as published by the
   8 * Free Software Foundation; either version 2, or (at your option) any
   9 * later version.
  10 *
  11 * This program is distributed in the hope that it will be useful, but
  12 * WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License along
  17 * with this program; if not, see <http://www.gnu.org/licenses/>.
  18 *
  19 * Author:
  20 *   wwang (wei_wang@realsil.com.cn)
  21 *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  22 */
  23
  24#ifndef __REALTEK_RTSX_CARD_H
  25#define __REALTEK_RTSX_CARD_H
  26
  27#include "debug.h"
  28#include "rtsx.h"
  29#include "rtsx_chip.h"
  30#include "rtsx_transport.h"
  31#include "sd.h"
  32
  33#define SSC_POWER_DOWN		0x01
  34#define SD_OC_POWER_DOWN	0x02
  35#define MS_OC_POWER_DOWN	0x04
  36#define ALL_POWER_DOWN		0x07
  37#define OC_POWER_DOWN		0x06
  38
  39#define PMOS_STRG_MASK		0x10
  40#define PMOS_STRG_800mA		0x10
  41#define PMOS_STRG_400mA		0x00
  42
  43#define POWER_OFF		0x03
  44#define PARTIAL_POWER_ON	0x01
  45#define POWER_ON		0x00
  46
  47#define MS_POWER_OFF		0x0C
  48#define MS_PARTIAL_POWER_ON	0x04
  49#define MS_POWER_ON		0x00
  50#define MS_POWER_MASK		0x0C
  51
  52#define SD_POWER_OFF		0x03
  53#define SD_PARTIAL_POWER_ON	0x01
  54#define SD_POWER_ON		0x00
  55#define SD_POWER_MASK		0x03
  56
  57#define XD_OUTPUT_EN		0x02
  58#define SD_OUTPUT_EN		0x04
  59#define MS_OUTPUT_EN		0x08
  60#define SPI_OUTPUT_EN		0x10
  61
  62#define CLK_LOW_FREQ		0x01
  63
  64#define CLK_DIV_1		0x01
  65#define CLK_DIV_2		0x02
  66#define CLK_DIV_4		0x03
  67#define CLK_DIV_8		0x04
  68
  69#define SSC_80			0
  70#define SSC_100			1
  71#define SSC_120			2
  72#define SSC_150			3
  73#define SSC_200			4
  74
  75#define XD_CLK_EN		0x02
  76#define SD_CLK_EN		0x04
  77#define MS_CLK_EN		0x08
  78#define SPI_CLK_EN		0x10
  79
  80#define XD_MOD_SEL		1
  81#define SD_MOD_SEL		2
  82#define MS_MOD_SEL		3
  83#define SPI_MOD_SEL		4
  84
  85#define CHANGE_CLK		0x01
  86
  87#define	SD_CRC7_ERR			0x80
  88#define	SD_CRC16_ERR			0x40
  89#define	SD_CRC_WRITE_ERR		0x20
  90#define	SD_CRC_WRITE_ERR_MASK	    	0x1C
  91#define	GET_CRC_TIME_OUT		0x02
  92#define	SD_TUNING_COMPARE_ERR		0x01
  93
  94#define	SD_RSP_80CLK_TIMEOUT		0x01
  95
  96#define	SD_CLK_TOGGLE_EN		0x80
  97#define	SD_CLK_FORCE_STOP	        0x40
  98#define	SD_DAT3_STATUS		        0x10
  99#define	SD_DAT2_STATUS		        0x08
 100#define	SD_DAT1_STATUS		        0x04
 101#define	SD_DAT0_STATUS		        0x02
 102#define	SD_CMD_STATUS			0x01
 103
 104#define	SD_IO_USING_1V8		        0x80
 105#define	SD_IO_USING_3V3		        0x7F
 106#define	TYPE_A_DRIVING		        0x00
 107#define	TYPE_B_DRIVING			0x01
 108#define	TYPE_C_DRIVING			0x02
 109#define	TYPE_D_DRIVING		        0x03
 110
 111#define	DDR_FIX_RX_DAT			0x00
 112#define	DDR_VAR_RX_DAT			0x80
 113#define	DDR_FIX_RX_DAT_EDGE		0x00
 114#define	DDR_FIX_RX_DAT_14_DELAY		0x40
 115#define	DDR_FIX_RX_CMD			0x00
 116#define	DDR_VAR_RX_CMD			0x20
 117#define	DDR_FIX_RX_CMD_POS_EDGE		0x00
 118#define	DDR_FIX_RX_CMD_14_DELAY		0x10
 119#define	SD20_RX_POS_EDGE		0x00
 120#define	SD20_RX_14_DELAY		0x08
 121#define SD20_RX_SEL_MASK		0x08
 122
 123#define	DDR_FIX_TX_CMD_DAT		0x00
 124#define	DDR_VAR_TX_CMD_DAT		0x80
 125#define	DDR_FIX_TX_DAT_14_TSU		0x00
 126#define	DDR_FIX_TX_DAT_12_TSU		0x40
 127#define	DDR_FIX_TX_CMD_NEG_EDGE		0x00
 128#define	DDR_FIX_TX_CMD_14_AHEAD		0x20
 129#define	SD20_TX_NEG_EDGE		0x00
 130#define	SD20_TX_14_AHEAD		0x10
 131#define SD20_TX_SEL_MASK		0x10
 132#define	DDR_VAR_SDCLK_POL_SWAP		0x01
 133
 134#define	SD_TRANSFER_START		0x80
 135#define	SD_TRANSFER_END			0x40
 136#define SD_STAT_IDLE			0x20
 137#define	SD_TRANSFER_ERR			0x10
 138#define	SD_TM_NORMAL_WRITE		0x00
 139#define	SD_TM_AUTO_WRITE_3		0x01
 140#define	SD_TM_AUTO_WRITE_4		0x02
 141#define	SD_TM_AUTO_READ_3		0x05
 142#define	SD_TM_AUTO_READ_4		0x06
 143#define	SD_TM_CMD_RSP			0x08
 144#define	SD_TM_AUTO_WRITE_1		0x09
 145#define	SD_TM_AUTO_WRITE_2		0x0A
 146#define	SD_TM_NORMAL_READ		0x0C
 147#define	SD_TM_AUTO_READ_1		0x0D
 148#define	SD_TM_AUTO_READ_2		0x0E
 149#define	SD_TM_AUTO_TUNING		0x0F
 150
 151#define PHASE_CHANGE			0x80
 152#define PHASE_NOT_RESET			0x40
 153
 154#define DCMPS_CHANGE			0x80
 155#define DCMPS_CHANGE_DONE	   	0x40
 156#define DCMPS_ERROR			0x20
 157#define DCMPS_CURRENT_PHASE     	0x1F
 158
 159#define SD_CLK_DIVIDE_0			0x00
 160#define	SD_CLK_DIVIDE_256		0xC0
 161#define	SD_CLK_DIVIDE_128		0x80
 162#define	SD_BUS_WIDTH_1			0x00
 163#define	SD_BUS_WIDTH_4			0x01
 164#define	SD_BUS_WIDTH_8			0x02
 165#define	SD_ASYNC_FIFO_NOT_RST		0x10
 166#define	SD_20_MODE			0x00
 167#define	SD_DDR_MODE			0x04
 168#define	SD_30_MODE			0x08
 169
 170#define SD_CLK_DIVIDE_MASK		0xC0
 171
 172#define SD_CMD_IDLE			0x80
 173
 174#define SD_DATA_IDLE			0x80
 175
 176#define DCM_RESET			0x08
 177#define DCM_LOCKED			0x04
 178#define DCM_208M			0x00
 179#define DCM_TX			        0x01
 180#define DCM_RX			        0x02
 181
 182#define DRP_START			0x80
 183#define DRP_DONE			0x40
 184
 185#define DRP_WRITE			0x80
 186#define DRP_READ			0x00
 187#define DCM_WRITE_ADDRESS_50		0x50
 188#define DCM_WRITE_ADDRESS_51		0x51
 189#define DCM_READ_ADDRESS_00		0x00
 190#define DCM_READ_ADDRESS_51		0x51
 191
 192#define	SD_CALCULATE_CRC7		0x00
 193#define	SD_NO_CALCULATE_CRC7		0x80
 194#define	SD_CHECK_CRC16			0x00
 195#define	SD_NO_CHECK_CRC16		0x40
 196#define SD_NO_CHECK_WAIT_CRC_TO		0x20
 197#define	SD_WAIT_BUSY_END		0x08
 198#define	SD_NO_WAIT_BUSY_END		0x00
 199#define	SD_CHECK_CRC7			0x00
 200#define	SD_NO_CHECK_CRC7		0x04
 201#define	SD_RSP_LEN_0			0x00
 202#define	SD_RSP_LEN_6			0x01
 203#define	SD_RSP_LEN_17			0x02
 204#define	SD_RSP_TYPE_R0			0x04
 205#define	SD_RSP_TYPE_R1			0x01
 206#define	SD_RSP_TYPE_R1b			0x09
 207#define	SD_RSP_TYPE_R2			0x02
 208#define	SD_RSP_TYPE_R3			0x05
 209#define	SD_RSP_TYPE_R4			0x05
 210#define	SD_RSP_TYPE_R5			0x01
 211#define	SD_RSP_TYPE_R6			0x01
 212#define	SD_RSP_TYPE_R7			0x01
 213
 214#define	SD_RSP_80CLK_TIMEOUT_EN	   	0x01
 215
 216#define	SAMPLE_TIME_RISING		0x00
 217#define	SAMPLE_TIME_FALLING		0x80
 218#define	PUSH_TIME_DEFAULT		0x00
 219#define	PUSH_TIME_ODD			0x40
 220#define	NO_EXTEND_TOGGLE		0x00
 221#define	EXTEND_TOGGLE_CHK		0x20
 222#define	MS_BUS_WIDTH_1			0x00
 223#define	MS_BUS_WIDTH_4			0x10
 224#define	MS_BUS_WIDTH_8			0x18
 225#define	MS_2K_SECTOR_MODE		0x04
 226#define	MS_512_SECTOR_MODE		0x00
 227#define	MS_TOGGLE_TIMEOUT_EN		0x00
 228#define	MS_TOGGLE_TIMEOUT_DISEN		0x01
 229#define MS_NO_CHECK_INT			0x02
 230
 231#define	WAIT_INT			0x80
 232#define	NO_WAIT_INT			0x00
 233#define	NO_AUTO_READ_INT_REG		0x00
 234#define	AUTO_READ_INT_REG		0x40
 235#define	MS_CRC16_ERR			0x20
 236#define	MS_RDY_TIMEOUT			0x10
 237#define	MS_INT_CMDNK			0x08
 238#define	MS_INT_BREQ			0x04
 239#define	MS_INT_ERR			0x02
 240#define	MS_INT_CED			0x01
 241
 242#define	MS_TRANSFER_START		0x80
 243#define	MS_TRANSFER_END			0x40
 244#define	MS_TRANSFER_ERR			0x20
 245#define	MS_BS_STATE			0x10
 246#define	MS_TM_READ_BYTES		0x00
 247#define	MS_TM_NORMAL_READ		0x01
 248#define	MS_TM_WRITE_BYTES		0x04
 249#define	MS_TM_NORMAL_WRITE		0x05
 250#define	MS_TM_AUTO_READ			0x08
 251#define	MS_TM_AUTO_WRITE		0x0C
 252
 253#define CARD_SHARE_MASK			0x0F
 254#define CARD_SHARE_MULTI_LUN		0x00
 255#define	CARD_SHARE_NORMAL		0x00
 256#define	CARD_SHARE_48_XD		0x02
 257#define	CARD_SHARE_48_SD		0x04
 258#define	CARD_SHARE_48_MS		0x08
 259#define CARD_SHARE_BAROSSA_XD		0x00
 260#define CARD_SHARE_BAROSSA_SD		0x01
 261#define CARD_SHARE_BAROSSA_MS		0x02
 262
 263#define	MS_DRIVE_8			0x00
 264#define	MS_DRIVE_4			0x40
 265#define	MS_DRIVE_12			0x80
 266#define	SD_DRIVE_8			0x00
 267#define	SD_DRIVE_4			0x10
 268#define	SD_DRIVE_12			0x20
 269#define	XD_DRIVE_8			0x00
 270#define	XD_DRIVE_4			0x04
 271#define	XD_DRIVE_12			0x08
 272
 273#define SPI_STOP		0x01
 274#define XD_STOP			0x02
 275#define SD_STOP			0x04
 276#define MS_STOP			0x08
 277#define SPI_CLR_ERR		0x10
 278#define XD_CLR_ERR		0x20
 279#define SD_CLR_ERR		0x40
 280#define MS_CLR_ERR		0x80
 281
 282#define CRC_FIX_CLK		(0x00 << 0)
 283#define CRC_VAR_CLK0		(0x01 << 0)
 284#define CRC_VAR_CLK1		(0x02 << 0)
 285#define SD30_FIX_CLK		(0x00 << 2)
 286#define SD30_VAR_CLK0		(0x01 << 2)
 287#define SD30_VAR_CLK1		(0x02 << 2)
 288#define SAMPLE_FIX_CLK		(0x00 << 4)
 289#define SAMPLE_VAR_CLK0		(0x01 << 4)
 290#define SAMPLE_VAR_CLK1		(0x02 << 4)
 291
 292#define SDIO_VER_20		0x80
 293#define SDIO_VER_10		0x00
 294#define SDIO_VER_CHG		0x40
 295#define SDIO_BUS_AUTO_SWITCH	0x10
 296
 297#define PINGPONG_BUFFER		0x01
 298#define RING_BUFFER		0x00
 299
 300#define RB_FLUSH		0x80
 301
 302#define DMA_DONE_INT_EN			0x80
 303#define SUSPEND_INT_EN			0x40
 304#define LINK_RDY_INT_EN			0x20
 305#define LINK_DOWN_INT_EN		0x10
 306
 307#define DMA_DONE_INT			0x80
 308#define SUSPEND_INT			0x40
 309#define LINK_RDY_INT			0x20
 310#define LINK_DOWN_INT			0x10
 311
 312#define MRD_ERR_INT_EN			0x40
 313#define MWR_ERR_INT_EN			0x20
 314#define SCSI_CMD_INT_EN			0x10
 315#define TLP_RCV_INT_EN			0x08
 316#define TLP_TRSMT_INT_EN		0x04
 317#define MRD_COMPLETE_INT_EN		0x02
 318#define MWR_COMPLETE_INT_EN		0x01
 319
 320#define MRD_ERR_INT			0x40
 321#define MWR_ERR_INT			0x20
 322#define SCSI_CMD_INT			0x10
 323#define TLP_RX_INT			0x08
 324#define TLP_TX_INT			0x04
 325#define MRD_COMPLETE_INT		0x02
 326#define MWR_COMPLETE_INT		0x01
 327
 328#define MSG_RX_INT_EN			0x08
 329#define MRD_RX_INT_EN			0x04
 330#define MWR_RX_INT_EN			0x02
 331#define CPLD_RX_INT_EN			0x01
 332
 333#define MSG_RX_INT			0x08
 334#define MRD_RX_INT			0x04
 335#define MWR_RX_INT			0x02
 336#define CPLD_RX_INT			0x01
 337
 338#define MSG_TX_INT_EN			0x08
 339#define MRD_TX_INT_EN			0x04
 340#define MWR_TX_INT_EN			0x02
 341#define CPLD_TX_INT_EN			0x01
 342
 343#define MSG_TX_INT			0x08
 344#define MRD_TX_INT			0x04
 345#define MWR_TX_INT			0x02
 346#define CPLD_TX_INT			0x01
 347
 348#define DMA_RST				0x80
 349#define DMA_BUSY			0x04
 350#define DMA_DIR_TO_CARD			0x00
 351#define DMA_DIR_FROM_CARD		0x02
 352#define DMA_EN				0x01
 353#define DMA_128				(0 << 4)
 354#define DMA_256				(1 << 4)
 355#define DMA_512				(2 << 4)
 356#define DMA_1024			(3 << 4)
 357#define DMA_PACK_SIZE_MASK		0x30
 358
 359#define	XD_PWR_OFF_DELAY0		0x00
 360#define	XD_PWR_OFF_DELAY1		0x02
 361#define	XD_PWR_OFF_DELAY2		0x04
 362#define	XD_PWR_OFF_DELAY3		0x06
 363#define	XD_AUTO_PWR_OFF_EN		0xF7
 364#define	XD_NO_AUTO_PWR_OFF		0x08
 365
 366#define	XD_TIME_RWN_1			0x00
 367#define	XD_TIME_RWN_STEP		0x20
 368#define	XD_TIME_RW_1			0x00
 369#define	XD_TIME_RW_STEP			0x04
 370#define	XD_TIME_SETUP_1			0x00
 371#define	XD_TIME_SETUP_STEP		0x01
 372
 373#define	XD_ECC2_UNCORRECTABLE		0x80
 374#define	XD_ECC2_ERROR			0x40
 375#define	XD_ECC1_UNCORRECTABLE		0x20
 376#define	XD_ECC1_ERROR			0x10
 377#define	XD_RDY				0x04
 378#define	XD_CE_EN			0xFD
 379#define	XD_CE_DISEN			0x02
 380#define	XD_WP_EN			0xFE
 381#define	XD_WP_DISEN			0x01
 382
 383#define	XD_TRANSFER_START		0x80
 384#define	XD_TRANSFER_END			0x40
 385#define	XD_PPB_EMPTY			0x20
 386#define	XD_RESET			0x00
 387#define	XD_ERASE			0x01
 388#define	XD_READ_STATUS			0x02
 389#define	XD_READ_ID			0x03
 390#define	XD_READ_REDUNDANT		0x04
 391#define	XD_READ_PAGES			0x05
 392#define	XD_SET_CMD			0x06
 393#define	XD_NORMAL_READ			0x07
 394#define	XD_WRITE_PAGES			0x08
 395#define	XD_NORMAL_WRITE			0x09
 396#define	XD_WRITE_REDUNDANT		0x0A
 397#define	XD_SET_ADDR			0x0B
 398
 399#define	XD_PPB_TO_SIE			0x80
 400#define	XD_TO_PPB_ONLY			0x00
 401#define	XD_BA_TRANSFORM			0x40
 402#define	XD_BA_NO_TRANSFORM		0x00
 403#define	XD_NO_CALC_ECC			0x20
 404#define	XD_CALC_ECC			0x00
 405#define	XD_IGNORE_ECC			0x10
 406#define	XD_CHECK_ECC			0x00
 407#define	XD_DIRECT_TO_RB			0x08
 408#define	XD_ADDR_LENGTH_0		0x00
 409#define	XD_ADDR_LENGTH_1		0x01
 410#define	XD_ADDR_LENGTH_2		0x02
 411#define	XD_ADDR_LENGTH_3		0x03
 412#define	XD_ADDR_LENGTH_4		0x04
 413
 414#define	XD_GPG				0xFF
 415#define	XD_BPG				0x00
 416
 417#define	XD_GBLK				0xFF
 418#define	XD_LATER_BBLK			0xF0
 419
 420#define	XD_ECC2_ALL1			0x80
 421#define	XD_ECC1_ALL1			0x40
 422#define	XD_BA2_ALL0			0x20
 423#define	XD_BA1_ALL0			0x10
 424#define	XD_BA1_BA2_EQL			0x04
 425#define	XD_BA2_VALID			0x02
 426#define	XD_BA1_VALID			0x01
 427
 428#define	XD_PGSTS_ZEROBIT_OVER4		0x00
 429#define	XD_PGSTS_NOT_FF			0x02
 430#define	XD_AUTO_CHK_DATA_STATUS		0x01
 431
 432#define	RSTB_MODE_DETECT		0x80
 433#define	MODE_OUT_VLD			0x40
 434#define	MODE_OUT_0_NONE			0x00
 435#define	MODE_OUT_10_NONE		0x04
 436#define	MODE_OUT_10_47			0x05
 437#define	MODE_OUT_10_180			0x06
 438#define	MODE_OUT_10_680			0x07
 439#define	MODE_OUT_16_NONE		0x08
 440#define	MODE_OUT_16_47			0x09
 441#define	MODE_OUT_16_180			0x0A
 442#define	MODE_OUT_16_680			0x0B
 443#define	MODE_OUT_NONE_NONE		0x0C
 444#define	MODE_OUT_NONE_47		0x0D
 445#define	MODE_OUT_NONE_180		0x0E
 446#define	MODE_OUT_NONE_680		0x0F
 447
 448#define	CARD_OC_INT_EN			0x20
 449#define	CARD_DETECT_EN			0x08
 450
 451#define MS_DETECT_EN			0x80
 452#define MS_OCP_INT_EN			0x40
 453#define MS_OCP_INT_CLR			0x20
 454#define MS_OC_CLR			0x10
 455#define SD_DETECT_EN			0x08
 456#define SD_OCP_INT_EN			0x04
 457#define SD_OCP_INT_CLR			0x02
 458#define SD_OC_CLR			0x01
 459
 460#define	CARD_OCP_DETECT			0x80
 461#define	CARD_OC_NOW			0x08
 462#define	CARD_OC_EVER			0x04
 463
 464#define MS_OCP_DETECT			0x80
 465#define MS_OC_NOW			0x40
 466#define MS_OC_EVER			0x20
 467#define SD_OCP_DETECT			0x08
 468#define SD_OC_NOW			0x04
 469#define SD_OC_EVER			0x02
 470
 471#define	CARD_OC_INT_CLR			0x08
 472#define	CARD_OC_CLR			0x02
 473
 474#define SD_OCP_GLITCH_MASK		0x07
 475#define SD_OCP_GLITCH_6_4		0x00
 476#define SD_OCP_GLITCH_64		0x01
 477#define SD_OCP_GLITCH_640		0x02
 478#define SD_OCP_GLITCH_1000		0x03
 479#define SD_OCP_GLITCH_2000		0x04
 480#define SD_OCP_GLITCH_4000		0x05
 481#define SD_OCP_GLITCH_8000		0x06
 482#define SD_OCP_GLITCH_10000		0x07
 483
 484#define MS_OCP_GLITCH_MASK		0x70
 485#define MS_OCP_GLITCH_6_4		(0x00 << 4)
 486#define MS_OCP_GLITCH_64		(0x01 << 4)
 487#define MS_OCP_GLITCH_640		(0x02 << 4)
 488#define MS_OCP_GLITCH_1000		(0x03 << 4)
 489#define MS_OCP_GLITCH_2000		(0x04 << 4)
 490#define MS_OCP_GLITCH_4000		(0x05 << 4)
 491#define MS_OCP_GLITCH_8000		(0x06 << 4)
 492#define MS_OCP_GLITCH_10000		(0x07 << 4)
 493
 494#define OCP_TIME_60			0x00
 495#define OCP_TIME_100			(0x01 << 3)
 496#define OCP_TIME_200			(0x02 << 3)
 497#define OCP_TIME_400			(0x03 << 3)
 498#define OCP_TIME_600			(0x04 << 3)
 499#define OCP_TIME_800			(0x05 << 3)
 500#define OCP_TIME_1100			(0x06 << 3)
 501#define OCP_TIME_MASK			0x38
 502
 503#define MS_OCP_TIME_60			0x00
 504#define MS_OCP_TIME_100			(0x01 << 4)
 505#define MS_OCP_TIME_200			(0x02 << 4)
 506#define MS_OCP_TIME_400			(0x03 << 4)
 507#define MS_OCP_TIME_600			(0x04 << 4)
 508#define MS_OCP_TIME_800			(0x05 << 4)
 509#define MS_OCP_TIME_1100		(0x06 << 4)
 510#define MS_OCP_TIME_MASK		0x70
 511
 512#define SD_OCP_TIME_60			0x00
 513#define SD_OCP_TIME_100			0x01
 514#define SD_OCP_TIME_200			0x02
 515#define SD_OCP_TIME_400			0x03
 516#define SD_OCP_TIME_600			0x04
 517#define SD_OCP_TIME_800			0x05
 518#define SD_OCP_TIME_1100		0x06
 519#define SD_OCP_TIME_MASK		0x07
 520
 521#define OCP_THD_315_417			0x00
 522#define OCP_THD_283_783			(0x01 << 6)
 523#define OCP_THD_244_946			(0x02 << 6)
 524#define OCP_THD_191_1080		(0x03 << 6)
 525#define OCP_THD_MASK			0xC0
 526
 527#define MS_OCP_THD_450			0x00
 528#define MS_OCP_THD_550			(0x01 << 4)
 529#define MS_OCP_THD_650			(0x02 << 4)
 530#define MS_OCP_THD_750			(0x03 << 4)
 531#define MS_OCP_THD_850			(0x04 << 4)
 532#define MS_OCP_THD_950			(0x05 << 4)
 533#define MS_OCP_THD_1050			(0x06 << 4)
 534#define MS_OCP_THD_1150			(0x07 << 4)
 535#define MS_OCP_THD_MASK			0x70
 536
 537#define SD_OCP_THD_450			0x00
 538#define SD_OCP_THD_550			0x01
 539#define SD_OCP_THD_650			0x02
 540#define SD_OCP_THD_750			0x03
 541#define SD_OCP_THD_850			0x04
 542#define SD_OCP_THD_950			0x05
 543#define SD_OCP_THD_1050			0x06
 544#define SD_OCP_THD_1150			0x07
 545#define SD_OCP_THD_MASK			0x07
 546
 547#define FPGA_MS_PULL_CTL_EN		0xEF
 548#define FPGA_SD_PULL_CTL_EN		0xF7
 549#define FPGA_XD_PULL_CTL_EN1		0xFE
 550#define FPGA_XD_PULL_CTL_EN2		0xFD
 551#define FPGA_XD_PULL_CTL_EN3		0xFB
 552
 553#define FPGA_MS_PULL_CTL_BIT		0x10
 554#define FPGA_SD_PULL_CTL_BIT		0x08
 555
 556#define BLINK_EN			0x08
 557#define LED_GPIO0			(0 << 4)
 558#define LED_GPIO1			(1 << 4)
 559#define LED_GPIO2			(2 << 4)
 560
 561#define SDIO_BUS_CTRL		0x01
 562#define SDIO_CD_CTRL		0x02
 563
 564#define SSC_RSTB		0x80
 565#define SSC_8X_EN		0x40
 566#define SSC_FIX_FRAC		0x20
 567#define SSC_SEL_1M		0x00
 568#define SSC_SEL_2M		0x08
 569#define SSC_SEL_4M		0x10
 570#define SSC_SEL_8M		0x18
 571
 572#define SSC_DEPTH_MASK		0x07
 573#define SSC_DEPTH_DISALBE	0x00
 574#define SSC_DEPTH_4M		0x01
 575#define SSC_DEPTH_2M		0x02
 576#define SSC_DEPTH_1M		0x03
 577#define SSC_DEPTH_512K		0x04
 578#define SSC_DEPTH_256K		0x05
 579#define SSC_DEPTH_128K		0x06
 580#define SSC_DEPTH_64K		0x07
 581
 582#define XD_D3_NP		0x00
 583#define XD_D3_PD		(0x01 << 6)
 584#define XD_D3_PU		(0x02 << 6)
 585#define XD_D2_NP		0x00
 586#define XD_D2_PD		(0x01 << 4)
 587#define XD_D2_PU		(0x02 << 4)
 588#define XD_D1_NP		0x00
 589#define XD_D1_PD		(0x01 << 2)
 590#define XD_D1_PU		(0x02 << 2)
 591#define XD_D0_NP		0x00
 592#define XD_D0_PD		0x01
 593#define XD_D0_PU		0x02
 594
 595#define SD_D7_NP		0x00
 596#define SD_D7_PD		(0x01 << 4)
 597#define SD_DAT7_PU		(0x02 << 4)
 598#define SD_CLK_NP		0x00
 599#define SD_CLK_PD		(0x01 << 2)
 600#define SD_CLK_PU		(0x02 << 2)
 601#define SD_D5_NP		0x00
 602#define SD_D5_PD		0x01
 603#define SD_D5_PU		0x02
 604
 605#define MS_D1_NP		0x00
 606#define MS_D1_PD		(0x01 << 6)
 607#define MS_D1_PU		(0x02 << 6)
 608#define MS_D2_NP		0x00
 609#define MS_D2_PD		(0x01 << 4)
 610#define MS_D2_PU		(0x02 << 4)
 611#define MS_CLK_NP		0x00
 612#define MS_CLK_PD		(0x01 << 2)
 613#define MS_CLK_PU		(0x02 << 2)
 614#define MS_D6_NP		0x00
 615#define MS_D6_PD		0x01
 616#define MS_D6_PU		0x02
 617
 618#define XD_D7_NP		0x00
 619#define XD_D7_PD		(0x01 << 6)
 620#define XD_D7_PU		(0x02 << 6)
 621#define XD_D6_NP		0x00
 622#define XD_D6_PD		(0x01 << 4)
 623#define XD_D6_PU		(0x02 << 4)
 624#define XD_D5_NP		0x00
 625#define XD_D5_PD		(0x01 << 2)
 626#define XD_D5_PU		(0x02 << 2)
 627#define XD_D4_NP		0x00
 628#define XD_D4_PD		0x01
 629#define XD_D4_PU		0x02
 630
 631#define SD_D6_NP		0x00
 632#define SD_D6_PD		(0x01 << 6)
 633#define SD_D6_PU		(0x02 << 6)
 634#define SD_D0_NP		0x00
 635#define SD_D0_PD		(0x01 << 4)
 636#define SD_D0_PU		(0x02 << 4)
 637#define SD_D1_NP		0x00
 638#define SD_D1_PD		0x01
 639#define SD_D1_PU		0x02
 640
 641#define MS_D3_NP		0x00
 642#define MS_D3_PD		(0x01 << 6)
 643#define MS_D3_PU		(0x02 << 6)
 644#define MS_D0_NP		0x00
 645#define MS_D0_PD		(0x01 << 4)
 646#define MS_D0_PU		(0x02 << 4)
 647#define MS_BS_NP		0x00
 648#define MS_BS_PD		(0x01 << 2)
 649#define MS_BS_PU		(0x02 << 2)
 650
 651#define XD_WP_NP		0x00
 652#define XD_WP_PD		(0x01 << 6)
 653#define XD_WP_PU		(0x02 << 6)
 654#define XD_CE_NP		0x00
 655#define XD_CE_PD		(0x01 << 3)
 656#define XD_CE_PU		(0x02 << 3)
 657#define XD_CLE_NP		0x00
 658#define XD_CLE_PD		(0x01 << 1)
 659#define XD_CLE_PU		(0x02 << 1)
 660#define XD_CD_PD		0x00
 661#define XD_CD_PU		0x01
 662
 663#define SD_D4_NP		0x00
 664#define SD_D4_PD		(0x01 << 6)
 665#define SD_D4_PU		(0x02 << 6)
 666
 667#define MS_D7_NP		0x00
 668#define MS_D7_PD		(0x01 << 6)
 669#define MS_D7_PU		(0x02 << 6)
 670
 671#define XD_RDY_NP		0x00
 672#define XD_RDY_PD		(0x01 << 6)
 673#define XD_RDY_PU		(0x02 << 6)
 674#define XD_WE_NP		0x00
 675#define XD_WE_PD		(0x01 << 4)
 676#define XD_WE_PU		(0x02 << 4)
 677#define XD_RE_NP		0x00
 678#define XD_RE_PD		(0x01 << 2)
 679#define XD_RE_PU		(0x02 << 2)
 680#define XD_ALE_NP		0x00
 681#define XD_ALE_PD		0x01
 682#define XD_ALE_PU		0x02
 683
 684#define SD_D3_NP		0x00
 685#define SD_D3_PD		(0x01 << 4)
 686#define SD_D3_PU		(0x02 << 4)
 687#define SD_D2_NP		0x00
 688#define SD_D2_PD		(0x01 << 2)
 689#define SD_D2_PU		(0x02 << 2)
 690
 691#define MS_INS_PD		0x00
 692#define MS_INS_PU		(0x01 << 7)
 693#define SD_WP_NP		0x00
 694#define SD_WP_PD		(0x01 << 5)
 695#define SD_WP_PU		(0x02 << 5)
 696#define SD_CD_PD		0x00
 697#define SD_CD_PU		(0x01 << 4)
 698#define SD_CMD_NP		0x00
 699#define SD_CMD_PD		(0x01 << 2)
 700#define SD_CMD_PU		(0x02 << 2)
 701
 702#define MS_D5_NP		0x00
 703#define MS_D5_PD		(0x01 << 2)
 704#define MS_D5_PU		(0x02 << 2)
 705#define MS_D4_NP		0x00
 706#define MS_D4_PD		0x01
 707#define MS_D4_PU		0x02
 708
 709#define FORCE_PM_CLOCK		0x10
 710#define EN_CLOCK_PM		0x01
 711
 712#define HOST_ENTER_S3		0x02
 713#define HOST_ENTER_S1		0x01
 714
 715#define AUX_PWR_DETECTED	0x01
 716
 717#define PHY_DEBUG_MODE		0x01
 718
 719#define SPI_COMMAND_BIT_8	0xE0
 720#define SPI_ADDRESS_BIT_24	0x17
 721#define SPI_ADDRESS_BIT_32	0x1F
 722
 723#define SPI_TRANSFER0_START	0x80
 724#define SPI_TRANSFER0_END	0x40
 725#define SPI_C_MODE0		0x00
 726#define SPI_CA_MODE0		0x01
 727#define SPI_CDO_MODE0		0x02
 728#define SPI_CDI_MODE0		0x03
 729#define SPI_CADO_MODE0		0x04
 730#define SPI_CADI_MODE0		0x05
 731#define SPI_POLLING_MODE0	0x06
 732
 733#define SPI_TRANSFER1_START	0x80
 734#define SPI_TRANSFER1_END	0x40
 735#define SPI_DO_MODE1		0x00
 736#define SPI_DI_MODE1		0x01
 737
 738#define CS_POLARITY_HIGH	0x40
 739#define CS_POLARITY_LOW		0x00
 740#define DTO_MSB_FIRST		0x00
 741#define DTO_LSB_FIRST		0x20
 742#define SPI_MASTER		0x00
 743#define SPI_SLAVE		0x10
 744#define SPI_MODE0		0x00
 745#define SPI_MODE1		0x04
 746#define SPI_MODE2		0x08
 747#define SPI_MODE3		0x0C
 748#define SPI_MANUAL		0x00
 749#define SPI_HALF_AUTO		0x01
 750#define SPI_AUTO		0x02
 751#define SPI_EEPROM_AUTO		0x03
 752
 753#define EDO_TIMING_MASK		0x03
 754#define SAMPLE_RISING		0x00
 755#define SAMPLE_DELAY_HALF	0x01
 756#define SAMPLE_DELAY_ONE	0x02
 757#define SAPMLE_DELAY_ONE_HALF	0x03
 758#define TCS_MASK		0x0C
 759
 760#define NOT_BYPASS_SD		0x02
 761#define DISABLE_SDIO_FUNC	0x04
 762#define SELECT_1LUN		0x08
 763
 764#define PWR_GATE_EN		0x01
 765#define LDO3318_PWR_MASK	0x06
 766#define LDO_ON			0x00
 767#define LDO_SUSPEND		0x04
 768#define LDO_OFF			0x06
 769
 770#define SD_CFG1			0xFDA0
 771#define SD_CFG2			0xFDA1
 772#define SD_CFG3			0xFDA2
 773#define SD_STAT1		0xFDA3
 774#define SD_STAT2		0xFDA4
 775#define SD_BUS_STAT		0xFDA5
 776#define SD_PAD_CTL		0xFDA6
 777#define SD_SAMPLE_POINT_CTL	0xFDA7
 778#define SD_PUSH_POINT_CTL	0xFDA8
 779#define SD_CMD0			0xFDA9
 780#define SD_CMD1			0xFDAA
 781#define SD_CMD2			0xFDAB
 782#define SD_CMD3			0xFDAC
 783#define SD_CMD4			0xFDAD
 784#define SD_CMD5			0xFDAE
 785#define SD_BYTE_CNT_L		0xFDAF
 786#define SD_BYTE_CNT_H		0xFDB0
 787#define SD_BLOCK_CNT_L		0xFDB1
 788#define SD_BLOCK_CNT_H		0xFDB2
 789#define SD_TRANSFER		0xFDB3
 790#define SD_CMD_STATE		0xFDB5
 791#define SD_DATA_STATE		0xFDB6
 792
 793#define	DCM_DRP_CTL         	0xFC23
 794#define	DCM_DRP_TRIG		0xFC24
 795#define	DCM_DRP_CFG         	0xFC25
 796#define	DCM_DRP_WR_DATA_L   	0xFC26
 797#define	DCM_DRP_WR_DATA_H   	0xFC27
 798#define	DCM_DRP_RD_DATA_L   	0xFC28
 799#define	DCM_DRP_RD_DATA_H   	0xFC29
 800#define SD_VPCLK0_CTL		0xFC2A
 801#define SD_VPCLK1_CTL		0xFC2B
 802#define SD_DCMPS0_CTL		0xFC2C
 803#define SD_DCMPS1_CTL		0xFC2D
 804#define SD_VPTX_CTL		SD_VPCLK0_CTL
 805#define SD_VPRX_CTL		SD_VPCLK1_CTL
 806#define SD_DCMPS_TX_CTL		SD_DCMPS0_CTL
 807#define SD_DCMPS_RX_CTL		SD_DCMPS1_CTL
 808
 809#define CARD_CLK_SOURCE		0xFC2E
 810
 811#define CARD_PWR_CTL		0xFD50
 812#define CARD_CLK_SWITCH		0xFD51
 813#define CARD_SHARE_MODE		0xFD52
 814#define CARD_DRIVE_SEL		0xFD53
 815#define CARD_STOP		0xFD54
 816#define CARD_OE			0xFD55
 817#define CARD_AUTO_BLINK		0xFD56
 818#define CARD_GPIO_DIR		0xFD57
 819#define CARD_GPIO		0xFD58
 820
 821#define CARD_DATA_SOURCE	0xFD5B
 822#define CARD_SELECT		0xFD5C
 823#define SD30_DRIVE_SEL		0xFD5E
 824
 825#define CARD_CLK_EN		0xFD69
 826
 827#define SDIO_CTRL		0xFD6B
 828
 829#define FPDCTL			0xFC00
 830#define PDINFO			0xFC01
 831
 832#define CLK_CTL			0xFC02
 833#define CLK_DIV			0xFC03
 834#define CLK_SEL			0xFC04
 835
 836#define SSC_DIV_N_0		0xFC0F
 837#define SSC_DIV_N_1		0xFC10
 838
 839#define RCCTL			0xFC14
 840
 841#define FPGA_PULL_CTL		0xFC1D
 842
 843#define CARD_PULL_CTL1		0xFD60
 844#define CARD_PULL_CTL2		0xFD61
 845#define CARD_PULL_CTL3		0xFD62
 846#define CARD_PULL_CTL4		0xFD63
 847#define CARD_PULL_CTL5		0xFD64
 848#define CARD_PULL_CTL6		0xFD65
 849
 850#define IRQEN0				0xFE20
 851#define IRQSTAT0			0xFE21
 852#define IRQEN1				0xFE22
 853#define IRQSTAT1			0xFE23
 854#define TLPRIEN				0xFE24
 855#define TLPRISTAT			0xFE25
 856#define TLPTIEN				0xFE26
 857#define TLPTISTAT			0xFE27
 858#define DMATC0				0xFE28
 859#define DMATC1				0xFE29
 860#define DMATC2				0xFE2A
 861#define DMATC3				0xFE2B
 862#define DMACTL				0xFE2C
 863#define BCTL				0xFE2D
 864#define RBBC0				0xFE2E
 865#define RBBC1				0xFE2F
 866#define RBDAT				0xFE30
 867#define RBCTL				0xFE34
 868#define CFGADDR0			0xFE35
 869#define CFGADDR1			0xFE36
 870#define CFGDATA0			0xFE37
 871#define CFGDATA1			0xFE38
 872#define CFGDATA2			0xFE39
 873#define CFGDATA3			0xFE3A
 874#define CFGRWCTL			0xFE3B
 875#define PHYRWCTL			0xFE3C
 876#define PHYDATA0			0xFE3D
 877#define PHYDATA1			0xFE3E
 878#define PHYADDR				0xFE3F
 879#define MSGRXDATA0			0xFE40
 880#define MSGRXDATA1			0xFE41
 881#define MSGRXDATA2			0xFE42
 882#define MSGRXDATA3			0xFE43
 883#define MSGTXDATA0			0xFE44
 884#define MSGTXDATA1			0xFE45
 885#define MSGTXDATA2			0xFE46
 886#define MSGTXDATA3			0xFE47
 887#define MSGTXCTL			0xFE48
 888#define PETXCFG				0xFE49
 889
 890#define CDRESUMECTL			0xFE52
 891#define WAKE_SEL_CTL			0xFE54
 892#define PME_FORCE_CTL			0xFE56
 893#define ASPM_FORCE_CTL			0xFE57
 894#define PM_CLK_FORCE_CTL		0xFE58
 895#define PERST_GLITCH_WIDTH		0xFE5C
 896#define CHANGE_LINK_STATE		0xFE5B
 897#define RESET_LOAD_REG			0xFE5E
 898#define HOST_SLEEP_STATE		0xFE60
 899#define MAIN_PWR_OFF_CTL		0xFE70	/* RTS5208 */
 900#define SDIO_CFG			0xFE70	/* RTS5209 */
 901
 902#define NFTS_TX_CTRL			0xFE72
 903
 904#define PWR_GATE_CTRL			0xFE75
 905#define PWD_SUSPEND_EN			0xFE76
 906
 907#define EFUSE_CONTENT			0xFE5F
 908
 909#define XD_INIT				0xFD10
 910#define XD_DTCTL			0xFD11
 911#define XD_CTL				0xFD12
 912#define XD_TRANSFER			0xFD13
 913#define XD_CFG				0xFD14
 914#define XD_ADDRESS0			0xFD15
 915#define XD_ADDRESS1			0xFD16
 916#define XD_ADDRESS2			0xFD17
 917#define XD_ADDRESS3			0xFD18
 918#define XD_ADDRESS4			0xFD19
 919#define XD_DAT				0xFD1A
 920#define XD_PAGE_CNT			0xFD1B
 921#define XD_PAGE_STATUS			0xFD1C
 922#define XD_BLOCK_STATUS			0xFD1D
 923#define XD_BLOCK_ADDR1_L		0xFD1E
 924#define XD_BLOCK_ADDR1_H		0xFD1F
 925#define XD_BLOCK_ADDR2_L		0xFD20
 926#define XD_BLOCK_ADDR2_H		0xFD21
 927#define XD_BYTE_CNT_L			0xFD22
 928#define XD_BYTE_CNT_H			0xFD23
 929#define	XD_PARITY			0xFD24
 930#define XD_ECC_BIT1			0xFD25
 931#define XD_ECC_BYTE1			0xFD26
 932#define XD_ECC_BIT2			0xFD27
 933#define XD_ECC_BYTE2			0xFD28
 934#define XD_RESERVED0			0xFD29
 935#define XD_RESERVED1			0xFD2A
 936#define XD_RESERVED2			0xFD2B
 937#define XD_RESERVED3			0xFD2C
 938#define XD_CHK_DATA_STATUS		0xFD2D
 939#define XD_CATCTL			0xFD2E
 940
 941#define MS_CFG				0xFD40
 942#define MS_TPC				0xFD41
 943#define MS_TRANS_CFG			0xFD42
 944#define MS_TRANSFER			0xFD43
 945#define MS_INT_REG			0xFD44
 946#define MS_BYTE_CNT			0xFD45
 947#define MS_SECTOR_CNT_L			0xFD46
 948#define MS_SECTOR_CNT_H			0xFD47
 949#define MS_DBUS_H			0xFD48
 950
 951#define SSC_CTL1			0xFC11
 952#define SSC_CTL2			0xFC12
 953
 954#define OCPCTL				0xFC15
 955#define OCPSTAT				0xFC16
 956#define OCPCLR				0xFC17	/* 5208 */
 957#define OCPGLITCH			0xFC17	/* 5209 */
 958#define OCPPARA1			0xFC18
 959#define OCPPARA2			0xFC19
 960
 961#define EFUSE_OP			0xFC20
 962#define EFUSE_CTRL			0xFC21
 963#define EFUSE_DATA			0xFC22
 964
 965#define	SPI_COMMAND			0xFD80
 966#define	SPI_ADDR0			0xFD81
 967#define	SPI_ADDR1			0xFD82
 968#define	SPI_ADDR2			0xFD83
 969#define	SPI_ADDR3			0xFD84
 970#define	SPI_CA_NUMBER			0xFD85
 971#define	SPI_LENGTH0			0xFD86
 972#define	SPI_LENGTH1			0xFD87
 973#define	SPI_DATA			0xFD88
 974#define SPI_DATA_NUMBER			0xFD89
 975#define	SPI_TRANSFER0			0xFD90
 976#define	SPI_TRANSFER1			0xFD91
 977#define	SPI_CONTROL			0xFD92
 978#define	SPI_SIG				0xFD93
 979#define	SPI_TCTL			0xFD94
 980#define	SPI_SLAVE_NUM			0xFD95
 981#define	SPI_CLK_DIVIDER0		0xFD96
 982#define	SPI_CLK_DIVIDER1		0xFD97
 983
 984#define SRAM_BASE			0xE600
 985#define RBUF_BASE			0xF400
 986#define PPBUF_BASE1			0xF800
 987#define PPBUF_BASE2			0xFA00
 988#define IMAGE_FLAG_ADDR0		0xCE80
 989#define IMAGE_FLAG_ADDR1		0xCE81
 990
 991#define READ_OP			1
 992#define WRITE_OP		2
 993
 994#define LCTLR		0x80
 995
 996#define POLLING_WAIT_CNT	1
 997#define IDLE_MAX_COUNT		10
 998#define SDIO_IDLE_COUNT		10
 999
1000#define DEBOUNCE_CNT			5
1001
1002void do_remaining_work(struct rtsx_chip *chip);
1003void try_to_switch_sdio_ctrl(struct rtsx_chip *chip);
1004void do_reset_sd_card(struct rtsx_chip *chip);
1005void do_reset_xd_card(struct rtsx_chip *chip);
1006void do_reset_ms_card(struct rtsx_chip *chip);
1007void rtsx_power_off_card(struct rtsx_chip *chip);
1008void rtsx_release_cards(struct rtsx_chip *chip);
1009void rtsx_reset_cards(struct rtsx_chip *chip);
1010void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip);
1011void rtsx_init_cards(struct rtsx_chip *chip);
1012int switch_ssc_clock(struct rtsx_chip *chip, int clk);
1013int switch_normal_clock(struct rtsx_chip *chip, int clk);
1014int enable_card_clock(struct rtsx_chip *chip, u8 card);
1015int disable_card_clock(struct rtsx_chip *chip, u8 card);
1016int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 sec_addr, u16 sec_cnt);
1017void trans_dma_enable(enum dma_data_direction dir, struct rtsx_chip *chip, u32 byte_cnt, u8 pack_size);
1018void toggle_gpio(struct rtsx_chip *chip, u8 gpio);
1019void turn_on_led(struct rtsx_chip *chip, u8 gpio);
1020void turn_off_led(struct rtsx_chip *chip, u8 gpio);
1021
1022int card_share_mode(struct rtsx_chip *chip, int card);
1023int select_card(struct rtsx_chip *chip, int card);
1024int detect_card_cd(struct rtsx_chip *chip, int card);
1025int check_card_exist(struct rtsx_chip *chip, unsigned int lun);
1026int check_card_ready(struct rtsx_chip *chip, unsigned int lun);
1027int check_card_wp(struct rtsx_chip *chip, unsigned int lun);
1028int check_card_fail(struct rtsx_chip *chip, unsigned int lun);
1029int check_card_ejected(struct rtsx_chip *chip, unsigned int lun);
1030void eject_card(struct rtsx_chip *chip, unsigned int lun);
1031u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun);
1032
1033static inline u32 get_card_size(struct rtsx_chip *chip, unsigned int lun)
1034{
1035#ifdef SUPPORT_SD_LOCK
1036	struct sd_info *sd_card = &(chip->sd_card);
1037
1038	if ((get_lun_card(chip, lun) == SD_CARD) && (sd_card->sd_lock_status & SD_LOCKED))
1039		return 0;
1040	else
1041		return chip->capacity[lun];
1042#else
1043	return chip->capacity[lun];
1044#endif
1045}
1046
1047static inline int switch_clock(struct rtsx_chip *chip, int clk)
1048{
1049	int retval = 0;
1050
1051	if (chip->asic_code)
1052		retval = switch_ssc_clock(chip, clk);
1053	else
1054		retval = switch_normal_clock(chip, clk);
1055
1056	return retval;
1057}
1058
1059int card_power_on(struct rtsx_chip *chip, u8 card);
1060int card_power_off(struct rtsx_chip *chip, u8 card);
1061
1062static inline int card_power_off_all(struct rtsx_chip *chip)
1063{
1064	RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0x0F, 0x0F);
1065
1066	return STATUS_SUCCESS;
1067}
1068
1069static inline void rtsx_clear_xd_error(struct rtsx_chip *chip)
1070{
1071	rtsx_write_register(chip, CARD_STOP, XD_STOP | XD_CLR_ERR, XD_STOP | XD_CLR_ERR);
1072}
1073
1074static inline void rtsx_clear_sd_error(struct rtsx_chip *chip)
1075{
1076	rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
1077}
1078
1079static inline void rtsx_clear_ms_error(struct rtsx_chip *chip)
1080{
1081	rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR);
1082}
1083
1084static inline void rtsx_clear_spi_error(struct rtsx_chip *chip)
1085{
1086	rtsx_write_register(chip, CARD_STOP, SPI_STOP | SPI_CLR_ERR, SPI_STOP | SPI_CLR_ERR);
1087}
1088
1089#ifdef SUPPORT_SDIO_ASPM
1090void dynamic_configure_sdio_aspm(struct rtsx_chip *chip);
1091#endif
1092
1093#endif  /* __REALTEK_RTSX_CARD_H */