/drivers/staging/octeon/cvmx-smix-defs.h

  1/***********************license start***************
  2 * Author: Cavium Networks
  3 *
  4 * Contact: support@caviumnetworks.com
  5 * This file is part of the OCTEON SDK
  6 *
  7 * Copyright (c) 2003-2008 Cavium Networks
  8 *
  9 * This file is free software; you can redistribute it and/or modify
 10 * it under the terms of the GNU General Public License, Version 2, as
 11 * published by the Free Software Foundation.
 12 *
 13 * This file is distributed in the hope that it will be useful, but
 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 16 * NONINFRINGEMENT.  See the GNU General Public License for more
 17 * details.
 18 *
 19 * You should have received a copy of the GNU General Public License
 20 * along with this file; if not, write to the Free Software
 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 22 * or visit http://www.gnu.org/licenses/.
 23 *
 24 * This file may also be available under a different license from Cavium.
 25 * Contact Cavium Networks for more information
 26 ***********************license end**************************************/
 27
 28#ifndef __CVMX_SMIX_DEFS_H__
 29#define __CVMX_SMIX_DEFS_H__
 30
 31#define CVMX_SMIX_CLK(offset) \
 32	 CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
 33#define CVMX_SMIX_CMD(offset) \
 34	 CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
 35#define CVMX_SMIX_EN(offset) \
 36	 CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
 37#define CVMX_SMIX_RD_DAT(offset) \
 38	 CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
 39#define CVMX_SMIX_WR_DAT(offset) \
 40	 CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
 41
 42union cvmx_smix_clk {
 43	uint64_t u64;
 44	struct cvmx_smix_clk_s {
 45		uint64_t reserved_25_63:39;
 46		uint64_t mode:1;
 47		uint64_t reserved_21_23:3;
 48		uint64_t sample_hi:5;
 49		uint64_t sample_mode:1;
 50		uint64_t reserved_14_14:1;
 51		uint64_t clk_idle:1;
 52		uint64_t preamble:1;
 53		uint64_t sample:4;
 54		uint64_t phase:8;
 55	} s;
 56	struct cvmx_smix_clk_cn30xx {
 57		uint64_t reserved_21_63:43;
 58		uint64_t sample_hi:5;
 59		uint64_t reserved_14_15:2;
 60		uint64_t clk_idle:1;
 61		uint64_t preamble:1;
 62		uint64_t sample:4;
 63		uint64_t phase:8;
 64	} cn30xx;
 65	struct cvmx_smix_clk_cn30xx cn31xx;
 66	struct cvmx_smix_clk_cn30xx cn38xx;
 67	struct cvmx_smix_clk_cn30xx cn38xxp2;
 68	struct cvmx_smix_clk_cn50xx {
 69		uint64_t reserved_25_63:39;
 70		uint64_t mode:1;
 71		uint64_t reserved_21_23:3;
 72		uint64_t sample_hi:5;
 73		uint64_t reserved_14_15:2;
 74		uint64_t clk_idle:1;
 75		uint64_t preamble:1;
 76		uint64_t sample:4;
 77		uint64_t phase:8;
 78	} cn50xx;
 79	struct cvmx_smix_clk_s cn52xx;
 80	struct cvmx_smix_clk_cn50xx cn52xxp1;
 81	struct cvmx_smix_clk_s cn56xx;
 82	struct cvmx_smix_clk_cn50xx cn56xxp1;
 83	struct cvmx_smix_clk_cn30xx cn58xx;
 84	struct cvmx_smix_clk_cn30xx cn58xxp1;
 85};
 86
 87union cvmx_smix_cmd {
 88	uint64_t u64;
 89	struct cvmx_smix_cmd_s {
 90		uint64_t reserved_18_63:46;
 91		uint64_t phy_op:2;
 92		uint64_t reserved_13_15:3;
 93		uint64_t phy_adr:5;
 94		uint64_t reserved_5_7:3;
 95		uint64_t reg_adr:5;
 96	} s;
 97	struct cvmx_smix_cmd_cn30xx {
 98		uint64_t reserved_17_63:47;
 99		uint64_t phy_op:1;
100		uint64_t reserved_13_15:3;
101		uint64_t phy_adr:5;
102		uint64_t reserved_5_7:3;
103		uint64_t reg_adr:5;
104	} cn30xx;
105	struct cvmx_smix_cmd_cn30xx cn31xx;
106	struct cvmx_smix_cmd_cn30xx cn38xx;
107	struct cvmx_smix_cmd_cn30xx cn38xxp2;
108	struct cvmx_smix_cmd_s cn50xx;
109	struct cvmx_smix_cmd_s cn52xx;
110	struct cvmx_smix_cmd_s cn52xxp1;
111	struct cvmx_smix_cmd_s cn56xx;
112	struct cvmx_smix_cmd_s cn56xxp1;
113	struct cvmx_smix_cmd_cn30xx cn58xx;
114	struct cvmx_smix_cmd_cn30xx cn58xxp1;
115};
116
117union cvmx_smix_en {
118	uint64_t u64;
119	struct cvmx_smix_en_s {
120		uint64_t reserved_1_63:63;
121		uint64_t en:1;
122	} s;
123	struct cvmx_smix_en_s cn30xx;
124	struct cvmx_smix_en_s cn31xx;
125	struct cvmx_smix_en_s cn38xx;
126	struct cvmx_smix_en_s cn38xxp2;
127	struct cvmx_smix_en_s cn50xx;
128	struct cvmx_smix_en_s cn52xx;
129	struct cvmx_smix_en_s cn52xxp1;
130	struct cvmx_smix_en_s cn56xx;
131	struct cvmx_smix_en_s cn56xxp1;
132	struct cvmx_smix_en_s cn58xx;
133	struct cvmx_smix_en_s cn58xxp1;
134};
135
136union cvmx_smix_rd_dat {
137	uint64_t u64;
138	struct cvmx_smix_rd_dat_s {
139		uint64_t reserved_18_63:46;
140		uint64_t pending:1;
141		uint64_t val:1;
142		uint64_t dat:16;
143	} s;
144	struct cvmx_smix_rd_dat_s cn30xx;
145	struct cvmx_smix_rd_dat_s cn31xx;
146	struct cvmx_smix_rd_dat_s cn38xx;
147	struct cvmx_smix_rd_dat_s cn38xxp2;
148	struct cvmx_smix_rd_dat_s cn50xx;
149	struct cvmx_smix_rd_dat_s cn52xx;
150	struct cvmx_smix_rd_dat_s cn52xxp1;
151	struct cvmx_smix_rd_dat_s cn56xx;
152	struct cvmx_smix_rd_dat_s cn56xxp1;
153	struct cvmx_smix_rd_dat_s cn58xx;
154	struct cvmx_smix_rd_dat_s cn58xxp1;
155};
156
157union cvmx_smix_wr_dat {
158	uint64_t u64;
159	struct cvmx_smix_wr_dat_s {
160		uint64_t reserved_18_63:46;
161		uint64_t pending:1;
162		uint64_t val:1;
163		uint64_t dat:16;
164	} s;
165	struct cvmx_smix_wr_dat_s cn30xx;
166	struct cvmx_smix_wr_dat_s cn31xx;
167	struct cvmx_smix_wr_dat_s cn38xx;
168	struct cvmx_smix_wr_dat_s cn38xxp2;
169	struct cvmx_smix_wr_dat_s cn50xx;
170	struct cvmx_smix_wr_dat_s cn52xx;
171	struct cvmx_smix_wr_dat_s cn52xxp1;
172	struct cvmx_smix_wr_dat_s cn56xx;
173	struct cvmx_smix_wr_dat_s cn56xxp1;
174	struct cvmx_smix_wr_dat_s cn58xx;
175	struct cvmx_smix_wr_dat_s cn58xxp1;
176};
177
178#endif