/drivers/staging/iio/accel/sca3000.h

https://bitbucket.org/slukk/jb-tsm-kernel-4.2 · C Header · 270 lines · 110 code · 33 blank · 127 comment · 0 complexity · 96255c0619755eaf6f0b4df873bd60f6 MD5 · raw file

  1. /*
  2. * sca3000.c -- support VTI sca3000 series accelerometers
  3. * via SPI
  4. *
  5. * Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk>
  6. *
  7. * Partly based upon tle62x0.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * Initial mode is direct measurement.
  14. *
  15. * Untested things
  16. *
  17. * Temperature reading (the e05 I'm testing with doesn't have a sensor)
  18. *
  19. * Free fall detection mode - supported but untested as I'm not droping my
  20. * dubious wire rig far enough to test it.
  21. *
  22. * Unsupported as yet
  23. *
  24. * Time stamping of data from ring. Various ideas on how to do this but none
  25. * are remotely simple. Suggestions welcome.
  26. *
  27. * Individual enabling disabling of channels going into ring buffer
  28. *
  29. * Overflow handling (this is signaled for all but 8 bit ring buffer mode.)
  30. *
  31. * Motion detector using AND combinations of signals.
  32. *
  33. * Note: Be very careful about not touching an register bytes marked
  34. * as reserved on the data sheet. They really mean it as changing convents of
  35. * some will cause the device to lock up.
  36. *
  37. * Known issues - on rare occasions the interrupts lock up. Not sure why as yet.
  38. * Can probably alleviate this by reading the interrupt register on start, but
  39. * that is really just brushing the problem under the carpet.
  40. */
  41. #define SCA3000_WRITE_REG(a) (((a) << 2) | 0x02)
  42. #define SCA3000_READ_REG(a) ((a) << 2)
  43. #define SCA3000_REG_ADDR_REVID 0x00
  44. #define SCA3000_REVID_MAJOR_MASK 0xf0
  45. #define SCA3000_REVID_MINOR_MASK 0x0f
  46. #define SCA3000_REG_ADDR_STATUS 0x02
  47. #define SCA3000_LOCKED 0x20
  48. #define SCA3000_EEPROM_CS_ERROR 0x02
  49. #define SCA3000_SPI_FRAME_ERROR 0x01
  50. /* All reads done using register decrement so no need to directly access LSBs */
  51. #define SCA3000_REG_ADDR_X_MSB 0x05
  52. #define SCA3000_REG_ADDR_Y_MSB 0x07
  53. #define SCA3000_REG_ADDR_Z_MSB 0x09
  54. #define SCA3000_REG_ADDR_RING_OUT 0x0f
  55. /* Temp read untested - the e05 doesn't have the sensor */
  56. #define SCA3000_REG_ADDR_TEMP_MSB 0x13
  57. #define SCA3000_REG_ADDR_MODE 0x14
  58. #define SCA3000_MODE_PROT_MASK 0x28
  59. #define SCA3000_RING_BUF_ENABLE 0x80
  60. #define SCA3000_RING_BUF_8BIT 0x40
  61. /* Free fall detection triggers an interrupt if the acceleration
  62. * is below a threshold for equivalent of 25cm drop
  63. */
  64. #define SCA3000_FREE_FALL_DETECT 0x10
  65. #define SCA3000_MEAS_MODE_NORMAL 0x00
  66. #define SCA3000_MEAS_MODE_OP_1 0x01
  67. #define SCA3000_MEAS_MODE_OP_2 0x02
  68. /* In motion detection mode the accelerations are band pass filtered
  69. * (aprox 1 - 25Hz) and then a programmable threshold used to trigger
  70. * and interrupt.
  71. */
  72. #define SCA3000_MEAS_MODE_MOT_DET 0x03
  73. #define SCA3000_REG_ADDR_BUF_COUNT 0x15
  74. #define SCA3000_REG_ADDR_INT_STATUS 0x16
  75. #define SCA3000_INT_STATUS_THREE_QUARTERS 0x80
  76. #define SCA3000_INT_STATUS_HALF 0x40
  77. #define SCA3000_INT_STATUS_FREE_FALL 0x08
  78. #define SCA3000_INT_STATUS_Y_TRIGGER 0x04
  79. #define SCA3000_INT_STATUS_X_TRIGGER 0x02
  80. #define SCA3000_INT_STATUS_Z_TRIGGER 0x01
  81. /* Used to allow access to multiplexed registers */
  82. #define SCA3000_REG_ADDR_CTRL_SEL 0x18
  83. /* Only available for SCA3000-D03 and SCA3000-D01 */
  84. #define SCA3000_REG_CTRL_SEL_I2C_DISABLE 0x01
  85. #define SCA3000_REG_CTRL_SEL_MD_CTRL 0x02
  86. #define SCA3000_REG_CTRL_SEL_MD_Y_TH 0x03
  87. #define SCA3000_REG_CTRL_SEL_MD_X_TH 0x04
  88. #define SCA3000_REG_CTRL_SEL_MD_Z_TH 0x05
  89. /* BE VERY CAREFUL WITH THIS, IF 3 BITS ARE NOT SET the device
  90. will not function */
  91. #define SCA3000_REG_CTRL_SEL_OUT_CTRL 0x0B
  92. #define SCA3000_OUT_CTRL_PROT_MASK 0xE0
  93. #define SCA3000_OUT_CTRL_BUF_X_EN 0x10
  94. #define SCA3000_OUT_CTRL_BUF_Y_EN 0x08
  95. #define SCA3000_OUT_CTRL_BUF_Z_EN 0x04
  96. #define SCA3000_OUT_CTRL_BUF_DIV_4 0x02
  97. #define SCA3000_OUT_CTRL_BUF_DIV_2 0x01
  98. /* Control which motion detector interrupts are on.
  99. * For now only OR combinations are supported.x
  100. */
  101. #define SCA3000_MD_CTRL_PROT_MASK 0xC0
  102. #define SCA3000_MD_CTRL_OR_Y 0x01
  103. #define SCA3000_MD_CTRL_OR_X 0x02
  104. #define SCA3000_MD_CTRL_OR_Z 0x04
  105. /* Currently unsupported */
  106. #define SCA3000_MD_CTRL_AND_Y 0x08
  107. #define SCA3000_MD_CTRL_AND_X 0x10
  108. #define SAC3000_MD_CTRL_AND_Z 0x20
  109. /* Some control registers of complex access methods requiring this register to
  110. * be used to remove a lock.
  111. */
  112. #define SCA3000_REG_ADDR_UNLOCK 0x1e
  113. #define SCA3000_REG_ADDR_INT_MASK 0x21
  114. #define SCA3000_INT_MASK_PROT_MASK 0x1C
  115. #define SCA3000_INT_MASK_RING_THREE_QUARTER 0x80
  116. #define SCA3000_INT_MASK_RING_HALF 0x40
  117. #define SCA3000_INT_MASK_ALL_INTS 0x02
  118. #define SCA3000_INT_MASK_ACTIVE_HIGH 0x01
  119. #define SCA3000_INT_MASK_ACTIVE_LOW 0x00
  120. /* Values of mulipexed registers (write to ctrl_data after select) */
  121. #define SCA3000_REG_ADDR_CTRL_DATA 0x22
  122. /* Measurement modes available on some sca3000 series chips. Code assumes others
  123. * may become available in the future.
  124. *
  125. * Bypass - Bypass the low-pass filter in the signal channel so as to increase
  126. * signal bandwidth.
  127. *
  128. * Narrow - Narrow low-pass filtering of the signal channel and half output
  129. * data rate by decimation.
  130. *
  131. * Wide - Widen low-pass filtering of signal channel to increase bandwidth
  132. */
  133. #define SCA3000_OP_MODE_BYPASS 0x01
  134. #define SCA3000_OP_MODE_NARROW 0x02
  135. #define SCA3000_OP_MODE_WIDE 0x04
  136. #define SCA3000_MAX_TX 6
  137. #define SCA3000_MAX_RX 2
  138. /**
  139. * struct sca3000_state - device instance state information
  140. * @us: the associated spi device
  141. * @info: chip variant information
  142. * @indio_dev: device information used by the IIO core
  143. * @interrupt_handler_ws: event interrupt handler for all events
  144. * @last_timestamp: the timestamp of the last event
  145. * @mo_det_use_count: reference counter for the motion detection unit
  146. * @lock: lock used to protect elements of sca3000_state
  147. * and the underlying device state.
  148. * @bpse: number of bits per scan element
  149. * @tx: dma-able transmit buffer
  150. * @rx: dma-able receive buffer
  151. **/
  152. struct sca3000_state {
  153. struct spi_device *us;
  154. const struct sca3000_chip_info *info;
  155. struct iio_dev *indio_dev;
  156. struct work_struct interrupt_handler_ws;
  157. s64 last_timestamp;
  158. int mo_det_use_count;
  159. struct mutex lock;
  160. int bpse;
  161. /* Can these share a cacheline ? */
  162. u8 rx[2] ____cacheline_aligned;
  163. u8 tx[6] ____cacheline_aligned;
  164. };
  165. /**
  166. * struct sca3000_chip_info - model dependent parameters
  167. * @scale: scale * 10^-6
  168. * @temp_output: some devices have temperature sensors.
  169. * @measurement_mode_freq: normal mode sampling frequency
  170. * @option_mode_1: first optional mode. Not all models have one
  171. * @option_mode_1_freq: option mode 1 sampling frequency
  172. * @option_mode_2: second optional mode. Not all chips have one
  173. * @option_mode_2_freq: option mode 2 sampling frequency
  174. *
  175. * This structure is used to hold information about the functionality of a given
  176. * sca3000 variant.
  177. **/
  178. struct sca3000_chip_info {
  179. unsigned int scale;
  180. bool temp_output;
  181. int measurement_mode_freq;
  182. int option_mode_1;
  183. int option_mode_1_freq;
  184. int option_mode_2;
  185. int option_mode_2_freq;
  186. int mot_det_mult_xz[6];
  187. int mot_det_mult_y[7];
  188. };
  189. int sca3000_read_data_short(struct sca3000_state *st,
  190. u8 reg_address_high,
  191. int len);
  192. /**
  193. * sca3000_write_reg() write a single register
  194. * @address: address of register on chip
  195. * @val: value to be written to register
  196. *
  197. * The main lock must be held.
  198. **/
  199. int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val);
  200. #ifdef CONFIG_IIO_RING_BUFFER
  201. /**
  202. * sca3000_register_ring_funcs() setup the ring state change functions
  203. **/
  204. void sca3000_register_ring_funcs(struct iio_dev *indio_dev);
  205. /**
  206. * sca3000_configure_ring() - allocate and configure ring buffer
  207. * @indio_dev: iio-core device whose ring is to be configured
  208. *
  209. * The hardware ring buffer needs far fewer ring buffer functions than
  210. * a software one as a lot of things are handled automatically.
  211. * This function also tells the iio core that our device supports a
  212. * hardware ring buffer mode.
  213. **/
  214. int sca3000_configure_ring(struct iio_dev *indio_dev);
  215. /**
  216. * sca3000_unconfigure_ring() - deallocate the ring buffer
  217. * @indio_dev: iio-core device whose ring we are freeing
  218. **/
  219. void sca3000_unconfigure_ring(struct iio_dev *indio_dev);
  220. /**
  221. * sca3000_ring_int_process() handles ring related event pushing and escalation
  222. * @val: the event code
  223. **/
  224. void sca3000_ring_int_process(u8 val, struct iio_ring_buffer *ring);
  225. #else
  226. static inline void sca3000_register_ring_funcs(struct iio_dev *indio_dev)
  227. {
  228. }
  229. static inline
  230. int sca3000_register_ring_access_and_init(struct iio_dev *indio_dev)
  231. {
  232. return 0;
  233. }
  234. static inline void sca3000_ring_int_process(u8 val, void *ring)
  235. {
  236. }
  237. #endif