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/drivers/staging/ft1000/ft1000-pcmcia/ft1000.h

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C Header | 409 lines | 286 code | 56 blank | 67 comment | 0 complexity | a6e4dc5c65fa01a7ae67013c84279346 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. //---------------------------------------------------------------------------
  2. // FT1000 driver for Flarion Flash OFDM NIC Device
  3. //
  4. // Copyright (C) 2002 Flarion Technologies, All rights reserved.
  5. //
  6. // This program is free software; you can redistribute it and/or modify it
  7. // under the terms of the GNU General Public License as published by the Free
  8. // Software Foundation; either version 2 of the License, or (at your option) any
  9. // later version. This program is distributed in the hope that it will be useful,
  10. // but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11. // or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. // more details. You should have received a copy of the GNU General Public
  13. // License along with this program; if not, write to the
  14. // Free Software Foundation, Inc., 59 Temple Place -
  15. // Suite 330, Boston, MA 02111-1307, USA.
  16. //---------------------------------------------------------------------------
  17. //
  18. // File: ft1000.h
  19. //
  20. // Description: Common structures and defines
  21. //
  22. // History:
  23. // 8/29/02 Whc Ported to Linux.
  24. // 7/19/04 Whc Drop packet and cmd msg with pseudo header
  25. // checksum
  26. // 10/27/04 Whc Added dynamic downloading of test image.
  27. // 01/11/04 Whc Added support for Magnemite ASIC
  28. //
  29. //---------------------------------------------------------------------------
  30. #ifndef _FT1000H_
  31. #define _FT1000H_
  32. #define FT1000_DRV_VER 0x01010300
  33. #define DSPVERSZ 4
  34. #define HWSERNUMSZ 16
  35. #define SKUSZ 20
  36. #define EUISZ 8
  37. #define MODESZ 2
  38. #define CALVERSZ 2
  39. #define CALDATESZ 6
  40. // Pseudo Header structure
  41. typedef struct _PSEUDO_HDR
  42. {
  43. unsigned short length; // length of msg body
  44. unsigned char source; // hardware source id
  45. // Host = 0x10
  46. // Dsp = 0x20
  47. unsigned char destination; // hardware destination id (refer to source)
  48. unsigned char portdest; // software destination port id
  49. // Host = 0x00
  50. // Applicaton Broadcast = 0x10
  51. // Network Stack = 0x20
  52. // Dsp OAM = 0x80
  53. // Dsp Airlink = 0x90
  54. // Dsp Loader = 0xa0
  55. // Dsp MIP = 0xb0
  56. unsigned char portsrc; // software source port id (refer to portdest)
  57. unsigned short sh_str_id; // not used
  58. unsigned char control; // not used
  59. unsigned char rsvd1;
  60. unsigned char seq_num; // message sequence number
  61. unsigned char rsvd2;
  62. unsigned short qos_class; // not used
  63. unsigned short checksum; // pseudo header checksum
  64. } __attribute__ ((packed)) PSEUDO_HDR, *PPSEUDO_HDR;
  65. // Definitions to maintain compatibility between other platforms
  66. #define UCHAR u8
  67. #define USHORT u16
  68. #define ULONG u32
  69. #define BOOLEAN u8
  70. #define PULONG u32 *
  71. #define PUSHORT u16 *
  72. #define PUCHAR u8 *
  73. #define PCHAR u8 *
  74. #define UINT u32
  75. #define ELECTRABUZZ_ID 0 // ASIC ID for Electrabuzz
  76. #define MAGNEMITE_ID 0x1a01 // ASIC ID for Magnemite
  77. // MEMORY MAP common to both ELECTRABUZZ and MAGNEMITE
  78. #define FT1000_REG_DPRAM_ADDR 0x000E // DPADR - Dual Port Ram Indirect Address Register
  79. #define FT1000_REG_SUP_CTRL 0x0020 // HCTR - Host Control Register
  80. #define FT1000_REG_SUP_STAT 0x0022 // HSTAT - Host Status Register
  81. #define FT1000_REG_RESET 0x0024 // HCTR - Host Control Register
  82. #define FT1000_REG_SUP_ISR 0x0026 // HISR - Host Interrupt Status Register
  83. #define FT1000_REG_SUP_IMASK 0x0028 // HIMASK - Host Interrupt Mask
  84. #define FT1000_REG_DOORBELL 0x002a // DBELL - Door Bell Register
  85. #define FT1000_REG_ASIC_ID 0x002e // ASICID - ASIC Identification Number
  86. // (Electrabuzz=0 Magnemite=0x1A01)
  87. // MEMORY MAP FOR ELECTRABUZZ ASIC
  88. #define FT1000_REG_UFIFO_STAT 0x0000 // UFSR - Uplink FIFO status register
  89. #define FT1000_REG_UFIFO_BEG 0x0002 // UFBR - Uplink FIFO beginning register
  90. #define FT1000_REG_UFIFO_MID 0x0004 // UFMR - Uplink FIFO middle register
  91. #define FT1000_REG_UFIFO_END 0x0006 // UFER - Uplink FIFO end register
  92. #define FT1000_REG_DFIFO_STAT 0x0008 // DFSR - Downlink FIFO status register
  93. #define FT1000_REG_DFIFO 0x000A // DFR - Downlink FIFO Register
  94. #define FT1000_REG_DPRAM_DATA 0x000C // DPRAM - Dual Port Indirect Data Register
  95. #define FT1000_REG_WATERMARK 0x0010 // WMARK - Watermark Register
  96. // MEMORY MAP FOR MAGNEMITE
  97. #define FT1000_REG_MAG_UFDR 0x0000 // UFDR - Uplink FIFO Data Register (32-bits)
  98. #define FT1000_REG_MAG_UFDRL 0x0000 // UFDRL - Uplink FIFO Data Register low-word (16-bits)
  99. #define FT1000_REG_MAG_UFDRH 0x0002 // UFDRH - Uplink FIFO Data Register high-word (16-bits)
  100. #define FT1000_REG_MAG_UFER 0x0004 // UFER - Uplink FIFO End Register
  101. #define FT1000_REG_MAG_UFSR 0x0006 // UFSR - Uplink FIFO Status Register
  102. #define FT1000_REG_MAG_DFR 0x0008 // DFR - Downlink FIFO Register (32-bits)
  103. #define FT1000_REG_MAG_DFRL 0x0008 // DFRL - Downlink FIFO Register low-word (16-bits)
  104. #define FT1000_REG_MAG_DFRH 0x000a // DFRH - Downlink FIFO Register high-word (16-bits)
  105. #define FT1000_REG_MAG_DFSR 0x000c // DFSR - Downlink FIFO Status Register
  106. #define FT1000_REG_MAG_DPDATA 0x0010 // DPDATA - Dual Port RAM Indirect Data Register (32-bits)
  107. #define FT1000_REG_MAG_DPDATAL 0x0010 // DPDATAL - Dual Port RAM Indirect Data Register low-word (16-bits)
  108. #define FT1000_REG_MAG_DPDATAH 0x0012 // DPDATAH - Dual Port RAM Indirect Data Register high-word (16-bits)
  109. #define FT1000_REG_MAG_WATERMARK 0x002c // WMARK - Watermark Register
  110. // Reserved Dual Port RAM offsets for Electrabuzz
  111. #define FT1000_DPRAM_TX_BASE 0x0002 // Host to PC Card Messaging Area
  112. #define FT1000_DPRAM_RX_BASE 0x0800 // PC Card to Host Messaging Area
  113. #define FT1000_FIFO_LEN 0x7FC // total length for DSP FIFO tracking
  114. #define FT1000_HI_HO 0x7FE // heartbeat with HI/HO
  115. #define FT1000_DSP_STATUS 0xFFE // dsp status - non-zero is a request to reset dsp
  116. #define FT1000_DSP_LED 0xFFA // dsp led status for PAD device
  117. #define FT1000_DSP_CON_STATE 0xFF8 // DSP Connection Status Info
  118. #define FT1000_DPRAM_FEFE 0x002 // location for dsp ready indicator
  119. #define FT1000_DSP_TIMER0 0x1FF0 // Timer Field from Basestation
  120. #define FT1000_DSP_TIMER1 0x1FF2 // Timer Field from Basestation
  121. #define FT1000_DSP_TIMER2 0x1FF4 // Timer Field from Basestation
  122. #define FT1000_DSP_TIMER3 0x1FF6 // Timer Field from Basestation
  123. // Reserved Dual Port RAM offsets for Magnemite
  124. #define FT1000_DPRAM_MAG_TX_BASE 0x0000 // Host to PC Card Messaging Area
  125. #define FT1000_DPRAM_MAG_RX_BASE 0x0200 // PC Card to Host Messaging Area
  126. #define FT1000_MAG_FIFO_LEN 0x1FF // total length for DSP FIFO tracking
  127. #define FT1000_MAG_FIFO_LEN_INDX 0x1 // low-word index
  128. #define FT1000_MAG_HI_HO 0x1FF // heartbeat with HI/HO
  129. #define FT1000_MAG_HI_HO_INDX 0x0 // high-word index
  130. #define FT1000_MAG_DSP_LED 0x3FE // dsp led status for PAD device
  131. #define FT1000_MAG_DSP_LED_INDX 0x0 // dsp led status for PAD device
  132. #define FT1000_MAG_DSP_CON_STATE 0x3FE // DSP Connection Status Info
  133. #define FT1000_MAG_DSP_CON_STATE_INDX 0x1 // DSP Connection Status Info
  134. #define FT1000_MAG_DPRAM_FEFE 0x000 // location for dsp ready indicator
  135. #define FT1000_MAG_DPRAM_FEFE_INDX 0x0 // location for dsp ready indicator
  136. #define FT1000_MAG_DSP_TIMER0 0x3FC // Timer Field from Basestation
  137. #define FT1000_MAG_DSP_TIMER0_INDX 0x1
  138. #define FT1000_MAG_DSP_TIMER1 0x3FC // Timer Field from Basestation
  139. #define FT1000_MAG_DSP_TIMER1_INDX 0x0
  140. #define FT1000_MAG_DSP_TIMER2 0x3FD // Timer Field from Basestation
  141. #define FT1000_MAG_DSP_TIMER2_INDX 0x1
  142. #define FT1000_MAG_DSP_TIMER3 0x3FD // Timer Field from Basestation
  143. #define FT1000_MAG_DSP_TIMER3_INDX 0x0
  144. #define FT1000_MAG_TOTAL_LEN 0x200
  145. #define FT1000_MAG_TOTAL_LEN_INDX 0x1
  146. #define FT1000_MAG_PH_LEN 0x200
  147. #define FT1000_MAG_PH_LEN_INDX 0x0
  148. #define FT1000_MAG_PORT_ID 0x201
  149. #define FT1000_MAG_PORT_ID_INDX 0x0
  150. #define HOST_INTF_LE 0x0 // Host interface little endian mode
  151. #define HOST_INTF_BE 0x1 // Host interface big endian mode
  152. // PC Card to Host Doorbell assignments
  153. #define FT1000_DB_DPRAM_RX 0x0001 // this value indicates that DSP has
  154. // data for host in DPRAM
  155. #define FT1000_ASIC_RESET_REQ 0x0004 // DSP requesting host to reset the ASIC
  156. #define FT1000_DSP_ASIC_RESET 0x0008 // DSP indicating host that it will reset the ASIC
  157. #define FT1000_DB_COND_RESET 0x0010 // DSP request for a card reset.
  158. // Host to PC Card Doorbell assignments
  159. #define FT1000_DB_DPRAM_TX 0x0100 // this value indicates that host has
  160. // data for DSP in DPRAM.
  161. #define FT1000_ASIC_RESET_DSP 0x0400 // Responds to FT1000_ASIC_RESET_REQ
  162. #define FT1000_DB_HB 0x1000 // Indicates that supervisor
  163. // has a heartbeat message for DSP.
  164. #define FT1000_DPRAM_BASE 0x0000 // Dual Port RAM starting offset
  165. #define hi 0x6869 // PC Card heartbeat values
  166. #define ho 0x686f // PC Card heartbeat values
  167. // Magnemite specific defines
  168. #define hi_mag 0x6968 // Byte swap hi to avoid additional system call
  169. #define ho_mag 0x6f68 // Byte swap ho to avoid additional system call
  170. //
  171. // Bit field definitions for Host Interrupt Status Register
  172. //
  173. // Indicate the cause of an interrupt.
  174. //
  175. #define ISR_EMPTY 0x00 // no bits set
  176. #define ISR_DOORBELL_ACK 0x01 // Doorbell acknowledge from DSP
  177. #define ISR_DOORBELL_PEND 0x02 // Doorbell pending from DSP
  178. #define ISR_RCV 0x04 // Packet available in Downlink FIFO
  179. #define ISR_WATERMARK 0x08 // Watermark requirements satisfied
  180. // Bit field definition for Host Interrupt Mask
  181. #define ISR_MASK_NONE 0x0000 // no bits set
  182. #define ISR_MASK_DOORBELL_ACK 0x0001 // Doorbell acknowledge mask
  183. #define ISR_MASK_DOORBELL_PEND 0x0002 // Doorbell pending mask
  184. #define ISR_MASK_RCV 0x0004 // Downlink Packet available mask
  185. #define ISR_MASK_WATERMARK 0x0008 // Watermark interrupt mask
  186. #define ISR_MASK_ALL 0xffff // Mask all interrupts
  187. // Bit field definition for Host Control Register
  188. #define DSP_RESET_BIT 0x0001 // Bit field to control dsp reset state
  189. // (0 = out of reset 1 = reset)
  190. #define ASIC_RESET_BIT 0x0002 // Bit field to control ASIC reset state
  191. // (0 = out of reset 1 = reset)
  192. // Default interrupt mask (Enable Doorbell pending and Packet available interrupts)
  193. #define ISR_DEFAULT_MASK 0x7ff9
  194. // Application specific IDs
  195. #define DSPID 0x20
  196. #define HOSTID 0x10
  197. #define DSPAIRID 0x90
  198. #define DRIVERID 0x00
  199. #define NETWORKID 0x20
  200. // Size of DPRAM Message
  201. #define MAX_CMD_SQSIZE 1780
  202. #define ENET_MAX_SIZE 1514
  203. #define ENET_HEADER_SIZE 14
  204. #define SLOWQ_TYPE 0
  205. #define FASTQ_TYPE 1
  206. #define MAX_DSP_SESS_REC 1024
  207. #define DSP_QID_OFFSET 4
  208. #define PSEUDOSZ 16
  209. #define PSEUDOSZWRD 8
  210. // Maximum number of occurrence of pseudo header errors before resetting PC Card.
  211. #define MAX_PH_ERR 300
  212. // Driver message types
  213. #define MEDIA_STATE 0x0010
  214. #define TIME_UPDATE 0x0020
  215. #define DSP_PROVISION 0x0030
  216. #define DSP_INIT_MSG 0x0050
  217. #define DSP_HIBERNATE 0x0060
  218. #define DSP_STORE_INFO 0x0070
  219. #define DSP_GET_INFO 0x0071
  220. #define GET_DRV_ERR_RPT_MSG 0x0073
  221. #define RSP_DRV_ERR_RPT_MSG 0x0074
  222. // Driver Error Messages for DSP
  223. #define DSP_HB_INFO 0x7ef0
  224. #define DSP_FIFO_INFO 0x7ef1
  225. #define DSP_CONDRESET_INFO 0x7ef2
  226. #define DSP_CMDLEN_INFO 0x7ef3
  227. #define DSP_CMDPHCKSUM_INFO 0x7ef4
  228. #define DSP_PKTPHCKSUM_INFO 0x7ef5
  229. #define DSP_PKTLEN_INFO 0x7ef6
  230. #define DSP_USER_RESET 0x7ef7
  231. #define FIFO_FLUSH_MAXLIMIT 0x7ef8
  232. #define FIFO_FLUSH_BADCNT 0x7ef9
  233. #define FIFO_ZERO_LEN 0x7efa
  234. #define HOST_QID_OFFSET 5
  235. #define QTYPE_OFFSET 13
  236. #define SUCCESS 0x00
  237. #define FAILURE 0x01
  238. #define TRUE 0x1
  239. #define FALSE 0x0
  240. #define MAX_NUM_APP 6
  241. #define MAXIMUM_ASIC_HB_CNT 15
  242. typedef struct _DRVMSG {
  243. PSEUDO_HDR pseudo;
  244. u16 type;
  245. u16 length;
  246. u8 data[0];
  247. } __attribute__ ((packed)) DRVMSG, *PDRVMSG;
  248. typedef struct _MEDIAMSG {
  249. PSEUDO_HDR pseudo;
  250. u16 type;
  251. u16 length;
  252. u16 state;
  253. u32 ip_addr;
  254. u32 net_mask;
  255. u32 gateway;
  256. u32 dns_1;
  257. u32 dns_2;
  258. } __attribute__ ((packed)) MEDIAMSG, *PMEDIAMSG;
  259. typedef struct _TIMEMSG {
  260. PSEUDO_HDR pseudo;
  261. u16 type;
  262. u16 length;
  263. u8 timeval[8];
  264. } __attribute__ ((packed)) TIMEMSG, *PTIMEMSG;
  265. typedef struct _DSPINITMSG {
  266. PSEUDO_HDR pseudo;
  267. u16 type;
  268. u16 length;
  269. u8 DspVer[DSPVERSZ]; // DSP version number
  270. u8 HwSerNum[HWSERNUMSZ]; // Hardware Serial Number
  271. u8 Sku[SKUSZ]; // SKU
  272. u8 eui64[EUISZ]; // EUI64
  273. u8 ProductMode[MODESZ]; // Product Mode (Market/Production)
  274. u8 RfCalVer[CALVERSZ]; // Rf Calibration version
  275. u8 RfCalDate[CALDATESZ]; // Rf Calibration date
  276. } __attribute__ ((packed)) DSPINITMSG, *PDSPINITMSG;
  277. typedef struct _DSPHIBERNATE {
  278. PSEUDO_HDR pseudo;
  279. u16 type;
  280. u16 length;
  281. u32 timeout;
  282. u16 sess_info[0];
  283. } DSPHIBERNATE, *PDSPHIBERNATE;
  284. typedef struct _APP_INFO_BLOCK
  285. {
  286. u32 fileobject; // Application's file object
  287. u16 app_id; // Application id
  288. } APP_INFO_BLOCK, *PAPP_INFO_BLOCK;
  289. typedef struct _PROV_RECORD {
  290. struct list_head list;
  291. u8 *pprov_data;
  292. } PROV_RECORD, *PPROV_RECORD;
  293. typedef struct _FT1000_INFO {
  294. struct net_device_stats stats;
  295. u16 DrvErrNum;
  296. u16 AsicID;
  297. int ASICResetNum;
  298. int DspAsicReset;
  299. int PktIntfErr;
  300. int DSPResetNum;
  301. int NumIOCTLBufs;
  302. int IOCTLBufLvl;
  303. int DeviceCreated;
  304. int CardReady;
  305. int DspHibernateFlag;
  306. int DSPReady;
  307. u8 DeviceName[15];
  308. int DeviceMajor;
  309. int registered;
  310. int mediastate;
  311. u16 packetseqnum;
  312. u8 squeseqnum; // sequence number on slow queue
  313. spinlock_t dpram_lock;
  314. u16 CurrentInterruptEnableMask;
  315. int InterruptsEnabled;
  316. u16 fifo_cnt;
  317. u8 DspVer[DSPVERSZ]; // DSP version number
  318. u8 HwSerNum[HWSERNUMSZ]; // Hardware Serial Number
  319. u8 Sku[SKUSZ]; // SKU
  320. u8 eui64[EUISZ]; // EUI64
  321. time_t ConTm; // Connection Time
  322. u16 LedStat;
  323. u16 ConStat;
  324. u16 ProgConStat;
  325. u8 ProductMode[MODESZ];
  326. u8 RfCalVer[CALVERSZ];
  327. u8 RfCalDate[CALDATESZ];
  328. u16 DSP_TIME[4];
  329. struct list_head prov_list;
  330. int appcnt;
  331. APP_INFO_BLOCK app_info[MAX_NUM_APP];
  332. u16 DSPInfoBlklen;
  333. u16 DrvMsgPend;
  334. int (*ft1000_reset)(void *);
  335. void *link;
  336. u16 DSPInfoBlk[MAX_DSP_SESS_REC];
  337. union {
  338. u16 Rec[MAX_DSP_SESS_REC];
  339. u32 MagRec[MAX_DSP_SESS_REC/2];
  340. } DSPSess;
  341. struct proc_dir_entry *proc_ft1000;
  342. char netdevname[IFNAMSIZ];
  343. } FT1000_INFO, *PFT1000_INFO;
  344. typedef struct _DPRAM_BLK {
  345. struct list_head list;
  346. u16 *pbuffer;
  347. } __attribute__ ((packed)) DPRAM_BLK, *PDPRAM_BLK;
  348. extern u16 ft1000_read_dpram (struct net_device *dev, int offset);
  349. extern void card_bootload(struct net_device *dev);
  350. extern u16 ft1000_read_dpram_mag_16 (struct net_device *dev, int offset, int Index);
  351. extern u32 ft1000_read_dpram_mag_32 (struct net_device *dev, int offset);
  352. void ft1000_write_dpram_mag_32 (struct net_device *dev, int offset, u32 value);
  353. #endif // _FT1000H_