/drivers/staging/cx25821/cx25821-video-upstream.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2 · C · 889 lines · 657 code · 162 blank · 70 comment · 105 complexity · 193dbf42b0bfd3245ae3cbee76fd8e97 MD5 · raw file

  1. /*
  2. * Driver for the Conexant CX25821 PCIe bridge
  3. *
  4. * Copyright (C) 2009 Conexant Systems Inc.
  5. * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. *
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  23. #include "cx25821-video.h"
  24. #include "cx25821-video-upstream.h"
  25. #include <linux/fs.h>
  26. #include <linux/errno.h>
  27. #include <linux/kernel.h>
  28. #include <linux/init.h>
  29. #include <linux/module.h>
  30. #include <linux/syscalls.h>
  31. #include <linux/file.h>
  32. #include <linux/fcntl.h>
  33. #include <linux/slab.h>
  34. #include <linux/uaccess.h>
  35. MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
  36. MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
  37. MODULE_LICENSE("GPL");
  38. static int _intr_msk =
  39. FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
  40. int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
  41. struct sram_channel *ch,
  42. unsigned int bpl, u32 risc)
  43. {
  44. unsigned int i, lines;
  45. u32 cdt;
  46. if (ch->cmds_start == 0) {
  47. cx_write(ch->ptr1_reg, 0);
  48. cx_write(ch->ptr2_reg, 0);
  49. cx_write(ch->cnt2_reg, 0);
  50. cx_write(ch->cnt1_reg, 0);
  51. return 0;
  52. }
  53. bpl = (bpl + 7) & ~7; /* alignment */
  54. cdt = ch->cdt;
  55. lines = ch->fifo_size / bpl;
  56. if (lines > 4)
  57. lines = 4;
  58. BUG_ON(lines < 2);
  59. /* write CDT */
  60. for (i = 0; i < lines; i++) {
  61. cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
  62. cx_write(cdt + 16 * i + 4, 0);
  63. cx_write(cdt + 16 * i + 8, 0);
  64. cx_write(cdt + 16 * i + 12, 0);
  65. }
  66. /* write CMDS */
  67. cx_write(ch->cmds_start + 0, risc);
  68. cx_write(ch->cmds_start + 4, 0);
  69. cx_write(ch->cmds_start + 8, cdt);
  70. cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
  71. cx_write(ch->cmds_start + 16, ch->ctrl_start);
  72. cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
  73. for (i = 24; i < 80; i += 4)
  74. cx_write(ch->cmds_start + i, 0);
  75. /* fill registers */
  76. cx_write(ch->ptr1_reg, ch->fifo_start);
  77. cx_write(ch->ptr2_reg, cdt);
  78. cx_write(ch->cnt2_reg, (lines * 16) >> 3);
  79. cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
  80. return 0;
  81. }
  82. static __le32 *cx25821_update_riscprogram(struct cx25821_dev *dev,
  83. __le32 *rp, unsigned int offset,
  84. unsigned int bpl, u32 sync_line,
  85. unsigned int lines, int fifo_enable,
  86. int field_type)
  87. {
  88. unsigned int line, i;
  89. int dist_betwn_starts = bpl * 2;
  90. *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
  91. if (USE_RISC_NOOP_VIDEO) {
  92. for (i = 0; i < NUM_NO_OPS; i++)
  93. *(rp++) = cpu_to_le32(RISC_NOOP);
  94. }
  95. /* scan lines */
  96. for (line = 0; line < lines; line++) {
  97. *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
  98. *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr + offset);
  99. *(rp++) = cpu_to_le32(0); /* bits 63-32 */
  100. if ((lines <= NTSC_FIELD_HEIGHT)
  101. || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
  102. offset += dist_betwn_starts;
  103. }
  104. }
  105. return rp;
  106. }
  107. static __le32 *cx25821_risc_field_upstream(struct cx25821_dev *dev, __le32 * rp,
  108. dma_addr_t databuf_phys_addr,
  109. unsigned int offset, u32 sync_line,
  110. unsigned int bpl, unsigned int lines,
  111. int fifo_enable, int field_type)
  112. {
  113. unsigned int line, i;
  114. struct sram_channel *sram_ch =
  115. dev->channels[dev->_channel_upstream_select].sram_channels;
  116. int dist_betwn_starts = bpl * 2;
  117. /* sync instruction */
  118. if (sync_line != NO_SYNC_LINE)
  119. *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
  120. if (USE_RISC_NOOP_VIDEO) {
  121. for (i = 0; i < NUM_NO_OPS; i++)
  122. *(rp++) = cpu_to_le32(RISC_NOOP);
  123. }
  124. /* scan lines */
  125. for (line = 0; line < lines; line++) {
  126. *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
  127. *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
  128. *(rp++) = cpu_to_le32(0); /* bits 63-32 */
  129. if ((lines <= NTSC_FIELD_HEIGHT)
  130. || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC))
  131. /* to skip the other field line */
  132. offset += dist_betwn_starts;
  133. /* check if we need to enable the FIFO after the first 4 lines
  134. * For the upstream video channel, the risc engine will enable
  135. * the FIFO. */
  136. if (fifo_enable && line == 3) {
  137. *(rp++) = RISC_WRITECR;
  138. *(rp++) = sram_ch->dma_ctl;
  139. *(rp++) = FLD_VID_FIFO_EN;
  140. *(rp++) = 0x00000001;
  141. }
  142. }
  143. return rp;
  144. }
  145. int cx25821_risc_buffer_upstream(struct cx25821_dev *dev,
  146. struct pci_dev *pci,
  147. unsigned int top_offset,
  148. unsigned int bpl, unsigned int lines)
  149. {
  150. __le32 *rp;
  151. int fifo_enable = 0;
  152. /* get line count for single field */
  153. int singlefield_lines = lines >> 1;
  154. int odd_num_lines = singlefield_lines;
  155. int frame = 0;
  156. int frame_size = 0;
  157. int databuf_offset = 0;
  158. int risc_program_size = 0;
  159. int risc_flag = RISC_CNT_RESET;
  160. unsigned int bottom_offset = bpl;
  161. dma_addr_t risc_phys_jump_addr;
  162. if (dev->_isNTSC) {
  163. odd_num_lines = singlefield_lines + 1;
  164. risc_program_size = FRAME1_VID_PROG_SIZE;
  165. frame_size =
  166. (bpl ==
  167. Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
  168. FRAME_SIZE_NTSC_Y422;
  169. } else {
  170. risc_program_size = PAL_VID_PROG_SIZE;
  171. frame_size =
  172. (bpl ==
  173. Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
  174. }
  175. /* Virtual address of Risc buffer program */
  176. rp = dev->_dma_virt_addr;
  177. for (frame = 0; frame < NUM_FRAMES; frame++) {
  178. databuf_offset = frame_size * frame;
  179. if (UNSET != top_offset) {
  180. fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
  181. rp = cx25821_risc_field_upstream(dev, rp,
  182. dev->
  183. _data_buf_phys_addr +
  184. databuf_offset,
  185. top_offset, 0, bpl,
  186. odd_num_lines,
  187. fifo_enable,
  188. ODD_FIELD);
  189. }
  190. fifo_enable = FIFO_DISABLE;
  191. /* Even Field */
  192. rp = cx25821_risc_field_upstream(dev, rp,
  193. dev->_data_buf_phys_addr +
  194. databuf_offset, bottom_offset,
  195. 0x200, bpl, singlefield_lines,
  196. fifo_enable, EVEN_FIELD);
  197. if (frame == 0) {
  198. risc_flag = RISC_CNT_RESET;
  199. risc_phys_jump_addr =
  200. dev->_dma_phys_start_addr + risc_program_size;
  201. } else {
  202. risc_phys_jump_addr = dev->_dma_phys_start_addr;
  203. risc_flag = RISC_CNT_INC;
  204. }
  205. /* Loop to 2ndFrameRISC or to Start of Risc
  206. * program & generate IRQ
  207. */
  208. *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
  209. *(rp++) = cpu_to_le32(risc_phys_jump_addr);
  210. *(rp++) = cpu_to_le32(0);
  211. }
  212. return 0;
  213. }
  214. void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev)
  215. {
  216. struct sram_channel *sram_ch =
  217. dev->channels[VID_UPSTREAM_SRAM_CHANNEL_I].sram_channels;
  218. u32 tmp = 0;
  219. if (!dev->_is_running) {
  220. pr_info("No video file is currently running so return!\n");
  221. return;
  222. }
  223. /* Disable RISC interrupts */
  224. tmp = cx_read(sram_ch->int_msk);
  225. cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
  226. /* Turn OFF risc and fifo enable */
  227. tmp = cx_read(sram_ch->dma_ctl);
  228. cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
  229. /* Clear data buffer memory */
  230. if (dev->_data_buf_virt_addr)
  231. memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
  232. dev->_is_running = 0;
  233. dev->_is_first_frame = 0;
  234. dev->_frame_count = 0;
  235. dev->_file_status = END_OF_FILE;
  236. kfree(dev->_irq_queues);
  237. dev->_irq_queues = NULL;
  238. kfree(dev->_filename);
  239. tmp = cx_read(VID_CH_MODE_SEL);
  240. cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
  241. }
  242. void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev)
  243. {
  244. if (dev->_is_running)
  245. cx25821_stop_upstream_video_ch1(dev);
  246. if (dev->_dma_virt_addr) {
  247. pci_free_consistent(dev->pci, dev->_risc_size,
  248. dev->_dma_virt_addr, dev->_dma_phys_addr);
  249. dev->_dma_virt_addr = NULL;
  250. }
  251. if (dev->_data_buf_virt_addr) {
  252. pci_free_consistent(dev->pci, dev->_data_buf_size,
  253. dev->_data_buf_virt_addr,
  254. dev->_data_buf_phys_addr);
  255. dev->_data_buf_virt_addr = NULL;
  256. }
  257. }
  258. int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch)
  259. {
  260. struct file *myfile;
  261. int frame_index_temp = dev->_frame_index;
  262. int i = 0;
  263. int line_size =
  264. (dev->_pixel_format ==
  265. PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
  266. int frame_size = 0;
  267. int frame_offset = 0;
  268. ssize_t vfs_read_retval = 0;
  269. char mybuf[line_size];
  270. loff_t file_offset;
  271. loff_t pos;
  272. mm_segment_t old_fs;
  273. if (dev->_file_status == END_OF_FILE)
  274. return 0;
  275. if (dev->_isNTSC) {
  276. frame_size =
  277. (line_size ==
  278. Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
  279. FRAME_SIZE_NTSC_Y422;
  280. } else {
  281. frame_size =
  282. (line_size ==
  283. Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
  284. }
  285. frame_offset = (frame_index_temp > 0) ? frame_size : 0;
  286. file_offset = dev->_frame_count * frame_size;
  287. myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
  288. if (IS_ERR(myfile)) {
  289. const int open_errno = -PTR_ERR(myfile);
  290. pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
  291. __func__, dev->_filename, open_errno);
  292. return PTR_ERR(myfile);
  293. } else {
  294. if (!(myfile->f_op)) {
  295. pr_err("%s(): File has no file operations registered!\n",
  296. __func__);
  297. filp_close(myfile, NULL);
  298. return -EIO;
  299. }
  300. if (!myfile->f_op->read) {
  301. pr_err("%s(): File has no READ operations registered!\n",
  302. __func__);
  303. filp_close(myfile, NULL);
  304. return -EIO;
  305. }
  306. pos = myfile->f_pos;
  307. old_fs = get_fs();
  308. set_fs(KERNEL_DS);
  309. for (i = 0; i < dev->_lines_count; i++) {
  310. pos = file_offset;
  311. vfs_read_retval =
  312. vfs_read(myfile, mybuf, line_size, &pos);
  313. if (vfs_read_retval > 0 && vfs_read_retval == line_size
  314. && dev->_data_buf_virt_addr != NULL) {
  315. memcpy((void *)(dev->_data_buf_virt_addr +
  316. frame_offset / 4), mybuf,
  317. vfs_read_retval);
  318. }
  319. file_offset += vfs_read_retval;
  320. frame_offset += vfs_read_retval;
  321. if (vfs_read_retval < line_size) {
  322. pr_info("Done: exit %s() since no more bytes to read from Video file\n",
  323. __func__);
  324. break;
  325. }
  326. }
  327. if (i > 0)
  328. dev->_frame_count++;
  329. dev->_file_status =
  330. (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
  331. set_fs(old_fs);
  332. filp_close(myfile, NULL);
  333. }
  334. return 0;
  335. }
  336. static void cx25821_vidups_handler(struct work_struct *work)
  337. {
  338. struct cx25821_dev *dev =
  339. container_of(work, struct cx25821_dev, _irq_work_entry);
  340. if (!dev) {
  341. pr_err("ERROR %s(): since container_of(work_struct) FAILED!\n",
  342. __func__);
  343. return;
  344. }
  345. cx25821_get_frame(dev,
  346. dev->channels[dev->_channel_upstream_select].
  347. sram_channels);
  348. }
  349. int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch)
  350. {
  351. struct file *myfile;
  352. int i = 0, j = 0;
  353. int line_size =
  354. (dev->_pixel_format ==
  355. PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
  356. ssize_t vfs_read_retval = 0;
  357. char mybuf[line_size];
  358. loff_t pos;
  359. loff_t offset = (unsigned long)0;
  360. mm_segment_t old_fs;
  361. myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
  362. if (IS_ERR(myfile)) {
  363. const int open_errno = -PTR_ERR(myfile);
  364. pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
  365. __func__, dev->_filename, open_errno);
  366. return PTR_ERR(myfile);
  367. } else {
  368. if (!(myfile->f_op)) {
  369. pr_err("%s(): File has no file operations registered!\n",
  370. __func__);
  371. filp_close(myfile, NULL);
  372. return -EIO;
  373. }
  374. if (!myfile->f_op->read) {
  375. pr_err("%s(): File has no READ operations registered! Returning\n",
  376. __func__);
  377. filp_close(myfile, NULL);
  378. return -EIO;
  379. }
  380. pos = myfile->f_pos;
  381. old_fs = get_fs();
  382. set_fs(KERNEL_DS);
  383. for (j = 0; j < NUM_FRAMES; j++) {
  384. for (i = 0; i < dev->_lines_count; i++) {
  385. pos = offset;
  386. vfs_read_retval =
  387. vfs_read(myfile, mybuf, line_size, &pos);
  388. if (vfs_read_retval > 0
  389. && vfs_read_retval == line_size
  390. && dev->_data_buf_virt_addr != NULL) {
  391. memcpy((void *)(dev->
  392. _data_buf_virt_addr +
  393. offset / 4), mybuf,
  394. vfs_read_retval);
  395. }
  396. offset += vfs_read_retval;
  397. if (vfs_read_retval < line_size) {
  398. pr_info("Done: exit %s() since no more bytes to read from Video file\n",
  399. __func__);
  400. break;
  401. }
  402. }
  403. if (i > 0)
  404. dev->_frame_count++;
  405. if (vfs_read_retval < line_size)
  406. break;
  407. }
  408. dev->_file_status =
  409. (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
  410. set_fs(old_fs);
  411. myfile->f_pos = 0;
  412. filp_close(myfile, NULL);
  413. }
  414. return 0;
  415. }
  416. int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev,
  417. struct sram_channel *sram_ch, int bpl)
  418. {
  419. int ret = 0;
  420. dma_addr_t dma_addr;
  421. dma_addr_t data_dma_addr;
  422. if (dev->_dma_virt_addr != NULL) {
  423. pci_free_consistent(dev->pci, dev->upstream_riscbuf_size,
  424. dev->_dma_virt_addr, dev->_dma_phys_addr);
  425. }
  426. dev->_dma_virt_addr =
  427. pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size,
  428. &dma_addr);
  429. dev->_dma_virt_start_addr = dev->_dma_virt_addr;
  430. dev->_dma_phys_start_addr = dma_addr;
  431. dev->_dma_phys_addr = dma_addr;
  432. dev->_risc_size = dev->upstream_riscbuf_size;
  433. if (!dev->_dma_virt_addr) {
  434. pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
  435. return -ENOMEM;
  436. }
  437. /* Clear memory at address */
  438. memset(dev->_dma_virt_addr, 0, dev->_risc_size);
  439. if (dev->_data_buf_virt_addr != NULL) {
  440. pci_free_consistent(dev->pci, dev->upstream_databuf_size,
  441. dev->_data_buf_virt_addr,
  442. dev->_data_buf_phys_addr);
  443. }
  444. /* For Video Data buffer allocation */
  445. dev->_data_buf_virt_addr =
  446. pci_alloc_consistent(dev->pci, dev->upstream_databuf_size,
  447. &data_dma_addr);
  448. dev->_data_buf_phys_addr = data_dma_addr;
  449. dev->_data_buf_size = dev->upstream_databuf_size;
  450. if (!dev->_data_buf_virt_addr) {
  451. pr_err("FAILED to allocate memory for data buffer! Returning\n");
  452. return -ENOMEM;
  453. }
  454. /* Clear memory at address */
  455. memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
  456. ret = cx25821_openfile(dev, sram_ch);
  457. if (ret < 0)
  458. return ret;
  459. /* Create RISC programs */
  460. ret =
  461. cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl,
  462. dev->_lines_count);
  463. if (ret < 0) {
  464. pr_info("Failed creating Video Upstream Risc programs!\n");
  465. goto error;
  466. }
  467. return 0;
  468. error:
  469. return ret;
  470. }
  471. int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num,
  472. u32 status)
  473. {
  474. u32 int_msk_tmp;
  475. struct sram_channel *channel = dev->channels[chan_num].sram_channels;
  476. int singlefield_lines = NTSC_FIELD_HEIGHT;
  477. int line_size_in_bytes = Y422_LINE_SZ;
  478. int odd_risc_prog_size = 0;
  479. dma_addr_t risc_phys_jump_addr;
  480. __le32 *rp;
  481. if (status & FLD_VID_SRC_RISC1) {
  482. /* We should only process one program per call */
  483. u32 prog_cnt = cx_read(channel->gpcnt);
  484. /* Since we've identified our IRQ, clear our bits from the
  485. * interrupt mask and interrupt status registers */
  486. int_msk_tmp = cx_read(channel->int_msk);
  487. cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
  488. cx_write(channel->int_stat, _intr_msk);
  489. spin_lock(&dev->slock);
  490. dev->_frame_index = prog_cnt;
  491. queue_work(dev->_irq_queues, &dev->_irq_work_entry);
  492. if (dev->_is_first_frame) {
  493. dev->_is_first_frame = 0;
  494. if (dev->_isNTSC) {
  495. singlefield_lines += 1;
  496. odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
  497. } else {
  498. singlefield_lines = PAL_FIELD_HEIGHT;
  499. odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
  500. }
  501. if (dev->_dma_virt_start_addr != NULL) {
  502. line_size_in_bytes =
  503. (dev->_pixel_format ==
  504. PIXEL_FRMT_411) ? Y411_LINE_SZ :
  505. Y422_LINE_SZ;
  506. risc_phys_jump_addr =
  507. dev->_dma_phys_start_addr +
  508. odd_risc_prog_size;
  509. rp = cx25821_update_riscprogram(dev,
  510. dev->
  511. _dma_virt_start_addr,
  512. TOP_OFFSET,
  513. line_size_in_bytes,
  514. 0x0,
  515. singlefield_lines,
  516. FIFO_DISABLE,
  517. ODD_FIELD);
  518. /* Jump to Even Risc program of 1st Frame */
  519. *(rp++) = cpu_to_le32(RISC_JUMP);
  520. *(rp++) = cpu_to_le32(risc_phys_jump_addr);
  521. *(rp++) = cpu_to_le32(0);
  522. }
  523. }
  524. spin_unlock(&dev->slock);
  525. } else {
  526. if (status & FLD_VID_SRC_UF)
  527. pr_err("%s(): Video Received Underflow Error Interrupt!\n",
  528. __func__);
  529. if (status & FLD_VID_SRC_SYNC)
  530. pr_err("%s(): Video Received Sync Error Interrupt!\n",
  531. __func__);
  532. if (status & FLD_VID_SRC_OPC_ERR)
  533. pr_err("%s(): Video Received OpCode Error Interrupt!\n",
  534. __func__);
  535. }
  536. if (dev->_file_status == END_OF_FILE) {
  537. pr_err("EOF Channel 1 Framecount = %d\n", dev->_frame_count);
  538. return -1;
  539. }
  540. /* ElSE, set the interrupt mask register, re-enable irq. */
  541. int_msk_tmp = cx_read(channel->int_msk);
  542. cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
  543. return 0;
  544. }
  545. static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
  546. {
  547. struct cx25821_dev *dev = dev_id;
  548. u32 msk_stat, vid_status;
  549. int handled = 0;
  550. int channel_num = 0;
  551. struct sram_channel *sram_ch;
  552. if (!dev)
  553. return -1;
  554. channel_num = VID_UPSTREAM_SRAM_CHANNEL_I;
  555. sram_ch = dev->channels[channel_num].sram_channels;
  556. msk_stat = cx_read(sram_ch->int_mstat);
  557. vid_status = cx_read(sram_ch->int_stat);
  558. /* Only deal with our interrupt */
  559. if (vid_status) {
  560. handled =
  561. cx25821_video_upstream_irq(dev, channel_num, vid_status);
  562. }
  563. if (handled < 0)
  564. cx25821_stop_upstream_video_ch1(dev);
  565. else
  566. handled += handled;
  567. return IRQ_RETVAL(handled);
  568. }
  569. void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch,
  570. int pix_format)
  571. {
  572. int width = WIDTH_D1;
  573. int height = dev->_lines_count;
  574. int num_lines, odd_num_lines;
  575. u32 value;
  576. int vip_mode = OUTPUT_FRMT_656;
  577. value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
  578. value &= 0xFFFFFFEF;
  579. value |= dev->_isNTSC ? 0 : 0x10;
  580. cx_write(ch->vid_fmt_ctl, value);
  581. /* set number of active pixels in each line.
  582. * Default is 720 pixels in both NTSC and PAL format */
  583. cx_write(ch->vid_active_ctl1, width);
  584. num_lines = (height / 2) & 0x3FF;
  585. odd_num_lines = num_lines;
  586. if (dev->_isNTSC)
  587. odd_num_lines += 1;
  588. value = (num_lines << 16) | odd_num_lines;
  589. /* set number of active lines in field 0 (top) and field 1 (bottom) */
  590. cx_write(ch->vid_active_ctl2, value);
  591. cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
  592. }
  593. int cx25821_start_video_dma_upstream(struct cx25821_dev *dev,
  594. struct sram_channel *sram_ch)
  595. {
  596. u32 tmp = 0;
  597. int err = 0;
  598. /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
  599. * channel A-C
  600. */
  601. tmp = cx_read(VID_CH_MODE_SEL);
  602. cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
  603. /* Set the physical start address of the RISC program in the initial
  604. * program counter(IPC) member of the cmds.
  605. */
  606. cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr);
  607. /* Risc IPC High 64 bits 63-32 */
  608. cx_write(sram_ch->cmds_start + 4, 0);
  609. /* reset counter */
  610. cx_write(sram_ch->gpcnt_ctl, 3);
  611. /* Clear our bits from the interrupt status register. */
  612. cx_write(sram_ch->int_stat, _intr_msk);
  613. /* Set the interrupt mask register, enable irq. */
  614. cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
  615. tmp = cx_read(sram_ch->int_msk);
  616. cx_write(sram_ch->int_msk, tmp |= _intr_msk);
  617. err =
  618. request_irq(dev->pci->irq, cx25821_upstream_irq,
  619. IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
  620. if (err < 0) {
  621. pr_err("%s: can't get upstream IRQ %d\n",
  622. dev->name, dev->pci->irq);
  623. goto fail_irq;
  624. }
  625. /* Start the DMA engine */
  626. tmp = cx_read(sram_ch->dma_ctl);
  627. cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
  628. dev->_is_running = 1;
  629. dev->_is_first_frame = 1;
  630. return 0;
  631. fail_irq:
  632. cx25821_dev_unregister(dev);
  633. return err;
  634. }
  635. int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select,
  636. int pixel_format)
  637. {
  638. struct sram_channel *sram_ch;
  639. u32 tmp;
  640. int retval = 0;
  641. int err = 0;
  642. int data_frame_size = 0;
  643. int risc_buffer_size = 0;
  644. int str_length = 0;
  645. if (dev->_is_running) {
  646. pr_info("Video Channel is still running so return!\n");
  647. return 0;
  648. }
  649. dev->_channel_upstream_select = channel_select;
  650. sram_ch = dev->channels[channel_select].sram_channels;
  651. INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler);
  652. dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue");
  653. if (!dev->_irq_queues) {
  654. pr_err("create_singlethread_workqueue() for Video FAILED!\n");
  655. return -ENOMEM;
  656. }
  657. /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
  658. * channel A-C
  659. */
  660. tmp = cx_read(VID_CH_MODE_SEL);
  661. cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
  662. dev->_is_running = 0;
  663. dev->_frame_count = 0;
  664. dev->_file_status = RESET_STATUS;
  665. dev->_lines_count = dev->_isNTSC ? 480 : 576;
  666. dev->_pixel_format = pixel_format;
  667. dev->_line_size =
  668. (dev->_pixel_format ==
  669. PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
  670. data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
  671. risc_buffer_size =
  672. dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
  673. if (dev->input_filename) {
  674. str_length = strlen(dev->input_filename);
  675. dev->_filename = kmalloc(str_length + 1, GFP_KERNEL);
  676. if (!dev->_filename)
  677. goto error;
  678. memcpy(dev->_filename, dev->input_filename, str_length + 1);
  679. } else {
  680. str_length = strlen(dev->_defaultname);
  681. dev->_filename = kmalloc(str_length + 1, GFP_KERNEL);
  682. if (!dev->_filename)
  683. goto error;
  684. memcpy(dev->_filename, dev->_defaultname, str_length + 1);
  685. }
  686. /* Default if filename is empty string */
  687. if (strcmp(dev->input_filename, "") == 0) {
  688. if (dev->_isNTSC) {
  689. dev->_filename =
  690. (dev->_pixel_format ==
  691. PIXEL_FRMT_411) ? "/root/vid411.yuv" :
  692. "/root/vidtest.yuv";
  693. } else {
  694. dev->_filename =
  695. (dev->_pixel_format ==
  696. PIXEL_FRMT_411) ? "/root/pal411.yuv" :
  697. "/root/pal422.yuv";
  698. }
  699. }
  700. dev->_is_running = 0;
  701. dev->_frame_count = 0;
  702. dev->_file_status = RESET_STATUS;
  703. dev->_lines_count = dev->_isNTSC ? 480 : 576;
  704. dev->_pixel_format = pixel_format;
  705. dev->_line_size =
  706. (dev->_pixel_format ==
  707. PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
  708. retval =
  709. cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size,
  710. 0);
  711. /* setup fifo + format */
  712. cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format);
  713. dev->upstream_riscbuf_size = risc_buffer_size * 2;
  714. dev->upstream_databuf_size = data_frame_size * 2;
  715. /* Allocating buffers and prepare RISC program */
  716. retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size);
  717. if (retval < 0) {
  718. pr_err("%s: Failed to set up Video upstream buffers!\n",
  719. dev->name);
  720. goto error;
  721. }
  722. cx25821_start_video_dma_upstream(dev, sram_ch);
  723. return 0;
  724. error:
  725. cx25821_dev_unregister(dev);
  726. return err;
  727. }