/drivers/staging/comedi/drivers/mite.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2 · C · 831 lines · 618 code · 101 blank · 112 comment · 49 complexity · f4d0ea69ae7b7fe4fe061ba938165627 MD5 · raw file

  1. /*
  2. comedi/drivers/mite.c
  3. Hardware driver for NI Mite PCI interface chip
  4. COMEDI - Linux Control and Measurement Device Interface
  5. Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. This program is distributed in the hope that it will be useful,
  11. but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. GNU General Public License for more details.
  14. You should have received a copy of the GNU General Public License
  15. along with this program; if not, write to the Free Software
  16. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. /*
  19. The PCI-MIO E series driver was originally written by
  20. Tomasz Motylewski <...>, and ported to comedi by ds.
  21. References for specifications:
  22. 321747b.pdf Register Level Programmer Manual (obsolete)
  23. 321747c.pdf Register Level Programmer Manual (new)
  24. DAQ-STC reference manual
  25. Other possibly relevant info:
  26. 320517c.pdf User manual (obsolete)
  27. 320517f.pdf User manual (new)
  28. 320889a.pdf delete
  29. 320906c.pdf maximum signal ratings
  30. 321066a.pdf about 16x
  31. 321791a.pdf discontinuation of at-mio-16e-10 rev. c
  32. 321808a.pdf about at-mio-16e-10 rev P
  33. 321837a.pdf discontinuation of at-mio-16de-10 rev d
  34. 321838a.pdf about at-mio-16de-10 rev N
  35. ISSUES:
  36. */
  37. /* #define USE_KMALLOC */
  38. #include "mite.h"
  39. #include "comedi_fc.h"
  40. #include "comedi_pci.h"
  41. #include "../comedidev.h"
  42. #include <asm/system.h>
  43. #define PCI_MITE_SIZE 4096
  44. #define PCI_DAQ_SIZE 4096
  45. #define PCI_DAQ_SIZE_660X 8192
  46. struct mite_struct *mite_devices;
  47. EXPORT_SYMBOL(mite_devices);
  48. #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
  49. void mite_init(void)
  50. {
  51. struct pci_dev *pcidev = NULL;
  52. struct mite_struct *mite;
  53. for_each_pci_dev(pcidev) {
  54. if (pcidev->vendor == PCI_VENDOR_ID_NI) {
  55. unsigned i;
  56. mite = kzalloc(sizeof(*mite), GFP_KERNEL);
  57. if (!mite) {
  58. printk(KERN_ERR "mite: allocation failed\n");
  59. pci_dev_put(pcidev);
  60. return;
  61. }
  62. spin_lock_init(&mite->lock);
  63. mite->pcidev = pci_dev_get(pcidev);
  64. for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
  65. mite->channels[i].mite = mite;
  66. mite->channels[i].channel = i;
  67. mite->channels[i].done = 1;
  68. }
  69. mite->next = mite_devices;
  70. mite_devices = mite;
  71. }
  72. }
  73. }
  74. static void dump_chip_signature(u32 csigr_bits)
  75. {
  76. printk(KERN_INFO "mite: version = %i, type = %i, mite mode = %i,"
  77. "interface mode = %i\n",
  78. mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
  79. mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
  80. printk(KERN_INFO "mite: num channels = %i, write post fifo depth = %i,"
  81. "wins = %i, iowins = %i\n",
  82. mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
  83. mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
  84. }
  85. unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
  86. {
  87. unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
  88. unsigned empty_count = (fcr_bits >> 16) & 0xff;
  89. unsigned full_count = fcr_bits & 0xff;
  90. return empty_count + full_count;
  91. }
  92. int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
  93. {
  94. unsigned long length;
  95. resource_size_t addr;
  96. int i;
  97. u32 csigr_bits;
  98. unsigned unknown_dma_burst_bits;
  99. if (comedi_pci_enable(mite->pcidev, "mite")) {
  100. printk(KERN_ERR "error enabling mite and requesting io regions\n");
  101. return -EIO;
  102. }
  103. pci_set_master(mite->pcidev);
  104. addr = pci_resource_start(mite->pcidev, 0);
  105. mite->mite_phys_addr = addr;
  106. mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
  107. if (!mite->mite_io_addr) {
  108. printk(KERN_ERR "Failed to remap mite io memory address\n");
  109. return -ENOMEM;
  110. }
  111. printk(KERN_INFO "MITE:0x%08llx mapped to %p ",
  112. (unsigned long long)mite->mite_phys_addr, mite->mite_io_addr);
  113. addr = pci_resource_start(mite->pcidev, 1);
  114. mite->daq_phys_addr = addr;
  115. length = pci_resource_len(mite->pcidev, 1);
  116. /*
  117. * In case of a 660x board, DAQ size is 8k instead of 4k
  118. * (see as shown by lspci output)
  119. */
  120. mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
  121. if (!mite->daq_io_addr) {
  122. printk(KERN_ERR "Failed to remap daq io memory address\n");
  123. return -ENOMEM;
  124. }
  125. printk(KERN_INFO "DAQ:0x%08llx mapped to %p\n",
  126. (unsigned long long)mite->daq_phys_addr, mite->daq_io_addr);
  127. if (use_iodwbsr_1) {
  128. writel(0, mite->mite_io_addr + MITE_IODWBSR);
  129. printk(KERN_INFO "mite: using I/O Window Base Size register 1\n");
  130. writel(mite->daq_phys_addr | WENAB |
  131. MITE_IODWBSR_1_WSIZE_bits(length),
  132. mite->mite_io_addr + MITE_IODWBSR_1);
  133. writel(0, mite->mite_io_addr + MITE_IODWCR_1);
  134. } else {
  135. writel(mite->daq_phys_addr | WENAB,
  136. mite->mite_io_addr + MITE_IODWBSR);
  137. }
  138. /*
  139. * make sure dma bursts work. I got this from running a bus analyzer
  140. * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
  141. * of 0x61f and bursts worked. 6281 powered up with register value of
  142. * 0x1f and bursts didn't work. The NI windows driver reads the
  143. * register, then does a bitwise-or of 0x600 with it and writes it back.
  144. */
  145. unknown_dma_burst_bits =
  146. readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
  147. unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
  148. writel(unknown_dma_burst_bits,
  149. mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
  150. csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
  151. mite->num_channels = mite_csigr_dmac(csigr_bits);
  152. if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
  153. printk(KERN_WARNING "mite: bug? chip claims to have %i dma "
  154. "channels. Setting to %i.\n",
  155. mite->num_channels, MAX_MITE_DMA_CHANNELS);
  156. mite->num_channels = MAX_MITE_DMA_CHANNELS;
  157. }
  158. dump_chip_signature(csigr_bits);
  159. for (i = 0; i < mite->num_channels; i++) {
  160. writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
  161. /* disable interrupts */
  162. writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
  163. CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
  164. CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
  165. mite->mite_io_addr + MITE_CHCR(i));
  166. }
  167. mite->fifo_size = mite_fifo_size(mite, 0);
  168. printk(KERN_INFO "mite: fifo size is %i.\n", mite->fifo_size);
  169. mite->used = 1;
  170. return 0;
  171. }
  172. EXPORT_SYMBOL(mite_setup2);
  173. int mite_setup(struct mite_struct *mite)
  174. {
  175. return mite_setup2(mite, 0);
  176. }
  177. EXPORT_SYMBOL(mite_setup);
  178. void mite_cleanup(void)
  179. {
  180. struct mite_struct *mite, *next;
  181. for (mite = mite_devices; mite; mite = next) {
  182. pci_dev_put(mite->pcidev);
  183. next = mite->next;
  184. kfree(mite);
  185. }
  186. }
  187. void mite_unsetup(struct mite_struct *mite)
  188. {
  189. /* unsigned long offset, start, length; */
  190. if (!mite)
  191. return;
  192. if (mite->mite_io_addr) {
  193. iounmap(mite->mite_io_addr);
  194. mite->mite_io_addr = NULL;
  195. }
  196. if (mite->daq_io_addr) {
  197. iounmap(mite->daq_io_addr);
  198. mite->daq_io_addr = NULL;
  199. }
  200. if (mite->mite_phys_addr) {
  201. comedi_pci_disable(mite->pcidev);
  202. mite->mite_phys_addr = 0;
  203. }
  204. mite->used = 0;
  205. }
  206. EXPORT_SYMBOL(mite_unsetup);
  207. void mite_list_devices(void)
  208. {
  209. struct mite_struct *mite, *next;
  210. printk(KERN_INFO "Available NI device IDs:");
  211. if (mite_devices)
  212. for (mite = mite_devices; mite; mite = next) {
  213. next = mite->next;
  214. printk(KERN_INFO " 0x%04x", mite_device_id(mite));
  215. if (mite->used)
  216. printk(KERN_INFO "(used)");
  217. }
  218. printk(KERN_INFO "\n");
  219. }
  220. EXPORT_SYMBOL(mite_list_devices);
  221. struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
  222. struct
  223. mite_dma_descriptor_ring
  224. *ring, unsigned min_channel,
  225. unsigned max_channel)
  226. {
  227. int i;
  228. unsigned long flags;
  229. struct mite_channel *channel = NULL;
  230. /* spin lock so mite_release_channel can be called safely
  231. * from interrupts
  232. */
  233. spin_lock_irqsave(&mite->lock, flags);
  234. for (i = min_channel; i <= max_channel; ++i) {
  235. if (mite->channel_allocated[i] == 0) {
  236. mite->channel_allocated[i] = 1;
  237. channel = &mite->channels[i];
  238. channel->ring = ring;
  239. break;
  240. }
  241. }
  242. spin_unlock_irqrestore(&mite->lock, flags);
  243. return channel;
  244. }
  245. EXPORT_SYMBOL(mite_request_channel_in_range);
  246. void mite_release_channel(struct mite_channel *mite_chan)
  247. {
  248. struct mite_struct *mite = mite_chan->mite;
  249. unsigned long flags;
  250. /* spin lock to prevent races with mite_request_channel */
  251. spin_lock_irqsave(&mite->lock, flags);
  252. if (mite->channel_allocated[mite_chan->channel]) {
  253. mite_dma_disarm(mite_chan);
  254. mite_dma_reset(mite_chan);
  255. /*
  256. * disable all channel's interrupts (do it after disarm/reset so
  257. * MITE_CHCR reg isn't changed while dma is still active!)
  258. */
  259. writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
  260. CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
  261. CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
  262. CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
  263. mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
  264. mite->channel_allocated[mite_chan->channel] = 0;
  265. mite_chan->ring = NULL;
  266. mmiowb();
  267. }
  268. spin_unlock_irqrestore(&mite->lock, flags);
  269. }
  270. EXPORT_SYMBOL(mite_release_channel);
  271. void mite_dma_arm(struct mite_channel *mite_chan)
  272. {
  273. struct mite_struct *mite = mite_chan->mite;
  274. int chor;
  275. unsigned long flags;
  276. MDPRINTK("mite_dma_arm ch%i\n", channel);
  277. /*
  278. * memory barrier is intended to insure any twiddling with the buffer
  279. * is done before writing to the mite to arm dma transfer
  280. */
  281. smp_mb();
  282. /* arm */
  283. chor = CHOR_START;
  284. spin_lock_irqsave(&mite->lock, flags);
  285. mite_chan->done = 0;
  286. writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
  287. mmiowb();
  288. spin_unlock_irqrestore(&mite->lock, flags);
  289. /* mite_dma_tcr(mite, channel); */
  290. }
  291. EXPORT_SYMBOL(mite_dma_arm);
  292. /**************************************/
  293. int mite_buf_change(struct mite_dma_descriptor_ring *ring,
  294. struct comedi_async *async)
  295. {
  296. unsigned int n_links;
  297. int i;
  298. if (ring->descriptors) {
  299. dma_free_coherent(ring->hw_dev,
  300. ring->n_links *
  301. sizeof(struct mite_dma_descriptor),
  302. ring->descriptors,
  303. ring->descriptors_dma_addr);
  304. }
  305. ring->descriptors = NULL;
  306. ring->descriptors_dma_addr = 0;
  307. ring->n_links = 0;
  308. if (async->prealloc_bufsz == 0)
  309. return 0;
  310. n_links = async->prealloc_bufsz >> PAGE_SHIFT;
  311. MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
  312. ring->descriptors =
  313. dma_alloc_coherent(ring->hw_dev,
  314. n_links * sizeof(struct mite_dma_descriptor),
  315. &ring->descriptors_dma_addr, GFP_KERNEL);
  316. if (!ring->descriptors) {
  317. printk(KERN_ERR "mite: ring buffer allocation failed\n");
  318. return -ENOMEM;
  319. }
  320. ring->n_links = n_links;
  321. for (i = 0; i < n_links; i++) {
  322. ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
  323. ring->descriptors[i].addr =
  324. cpu_to_le32(async->buf_page_list[i].dma_addr);
  325. ring->descriptors[i].next =
  326. cpu_to_le32(ring->descriptors_dma_addr + (i +
  327. 1) *
  328. sizeof(struct mite_dma_descriptor));
  329. }
  330. ring->descriptors[n_links - 1].next =
  331. cpu_to_le32(ring->descriptors_dma_addr);
  332. /*
  333. * barrier is meant to insure that all the writes to the dma descriptors
  334. * have completed before the dma controller is commanded to read them
  335. */
  336. smp_wmb();
  337. return 0;
  338. }
  339. EXPORT_SYMBOL(mite_buf_change);
  340. void mite_prep_dma(struct mite_channel *mite_chan,
  341. unsigned int num_device_bits, unsigned int num_memory_bits)
  342. {
  343. unsigned int chor, chcr, mcr, dcr, lkcr;
  344. struct mite_struct *mite = mite_chan->mite;
  345. MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
  346. /* reset DMA and FIFO */
  347. chor = CHOR_DMARESET | CHOR_FRESET;
  348. writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
  349. /* short link chaining mode */
  350. chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
  351. CHCR_BURSTEN;
  352. /*
  353. * Link Complete Interrupt: interrupt every time a link
  354. * in MITE_RING is completed. This can generate a lot of
  355. * extra interrupts, but right now we update the values
  356. * of buf_int_ptr and buf_int_count at each interrupt. A
  357. * better method is to poll the MITE before each user
  358. * "read()" to calculate the number of bytes available.
  359. */
  360. chcr |= CHCR_SET_LC_IE;
  361. if (num_memory_bits == 32 && num_device_bits == 16) {
  362. /*
  363. * Doing a combined 32 and 16 bit byteswap gets the 16 bit
  364. * samples into the fifo in the right order. Tested doing 32 bit
  365. * memory to 16 bit device transfers to the analog out of a
  366. * pxi-6281, which has mite version = 1, type = 4. This also
  367. * works for dma reads from the counters on e-series boards.
  368. */
  369. chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
  370. }
  371. if (mite_chan->dir == COMEDI_INPUT)
  372. chcr |= CHCR_DEV_TO_MEM;
  373. writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
  374. /* to/from memory */
  375. mcr = CR_RL(64) | CR_ASEQUP;
  376. switch (num_memory_bits) {
  377. case 8:
  378. mcr |= CR_PSIZE8;
  379. break;
  380. case 16:
  381. mcr |= CR_PSIZE16;
  382. break;
  383. case 32:
  384. mcr |= CR_PSIZE32;
  385. break;
  386. default:
  387. printk(KERN_WARNING "mite: bug! invalid mem bit width for dma "
  388. "transfer\n");
  389. break;
  390. }
  391. writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
  392. /* from/to device */
  393. dcr = CR_RL(64) | CR_ASEQUP;
  394. dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
  395. switch (num_device_bits) {
  396. case 8:
  397. dcr |= CR_PSIZE8;
  398. break;
  399. case 16:
  400. dcr |= CR_PSIZE16;
  401. break;
  402. case 32:
  403. dcr |= CR_PSIZE32;
  404. break;
  405. default:
  406. printk(KERN_WARNING "mite: bug! invalid dev bit width for dma "
  407. "transfer\n");
  408. break;
  409. }
  410. writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
  411. /* reset the DAR */
  412. writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
  413. /* the link is 32bits */
  414. lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
  415. writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
  416. /* starting address for link chaining */
  417. writel(mite_chan->ring->descriptors_dma_addr,
  418. mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
  419. MDPRINTK("exit mite_prep_dma\n");
  420. }
  421. EXPORT_SYMBOL(mite_prep_dma);
  422. u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
  423. {
  424. struct mite_struct *mite = mite_chan->mite;
  425. return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
  426. }
  427. u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
  428. {
  429. struct mite_struct *mite = mite_chan->mite;
  430. return readl(mite->mite_io_addr +
  431. MITE_FCR(mite_chan->channel)) & 0x000000FF;
  432. }
  433. EXPORT_SYMBOL(mite_bytes_in_transit);
  434. /* returns lower bound for number of bytes transferred from device to memory */
  435. u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
  436. {
  437. u32 device_byte_count;
  438. device_byte_count = mite_device_bytes_transferred(mite_chan);
  439. return device_byte_count - mite_bytes_in_transit(mite_chan);
  440. }
  441. EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
  442. /* returns upper bound for number of bytes transferred from device to memory */
  443. u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
  444. {
  445. u32 in_transit_count;
  446. in_transit_count = mite_bytes_in_transit(mite_chan);
  447. return mite_device_bytes_transferred(mite_chan) - in_transit_count;
  448. }
  449. EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
  450. /* returns lower bound for number of bytes read from memory to device */
  451. u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
  452. {
  453. u32 device_byte_count;
  454. device_byte_count = mite_device_bytes_transferred(mite_chan);
  455. return device_byte_count + mite_bytes_in_transit(mite_chan);
  456. }
  457. EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
  458. /* returns upper bound for number of bytes read from memory to device */
  459. u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
  460. {
  461. u32 in_transit_count;
  462. in_transit_count = mite_bytes_in_transit(mite_chan);
  463. return mite_device_bytes_transferred(mite_chan) + in_transit_count;
  464. }
  465. EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
  466. unsigned mite_dma_tcr(struct mite_channel *mite_chan)
  467. {
  468. struct mite_struct *mite = mite_chan->mite;
  469. int tcr;
  470. int lkar;
  471. lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
  472. tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
  473. MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
  474. lkar, tcr);
  475. return tcr;
  476. }
  477. EXPORT_SYMBOL(mite_dma_tcr);
  478. void mite_dma_disarm(struct mite_channel *mite_chan)
  479. {
  480. struct mite_struct *mite = mite_chan->mite;
  481. unsigned chor;
  482. /* disarm */
  483. chor = CHOR_ABORT;
  484. writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
  485. }
  486. EXPORT_SYMBOL(mite_dma_disarm);
  487. int mite_sync_input_dma(struct mite_channel *mite_chan,
  488. struct comedi_async *async)
  489. {
  490. int count;
  491. unsigned int nbytes, old_alloc_count;
  492. const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
  493. old_alloc_count = async->buf_write_alloc_count;
  494. /* write alloc as much as we can */
  495. comedi_buf_write_alloc(async, async->prealloc_bufsz);
  496. nbytes = mite_bytes_written_to_memory_lb(mite_chan);
  497. if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
  498. old_alloc_count) > 0) {
  499. printk("mite: DMA overwrite of free area\n");
  500. async->events |= COMEDI_CB_OVERFLOW;
  501. return -1;
  502. }
  503. count = nbytes - async->buf_write_count;
  504. /* it's possible count will be negative due to
  505. * conservative value returned by mite_bytes_written_to_memory_lb */
  506. if (count <= 0)
  507. return 0;
  508. comedi_buf_write_free(async, count);
  509. async->scan_progress += count;
  510. if (async->scan_progress >= bytes_per_scan) {
  511. async->scan_progress %= bytes_per_scan;
  512. async->events |= COMEDI_CB_EOS;
  513. }
  514. async->events |= COMEDI_CB_BLOCK;
  515. return 0;
  516. }
  517. EXPORT_SYMBOL(mite_sync_input_dma);
  518. int mite_sync_output_dma(struct mite_channel *mite_chan,
  519. struct comedi_async *async)
  520. {
  521. int count;
  522. u32 nbytes_ub, nbytes_lb;
  523. unsigned int old_alloc_count;
  524. u32 stop_count =
  525. async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
  526. old_alloc_count = async->buf_read_alloc_count;
  527. /* read alloc as much as we can */
  528. comedi_buf_read_alloc(async, async->prealloc_bufsz);
  529. nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
  530. if (async->cmd.stop_src == TRIG_COUNT &&
  531. (int)(nbytes_lb - stop_count) > 0)
  532. nbytes_lb = stop_count;
  533. nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
  534. if (async->cmd.stop_src == TRIG_COUNT &&
  535. (int)(nbytes_ub - stop_count) > 0)
  536. nbytes_ub = stop_count;
  537. if ((int)(nbytes_ub - old_alloc_count) > 0) {
  538. printk(KERN_ERR "mite: DMA underrun\n");
  539. async->events |= COMEDI_CB_OVERFLOW;
  540. return -1;
  541. }
  542. count = nbytes_lb - async->buf_read_count;
  543. if (count <= 0)
  544. return 0;
  545. if (count) {
  546. comedi_buf_read_free(async, count);
  547. async->events |= COMEDI_CB_BLOCK;
  548. }
  549. return 0;
  550. }
  551. EXPORT_SYMBOL(mite_sync_output_dma);
  552. unsigned mite_get_status(struct mite_channel *mite_chan)
  553. {
  554. struct mite_struct *mite = mite_chan->mite;
  555. unsigned status;
  556. unsigned long flags;
  557. spin_lock_irqsave(&mite->lock, flags);
  558. status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
  559. if (status & CHSR_DONE) {
  560. mite_chan->done = 1;
  561. writel(CHOR_CLRDONE,
  562. mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
  563. }
  564. mmiowb();
  565. spin_unlock_irqrestore(&mite->lock, flags);
  566. return status;
  567. }
  568. EXPORT_SYMBOL(mite_get_status);
  569. int mite_done(struct mite_channel *mite_chan)
  570. {
  571. struct mite_struct *mite = mite_chan->mite;
  572. unsigned long flags;
  573. int done;
  574. mite_get_status(mite_chan);
  575. spin_lock_irqsave(&mite->lock, flags);
  576. done = mite_chan->done;
  577. spin_unlock_irqrestore(&mite->lock, flags);
  578. return done;
  579. }
  580. EXPORT_SYMBOL(mite_done);
  581. #ifdef DEBUG_MITE
  582. static void mite_decode(char **bit_str, unsigned int bits);
  583. /* names of bits in mite registers */
  584. static const char *const mite_CHOR_strings[] = {
  585. "start", "cont", "stop", "abort",
  586. "freset", "clrlc", "clrrb", "clrdone",
  587. "clr_lpause", "set_lpause", "clr_send_tc",
  588. "set_send_tc", "12", "13", "14",
  589. "15", "16", "17", "18",
  590. "19", "20", "21", "22",
  591. "23", "24", "25", "26",
  592. "27", "28", "29", "30",
  593. "dmareset",
  594. };
  595. static const char *const mite_CHCR_strings[] = {
  596. "continue", "ringbuff", "2", "3",
  597. "4", "5", "6", "7",
  598. "8", "9", "10", "11",
  599. "12", "13", "bursten", "fifodis",
  600. "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
  601. "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
  602. "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
  603. "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
  604. };
  605. static const char *const mite_MCR_strings[] = {
  606. "amdevice", "1", "2", "3",
  607. "4", "5", "portio", "portvxi",
  608. "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
  609. "12", "13", "blocken", "berhand",
  610. "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
  611. "rd512", "rl1", "rl2", "rl8",
  612. "24", "25", "26", "27",
  613. "28", "29", "30", "stopen",
  614. };
  615. static const char *const mite_DCR_strings[] = {
  616. "amdevice", "1", "2", "3",
  617. "4", "5", "portio", "portvxi",
  618. "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
  619. "aseqxp8", "13", "blocken", "berhand",
  620. "reqsintlim", "reqs1", "reqs2", "rd32",
  621. "rd512", "rl1", "rl2", "rl8",
  622. "23", "24", "25", "27",
  623. "28", "wsdevc", "wsdevs", "rwdevpack",
  624. };
  625. static const char *const mite_LKCR_strings[] = {
  626. "amdevice", "1", "2", "3",
  627. "4", "5", "portio", "portvxi",
  628. "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
  629. "12", "13", "14", "berhand",
  630. "16", "17", "18", "rd32",
  631. "rd512", "rl1", "rl2", "rl8",
  632. "24", "25", "26", "27",
  633. "28", "29", "30", "chngend",
  634. };
  635. static const char *const mite_CHSR_strings[] = {
  636. "d.err0", "d.err1", "m.err0", "m.err1",
  637. "l.err0", "l.err1", "drq0", "drq1",
  638. "end", "xferr", "operr0", "operr1",
  639. "stops", "habort", "sabort", "error",
  640. "16", "conts_rb", "18", "linkc",
  641. "20", "drdy", "22", "mrdy",
  642. "24", "done", "26", "sars",
  643. "28", "lpauses", "30", "int",
  644. };
  645. void mite_dump_regs(struct mite_channel *mite_chan)
  646. {
  647. unsigned long mite_io_addr =
  648. (unsigned long)mite_chan->mite->mite_io_addr;
  649. unsigned long addr = 0;
  650. unsigned long temp = 0;
  651. printk(KERN_DEBUG "mite_dump_regs ch%i\n", mite_chan->channel);
  652. printk(KERN_DEBUG "mite address is =0x%08lx\n", mite_io_addr);
  653. addr = mite_io_addr + MITE_CHOR(channel);
  654. printk(KERN_DEBUG "mite status[CHOR]at 0x%08lx =0x%08lx\n", addr,
  655. temp = readl(addr));
  656. mite_decode(mite_CHOR_strings, temp);
  657. addr = mite_io_addr + MITE_CHCR(channel);
  658. printk(KERN_DEBUG "mite status[CHCR]at 0x%08lx =0x%08lx\n", addr,
  659. temp = readl(addr));
  660. mite_decode(mite_CHCR_strings, temp);
  661. addr = mite_io_addr + MITE_TCR(channel);
  662. printk(KERN_DEBUG "mite status[TCR] at 0x%08lx =0x%08x\n", addr,
  663. readl(addr));
  664. addr = mite_io_addr + MITE_MCR(channel);
  665. printk(KERN_DEBUG "mite status[MCR] at 0x%08lx =0x%08lx\n", addr,
  666. temp = readl(addr));
  667. mite_decode(mite_MCR_strings, temp);
  668. addr = mite_io_addr + MITE_MAR(channel);
  669. printk(KERN_DEBUG "mite status[MAR] at 0x%08lx =0x%08x\n", addr,
  670. readl(addr));
  671. addr = mite_io_addr + MITE_DCR(channel);
  672. printk(KERN_DEBUG "mite status[DCR] at 0x%08lx =0x%08lx\n", addr,
  673. temp = readl(addr));
  674. mite_decode(mite_DCR_strings, temp);
  675. addr = mite_io_addr + MITE_DAR(channel);
  676. printk(KERN_DEBUG "mite status[DAR] at 0x%08lx =0x%08x\n", addr,
  677. readl(addr));
  678. addr = mite_io_addr + MITE_LKCR(channel);
  679. printk(KERN_DEBUG "mite status[LKCR]at 0x%08lx =0x%08lx\n", addr,
  680. temp = readl(addr));
  681. mite_decode(mite_LKCR_strings, temp);
  682. addr = mite_io_addr + MITE_LKAR(channel);
  683. printk(KERN_DEBUG "mite status[LKAR]at 0x%08lx =0x%08x\n", addr,
  684. readl(addr));
  685. addr = mite_io_addr + MITE_CHSR(channel);
  686. printk(KERN_DEBUG "mite status[CHSR]at 0x%08lx =0x%08lx\n", addr,
  687. temp = readl(addr));
  688. mite_decode(mite_CHSR_strings, temp);
  689. addr = mite_io_addr + MITE_FCR(channel);
  690. printk(KERN_DEBUG "mite status[FCR] at 0x%08lx =0x%08x\n\n", addr,
  691. readl(addr));
  692. }
  693. EXPORT_SYMBOL(mite_dump_regs);
  694. static void mite_decode(char **bit_str, unsigned int bits)
  695. {
  696. int i;
  697. for (i = 31; i >= 0; i--) {
  698. if (bits & (1 << i))
  699. printk(KERN_DEBUG " %s", bit_str[i]);
  700. }
  701. printk(KERN_DEBUG "\n");
  702. }
  703. EXPORT_SYMBOL(mite_decode);
  704. #endif
  705. #ifdef MODULE
  706. int __init init_module(void)
  707. {
  708. mite_init();
  709. mite_list_devices();
  710. return 0;
  711. }
  712. void __exit cleanup_module(void)
  713. {
  714. mite_cleanup();
  715. }
  716. #endif
  717. MODULE_AUTHOR("Comedi http://www.comedi.org");
  718. MODULE_DESCRIPTION("Comedi low-level driver");
  719. MODULE_LICENSE("GPL");