/drivers/staging/comedi/drivers/mite.c
C | 831 lines | 618 code | 101 blank | 112 comment | 49 complexity | f4d0ea69ae7b7fe4fe061ba938165627 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/*
2 comedi/drivers/mite.c
3 Hardware driver for NI Mite PCI interface chip
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21
22*/
23
24/*
25 The PCI-MIO E series driver was originally written by
26 Tomasz Motylewski <...>, and ported to comedi by ds.
27
28 References for specifications:
29
30 321747b.pdf Register Level Programmer Manual (obsolete)
31 321747c.pdf Register Level Programmer Manual (new)
32 DAQ-STC reference manual
33
34 Other possibly relevant info:
35
36 320517c.pdf User manual (obsolete)
37 320517f.pdf User manual (new)
38 320889a.pdf delete
39 320906c.pdf maximum signal ratings
40 321066a.pdf about 16x
41 321791a.pdf discontinuation of at-mio-16e-10 rev. c
42 321808a.pdf about at-mio-16e-10 rev P
43 321837a.pdf discontinuation of at-mio-16de-10 rev d
44 321838a.pdf about at-mio-16de-10 rev N
45
46 ISSUES:
47
48*/
49
50/* #define USE_KMALLOC */
51
52#include "mite.h"
53
54#include "comedi_fc.h"
55#include "comedi_pci.h"
56#include "../comedidev.h"
57
58#include <asm/system.h>
59
60#define PCI_MITE_SIZE 4096
61#define PCI_DAQ_SIZE 4096
62#define PCI_DAQ_SIZE_660X 8192
63
64struct mite_struct *mite_devices;
65EXPORT_SYMBOL(mite_devices);
66
67#define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
68
69void mite_init(void)
70{
71 struct pci_dev *pcidev = NULL;
72 struct mite_struct *mite;
73
74 for_each_pci_dev(pcidev) {
75 if (pcidev->vendor == PCI_VENDOR_ID_NI) {
76 unsigned i;
77
78 mite = kzalloc(sizeof(*mite), GFP_KERNEL);
79 if (!mite) {
80 printk(KERN_ERR "mite: allocation failed\n");
81 pci_dev_put(pcidev);
82 return;
83 }
84 spin_lock_init(&mite->lock);
85 mite->pcidev = pci_dev_get(pcidev);
86 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
87 mite->channels[i].mite = mite;
88 mite->channels[i].channel = i;
89 mite->channels[i].done = 1;
90 }
91 mite->next = mite_devices;
92 mite_devices = mite;
93 }
94 }
95}
96
97static void dump_chip_signature(u32 csigr_bits)
98{
99 printk(KERN_INFO "mite: version = %i, type = %i, mite mode = %i,"
100 "interface mode = %i\n",
101 mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
102 mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
103 printk(KERN_INFO "mite: num channels = %i, write post fifo depth = %i,"
104 "wins = %i, iowins = %i\n",
105 mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
106 mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
107}
108
109unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
110{
111 unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
112 unsigned empty_count = (fcr_bits >> 16) & 0xff;
113 unsigned full_count = fcr_bits & 0xff;
114 return empty_count + full_count;
115}
116
117int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
118{
119 unsigned long length;
120 resource_size_t addr;
121 int i;
122 u32 csigr_bits;
123 unsigned unknown_dma_burst_bits;
124
125 if (comedi_pci_enable(mite->pcidev, "mite")) {
126 printk(KERN_ERR "error enabling mite and requesting io regions\n");
127 return -EIO;
128 }
129 pci_set_master(mite->pcidev);
130
131 addr = pci_resource_start(mite->pcidev, 0);
132 mite->mite_phys_addr = addr;
133 mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
134 if (!mite->mite_io_addr) {
135 printk(KERN_ERR "Failed to remap mite io memory address\n");
136 return -ENOMEM;
137 }
138 printk(KERN_INFO "MITE:0x%08llx mapped to %p ",
139 (unsigned long long)mite->mite_phys_addr, mite->mite_io_addr);
140
141 addr = pci_resource_start(mite->pcidev, 1);
142 mite->daq_phys_addr = addr;
143 length = pci_resource_len(mite->pcidev, 1);
144 /*
145 * In case of a 660x board, DAQ size is 8k instead of 4k
146 * (see as shown by lspci output)
147 */
148 mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
149 if (!mite->daq_io_addr) {
150 printk(KERN_ERR "Failed to remap daq io memory address\n");
151 return -ENOMEM;
152 }
153 printk(KERN_INFO "DAQ:0x%08llx mapped to %p\n",
154 (unsigned long long)mite->daq_phys_addr, mite->daq_io_addr);
155
156 if (use_iodwbsr_1) {
157 writel(0, mite->mite_io_addr + MITE_IODWBSR);
158 printk(KERN_INFO "mite: using I/O Window Base Size register 1\n");
159 writel(mite->daq_phys_addr | WENAB |
160 MITE_IODWBSR_1_WSIZE_bits(length),
161 mite->mite_io_addr + MITE_IODWBSR_1);
162 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
163 } else {
164 writel(mite->daq_phys_addr | WENAB,
165 mite->mite_io_addr + MITE_IODWBSR);
166 }
167 /*
168 * make sure dma bursts work. I got this from running a bus analyzer
169 * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
170 * of 0x61f and bursts worked. 6281 powered up with register value of
171 * 0x1f and bursts didn't work. The NI windows driver reads the
172 * register, then does a bitwise-or of 0x600 with it and writes it back.
173 */
174 unknown_dma_burst_bits =
175 readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
176 unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
177 writel(unknown_dma_burst_bits,
178 mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
179
180 csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
181 mite->num_channels = mite_csigr_dmac(csigr_bits);
182 if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
183 printk(KERN_WARNING "mite: bug? chip claims to have %i dma "
184 "channels. Setting to %i.\n",
185 mite->num_channels, MAX_MITE_DMA_CHANNELS);
186 mite->num_channels = MAX_MITE_DMA_CHANNELS;
187 }
188 dump_chip_signature(csigr_bits);
189 for (i = 0; i < mite->num_channels; i++) {
190 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
191 /* disable interrupts */
192 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
193 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
194 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
195 mite->mite_io_addr + MITE_CHCR(i));
196 }
197 mite->fifo_size = mite_fifo_size(mite, 0);
198 printk(KERN_INFO "mite: fifo size is %i.\n", mite->fifo_size);
199 mite->used = 1;
200
201 return 0;
202}
203EXPORT_SYMBOL(mite_setup2);
204
205int mite_setup(struct mite_struct *mite)
206{
207 return mite_setup2(mite, 0);
208}
209EXPORT_SYMBOL(mite_setup);
210
211void mite_cleanup(void)
212{
213 struct mite_struct *mite, *next;
214
215 for (mite = mite_devices; mite; mite = next) {
216 pci_dev_put(mite->pcidev);
217 next = mite->next;
218 kfree(mite);
219 }
220}
221
222void mite_unsetup(struct mite_struct *mite)
223{
224 /* unsigned long offset, start, length; */
225
226 if (!mite)
227 return;
228
229 if (mite->mite_io_addr) {
230 iounmap(mite->mite_io_addr);
231 mite->mite_io_addr = NULL;
232 }
233 if (mite->daq_io_addr) {
234 iounmap(mite->daq_io_addr);
235 mite->daq_io_addr = NULL;
236 }
237 if (mite->mite_phys_addr) {
238 comedi_pci_disable(mite->pcidev);
239 mite->mite_phys_addr = 0;
240 }
241
242 mite->used = 0;
243}
244EXPORT_SYMBOL(mite_unsetup);
245
246void mite_list_devices(void)
247{
248 struct mite_struct *mite, *next;
249
250 printk(KERN_INFO "Available NI device IDs:");
251 if (mite_devices)
252 for (mite = mite_devices; mite; mite = next) {
253 next = mite->next;
254 printk(KERN_INFO " 0x%04x", mite_device_id(mite));
255 if (mite->used)
256 printk(KERN_INFO "(used)");
257 }
258 printk(KERN_INFO "\n");
259}
260EXPORT_SYMBOL(mite_list_devices);
261
262struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
263 struct
264 mite_dma_descriptor_ring
265 *ring, unsigned min_channel,
266 unsigned max_channel)
267{
268 int i;
269 unsigned long flags;
270 struct mite_channel *channel = NULL;
271
272 /* spin lock so mite_release_channel can be called safely
273 * from interrupts
274 */
275 spin_lock_irqsave(&mite->lock, flags);
276 for (i = min_channel; i <= max_channel; ++i) {
277 if (mite->channel_allocated[i] == 0) {
278 mite->channel_allocated[i] = 1;
279 channel = &mite->channels[i];
280 channel->ring = ring;
281 break;
282 }
283 }
284 spin_unlock_irqrestore(&mite->lock, flags);
285 return channel;
286}
287EXPORT_SYMBOL(mite_request_channel_in_range);
288
289void mite_release_channel(struct mite_channel *mite_chan)
290{
291 struct mite_struct *mite = mite_chan->mite;
292 unsigned long flags;
293
294 /* spin lock to prevent races with mite_request_channel */
295 spin_lock_irqsave(&mite->lock, flags);
296 if (mite->channel_allocated[mite_chan->channel]) {
297 mite_dma_disarm(mite_chan);
298 mite_dma_reset(mite_chan);
299 /*
300 * disable all channel's interrupts (do it after disarm/reset so
301 * MITE_CHCR reg isn't changed while dma is still active!)
302 */
303 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
304 CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
305 CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
306 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
307 mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
308 mite->channel_allocated[mite_chan->channel] = 0;
309 mite_chan->ring = NULL;
310 mmiowb();
311 }
312 spin_unlock_irqrestore(&mite->lock, flags);
313}
314EXPORT_SYMBOL(mite_release_channel);
315
316void mite_dma_arm(struct mite_channel *mite_chan)
317{
318 struct mite_struct *mite = mite_chan->mite;
319 int chor;
320 unsigned long flags;
321
322 MDPRINTK("mite_dma_arm ch%i\n", channel);
323 /*
324 * memory barrier is intended to insure any twiddling with the buffer
325 * is done before writing to the mite to arm dma transfer
326 */
327 smp_mb();
328 /* arm */
329 chor = CHOR_START;
330 spin_lock_irqsave(&mite->lock, flags);
331 mite_chan->done = 0;
332 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
333 mmiowb();
334 spin_unlock_irqrestore(&mite->lock, flags);
335/* mite_dma_tcr(mite, channel); */
336}
337EXPORT_SYMBOL(mite_dma_arm);
338
339/**************************************/
340
341int mite_buf_change(struct mite_dma_descriptor_ring *ring,
342 struct comedi_async *async)
343{
344 unsigned int n_links;
345 int i;
346
347 if (ring->descriptors) {
348 dma_free_coherent(ring->hw_dev,
349 ring->n_links *
350 sizeof(struct mite_dma_descriptor),
351 ring->descriptors,
352 ring->descriptors_dma_addr);
353 }
354 ring->descriptors = NULL;
355 ring->descriptors_dma_addr = 0;
356 ring->n_links = 0;
357
358 if (async->prealloc_bufsz == 0)
359 return 0;
360
361 n_links = async->prealloc_bufsz >> PAGE_SHIFT;
362
363 MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
364
365 ring->descriptors =
366 dma_alloc_coherent(ring->hw_dev,
367 n_links * sizeof(struct mite_dma_descriptor),
368 &ring->descriptors_dma_addr, GFP_KERNEL);
369 if (!ring->descriptors) {
370 printk(KERN_ERR "mite: ring buffer allocation failed\n");
371 return -ENOMEM;
372 }
373 ring->n_links = n_links;
374
375 for (i = 0; i < n_links; i++) {
376 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
377 ring->descriptors[i].addr =
378 cpu_to_le32(async->buf_page_list[i].dma_addr);
379 ring->descriptors[i].next =
380 cpu_to_le32(ring->descriptors_dma_addr + (i +
381 1) *
382 sizeof(struct mite_dma_descriptor));
383 }
384 ring->descriptors[n_links - 1].next =
385 cpu_to_le32(ring->descriptors_dma_addr);
386 /*
387 * barrier is meant to insure that all the writes to the dma descriptors
388 * have completed before the dma controller is commanded to read them
389 */
390 smp_wmb();
391 return 0;
392}
393EXPORT_SYMBOL(mite_buf_change);
394
395void mite_prep_dma(struct mite_channel *mite_chan,
396 unsigned int num_device_bits, unsigned int num_memory_bits)
397{
398 unsigned int chor, chcr, mcr, dcr, lkcr;
399 struct mite_struct *mite = mite_chan->mite;
400
401 MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
402
403 /* reset DMA and FIFO */
404 chor = CHOR_DMARESET | CHOR_FRESET;
405 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
406
407 /* short link chaining mode */
408 chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
409 CHCR_BURSTEN;
410 /*
411 * Link Complete Interrupt: interrupt every time a link
412 * in MITE_RING is completed. This can generate a lot of
413 * extra interrupts, but right now we update the values
414 * of buf_int_ptr and buf_int_count at each interrupt. A
415 * better method is to poll the MITE before each user
416 * "read()" to calculate the number of bytes available.
417 */
418 chcr |= CHCR_SET_LC_IE;
419 if (num_memory_bits == 32 && num_device_bits == 16) {
420 /*
421 * Doing a combined 32 and 16 bit byteswap gets the 16 bit
422 * samples into the fifo in the right order. Tested doing 32 bit
423 * memory to 16 bit device transfers to the analog out of a
424 * pxi-6281, which has mite version = 1, type = 4. This also
425 * works for dma reads from the counters on e-series boards.
426 */
427 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
428 }
429 if (mite_chan->dir == COMEDI_INPUT)
430 chcr |= CHCR_DEV_TO_MEM;
431
432 writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
433
434 /* to/from memory */
435 mcr = CR_RL(64) | CR_ASEQUP;
436 switch (num_memory_bits) {
437 case 8:
438 mcr |= CR_PSIZE8;
439 break;
440 case 16:
441 mcr |= CR_PSIZE16;
442 break;
443 case 32:
444 mcr |= CR_PSIZE32;
445 break;
446 default:
447 printk(KERN_WARNING "mite: bug! invalid mem bit width for dma "
448 "transfer\n");
449 break;
450 }
451 writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
452
453 /* from/to device */
454 dcr = CR_RL(64) | CR_ASEQUP;
455 dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
456 switch (num_device_bits) {
457 case 8:
458 dcr |= CR_PSIZE8;
459 break;
460 case 16:
461 dcr |= CR_PSIZE16;
462 break;
463 case 32:
464 dcr |= CR_PSIZE32;
465 break;
466 default:
467 printk(KERN_WARNING "mite: bug! invalid dev bit width for dma "
468 "transfer\n");
469 break;
470 }
471 writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
472
473 /* reset the DAR */
474 writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
475
476 /* the link is 32bits */
477 lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
478 writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
479
480 /* starting address for link chaining */
481 writel(mite_chan->ring->descriptors_dma_addr,
482 mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
483
484 MDPRINTK("exit mite_prep_dma\n");
485}
486EXPORT_SYMBOL(mite_prep_dma);
487
488u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
489{
490 struct mite_struct *mite = mite_chan->mite;
491 return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
492}
493
494u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
495{
496 struct mite_struct *mite = mite_chan->mite;
497 return readl(mite->mite_io_addr +
498 MITE_FCR(mite_chan->channel)) & 0x000000FF;
499}
500EXPORT_SYMBOL(mite_bytes_in_transit);
501
502/* returns lower bound for number of bytes transferred from device to memory */
503u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
504{
505 u32 device_byte_count;
506
507 device_byte_count = mite_device_bytes_transferred(mite_chan);
508 return device_byte_count - mite_bytes_in_transit(mite_chan);
509}
510EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
511
512/* returns upper bound for number of bytes transferred from device to memory */
513u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
514{
515 u32 in_transit_count;
516
517 in_transit_count = mite_bytes_in_transit(mite_chan);
518 return mite_device_bytes_transferred(mite_chan) - in_transit_count;
519}
520EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
521
522/* returns lower bound for number of bytes read from memory to device */
523u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
524{
525 u32 device_byte_count;
526
527 device_byte_count = mite_device_bytes_transferred(mite_chan);
528 return device_byte_count + mite_bytes_in_transit(mite_chan);
529}
530EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
531
532/* returns upper bound for number of bytes read from memory to device */
533u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
534{
535 u32 in_transit_count;
536
537 in_transit_count = mite_bytes_in_transit(mite_chan);
538 return mite_device_bytes_transferred(mite_chan) + in_transit_count;
539}
540EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
541
542unsigned mite_dma_tcr(struct mite_channel *mite_chan)
543{
544 struct mite_struct *mite = mite_chan->mite;
545 int tcr;
546 int lkar;
547
548 lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
549 tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
550 MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
551 lkar, tcr);
552
553 return tcr;
554}
555EXPORT_SYMBOL(mite_dma_tcr);
556
557void mite_dma_disarm(struct mite_channel *mite_chan)
558{
559 struct mite_struct *mite = mite_chan->mite;
560 unsigned chor;
561
562 /* disarm */
563 chor = CHOR_ABORT;
564 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
565}
566EXPORT_SYMBOL(mite_dma_disarm);
567
568int mite_sync_input_dma(struct mite_channel *mite_chan,
569 struct comedi_async *async)
570{
571 int count;
572 unsigned int nbytes, old_alloc_count;
573 const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
574
575 old_alloc_count = async->buf_write_alloc_count;
576 /* write alloc as much as we can */
577 comedi_buf_write_alloc(async, async->prealloc_bufsz);
578
579 nbytes = mite_bytes_written_to_memory_lb(mite_chan);
580 if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
581 old_alloc_count) > 0) {
582 printk("mite: DMA overwrite of free area\n");
583 async->events |= COMEDI_CB_OVERFLOW;
584 return -1;
585 }
586
587 count = nbytes - async->buf_write_count;
588 /* it's possible count will be negative due to
589 * conservative value returned by mite_bytes_written_to_memory_lb */
590 if (count <= 0)
591 return 0;
592
593 comedi_buf_write_free(async, count);
594
595 async->scan_progress += count;
596 if (async->scan_progress >= bytes_per_scan) {
597 async->scan_progress %= bytes_per_scan;
598 async->events |= COMEDI_CB_EOS;
599 }
600 async->events |= COMEDI_CB_BLOCK;
601 return 0;
602}
603EXPORT_SYMBOL(mite_sync_input_dma);
604
605int mite_sync_output_dma(struct mite_channel *mite_chan,
606 struct comedi_async *async)
607{
608 int count;
609 u32 nbytes_ub, nbytes_lb;
610 unsigned int old_alloc_count;
611 u32 stop_count =
612 async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
613
614 old_alloc_count = async->buf_read_alloc_count;
615 /* read alloc as much as we can */
616 comedi_buf_read_alloc(async, async->prealloc_bufsz);
617 nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
618 if (async->cmd.stop_src == TRIG_COUNT &&
619 (int)(nbytes_lb - stop_count) > 0)
620 nbytes_lb = stop_count;
621 nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
622 if (async->cmd.stop_src == TRIG_COUNT &&
623 (int)(nbytes_ub - stop_count) > 0)
624 nbytes_ub = stop_count;
625 if ((int)(nbytes_ub - old_alloc_count) > 0) {
626 printk(KERN_ERR "mite: DMA underrun\n");
627 async->events |= COMEDI_CB_OVERFLOW;
628 return -1;
629 }
630 count = nbytes_lb - async->buf_read_count;
631 if (count <= 0)
632 return 0;
633
634 if (count) {
635 comedi_buf_read_free(async, count);
636 async->events |= COMEDI_CB_BLOCK;
637 }
638 return 0;
639}
640EXPORT_SYMBOL(mite_sync_output_dma);
641
642unsigned mite_get_status(struct mite_channel *mite_chan)
643{
644 struct mite_struct *mite = mite_chan->mite;
645 unsigned status;
646 unsigned long flags;
647
648 spin_lock_irqsave(&mite->lock, flags);
649 status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
650 if (status & CHSR_DONE) {
651 mite_chan->done = 1;
652 writel(CHOR_CLRDONE,
653 mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
654 }
655 mmiowb();
656 spin_unlock_irqrestore(&mite->lock, flags);
657 return status;
658}
659EXPORT_SYMBOL(mite_get_status);
660
661int mite_done(struct mite_channel *mite_chan)
662{
663 struct mite_struct *mite = mite_chan->mite;
664 unsigned long flags;
665 int done;
666
667 mite_get_status(mite_chan);
668 spin_lock_irqsave(&mite->lock, flags);
669 done = mite_chan->done;
670 spin_unlock_irqrestore(&mite->lock, flags);
671 return done;
672}
673EXPORT_SYMBOL(mite_done);
674
675#ifdef DEBUG_MITE
676
677static void mite_decode(char **bit_str, unsigned int bits);
678
679/* names of bits in mite registers */
680
681static const char *const mite_CHOR_strings[] = {
682 "start", "cont", "stop", "abort",
683 "freset", "clrlc", "clrrb", "clrdone",
684 "clr_lpause", "set_lpause", "clr_send_tc",
685 "set_send_tc", "12", "13", "14",
686 "15", "16", "17", "18",
687 "19", "20", "21", "22",
688 "23", "24", "25", "26",
689 "27", "28", "29", "30",
690 "dmareset",
691};
692
693static const char *const mite_CHCR_strings[] = {
694 "continue", "ringbuff", "2", "3",
695 "4", "5", "6", "7",
696 "8", "9", "10", "11",
697 "12", "13", "bursten", "fifodis",
698 "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
699 "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
700 "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
701 "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
702};
703
704static const char *const mite_MCR_strings[] = {
705 "amdevice", "1", "2", "3",
706 "4", "5", "portio", "portvxi",
707 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
708 "12", "13", "blocken", "berhand",
709 "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
710 "rd512", "rl1", "rl2", "rl8",
711 "24", "25", "26", "27",
712 "28", "29", "30", "stopen",
713};
714
715static const char *const mite_DCR_strings[] = {
716 "amdevice", "1", "2", "3",
717 "4", "5", "portio", "portvxi",
718 "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
719 "aseqxp8", "13", "blocken", "berhand",
720 "reqsintlim", "reqs1", "reqs2", "rd32",
721 "rd512", "rl1", "rl2", "rl8",
722 "23", "24", "25", "27",
723 "28", "wsdevc", "wsdevs", "rwdevpack",
724};
725
726static const char *const mite_LKCR_strings[] = {
727 "amdevice", "1", "2", "3",
728 "4", "5", "portio", "portvxi",
729 "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
730 "12", "13", "14", "berhand",
731 "16", "17", "18", "rd32",
732 "rd512", "rl1", "rl2", "rl8",
733 "24", "25", "26", "27",
734 "28", "29", "30", "chngend",
735};
736
737static const char *const mite_CHSR_strings[] = {
738 "d.err0", "d.err1", "m.err0", "m.err1",
739 "l.err0", "l.err1", "drq0", "drq1",
740 "end", "xferr", "operr0", "operr1",
741 "stops", "habort", "sabort", "error",
742 "16", "conts_rb", "18", "linkc",
743 "20", "drdy", "22", "mrdy",
744 "24", "done", "26", "sars",
745 "28", "lpauses", "30", "int",
746};
747
748void mite_dump_regs(struct mite_channel *mite_chan)
749{
750 unsigned long mite_io_addr =
751 (unsigned long)mite_chan->mite->mite_io_addr;
752 unsigned long addr = 0;
753 unsigned long temp = 0;
754
755 printk(KERN_DEBUG "mite_dump_regs ch%i\n", mite_chan->channel);
756 printk(KERN_DEBUG "mite address is =0x%08lx\n", mite_io_addr);
757
758 addr = mite_io_addr + MITE_CHOR(channel);
759 printk(KERN_DEBUG "mite status[CHOR]at 0x%08lx =0x%08lx\n", addr,
760 temp = readl(addr));
761 mite_decode(mite_CHOR_strings, temp);
762 addr = mite_io_addr + MITE_CHCR(channel);
763 printk(KERN_DEBUG "mite status[CHCR]at 0x%08lx =0x%08lx\n", addr,
764 temp = readl(addr));
765 mite_decode(mite_CHCR_strings, temp);
766 addr = mite_io_addr + MITE_TCR(channel);
767 printk(KERN_DEBUG "mite status[TCR] at 0x%08lx =0x%08x\n", addr,
768 readl(addr));
769 addr = mite_io_addr + MITE_MCR(channel);
770 printk(KERN_DEBUG "mite status[MCR] at 0x%08lx =0x%08lx\n", addr,
771 temp = readl(addr));
772 mite_decode(mite_MCR_strings, temp);
773
774 addr = mite_io_addr + MITE_MAR(channel);
775 printk(KERN_DEBUG "mite status[MAR] at 0x%08lx =0x%08x\n", addr,
776 readl(addr));
777 addr = mite_io_addr + MITE_DCR(channel);
778 printk(KERN_DEBUG "mite status[DCR] at 0x%08lx =0x%08lx\n", addr,
779 temp = readl(addr));
780 mite_decode(mite_DCR_strings, temp);
781 addr = mite_io_addr + MITE_DAR(channel);
782 printk(KERN_DEBUG "mite status[DAR] at 0x%08lx =0x%08x\n", addr,
783 readl(addr));
784 addr = mite_io_addr + MITE_LKCR(channel);
785 printk(KERN_DEBUG "mite status[LKCR]at 0x%08lx =0x%08lx\n", addr,
786 temp = readl(addr));
787 mite_decode(mite_LKCR_strings, temp);
788 addr = mite_io_addr + MITE_LKAR(channel);
789 printk(KERN_DEBUG "mite status[LKAR]at 0x%08lx =0x%08x\n", addr,
790 readl(addr));
791 addr = mite_io_addr + MITE_CHSR(channel);
792 printk(KERN_DEBUG "mite status[CHSR]at 0x%08lx =0x%08lx\n", addr,
793 temp = readl(addr));
794 mite_decode(mite_CHSR_strings, temp);
795 addr = mite_io_addr + MITE_FCR(channel);
796 printk(KERN_DEBUG "mite status[FCR] at 0x%08lx =0x%08x\n\n", addr,
797 readl(addr));
798}
799EXPORT_SYMBOL(mite_dump_regs);
800
801static void mite_decode(char **bit_str, unsigned int bits)
802{
803 int i;
804
805 for (i = 31; i >= 0; i--) {
806 if (bits & (1 << i))
807 printk(KERN_DEBUG " %s", bit_str[i]);
808 }
809 printk(KERN_DEBUG "\n");
810}
811EXPORT_SYMBOL(mite_decode);
812#endif
813
814#ifdef MODULE
815int __init init_module(void)
816{
817 mite_init();
818 mite_list_devices();
819
820 return 0;
821}
822
823void __exit cleanup_module(void)
824{
825 mite_cleanup();
826}
827#endif
828
829MODULE_AUTHOR("Comedi http://www.comedi.org");
830MODULE_DESCRIPTION("Comedi low-level driver");
831MODULE_LICENSE("GPL");