/drivers/staging/comedi/drivers/gsc_hpdi.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2 · C · 1118 lines · 840 code · 166 blank · 112 comment · 107 complexity · d07ddf5ab50d226339aadfa6ec916750 MD5 · raw file

  1. /*
  2. comedi/drivers/gsc_hpdi.c
  3. This is a driver for the General Standards Corporation High
  4. Speed Parallel Digital Interface rs485 boards.
  5. Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  6. Copyright (C) 2003 Coherent Imaging Systems
  7. COMEDI - Linux Control and Measurement Device Interface
  8. Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  9. This program is free software; you can redistribute it and/or modify
  10. it under the terms of the GNU General Public License as published by
  11. the Free Software Foundation; either version 2 of the License, or
  12. (at your option) any later version.
  13. This program is distributed in the hope that it will be useful,
  14. but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. GNU General Public License for more details.
  17. You should have received a copy of the GNU General Public License
  18. along with this program; if not, write to the Free Software
  19. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. ************************************************************************/
  21. /*
  22. Driver: gsc_hpdi
  23. Description: General Standards Corporation High
  24. Speed Parallel Digital Interface rs485 boards
  25. Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  26. Status: only receive mode works, transmit not supported
  27. Updated: 2003-02-20
  28. Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
  29. PMC-HPDI32
  30. Configuration options:
  31. [0] - PCI bus of device (optional)
  32. [1] - PCI slot of device (optional)
  33. There are some additional hpdi models available from GSC for which
  34. support could be added to this driver.
  35. */
  36. #include <linux/interrupt.h>
  37. #include "../comedidev.h"
  38. #include <linux/delay.h>
  39. #include "comedi_pci.h"
  40. #include "plx9080.h"
  41. #include "comedi_fc.h"
  42. static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it);
  43. static int hpdi_detach(struct comedi_device *dev);
  44. static void abort_dma(struct comedi_device *dev, unsigned int channel);
  45. static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
  46. static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
  47. struct comedi_cmd *cmd);
  48. static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
  49. static irqreturn_t handle_interrupt(int irq, void *d);
  50. static int dio_config_block_size(struct comedi_device *dev, unsigned int *data);
  51. #undef HPDI_DEBUG /* disable debugging messages */
  52. /* #define HPDI_DEBUG enable debugging code */
  53. #ifdef HPDI_DEBUG
  54. #define DEBUG_PRINT(format, args...) printk(format , ## args)
  55. #else
  56. #define DEBUG_PRINT(format, args...)
  57. #endif
  58. #define TIMER_BASE 50 /* 20MHz master clock */
  59. #define DMA_BUFFER_SIZE 0x10000
  60. #define NUM_DMA_BUFFERS 4
  61. #define NUM_DMA_DESCRIPTORS 256
  62. /* indices of base address regions */
  63. enum base_address_regions {
  64. PLX9080_BADDRINDEX = 0,
  65. HPDI_BADDRINDEX = 2,
  66. };
  67. enum hpdi_registers {
  68. FIRMWARE_REV_REG = 0x0,
  69. BOARD_CONTROL_REG = 0x4,
  70. BOARD_STATUS_REG = 0x8,
  71. TX_PROG_ALMOST_REG = 0xc,
  72. RX_PROG_ALMOST_REG = 0x10,
  73. FEATURES_REG = 0x14,
  74. FIFO_REG = 0x18,
  75. TX_STATUS_COUNT_REG = 0x1c,
  76. TX_LINE_VALID_COUNT_REG = 0x20,
  77. TX_LINE_INVALID_COUNT_REG = 0x24,
  78. RX_STATUS_COUNT_REG = 0x28,
  79. RX_LINE_COUNT_REG = 0x2c,
  80. INTERRUPT_CONTROL_REG = 0x30,
  81. INTERRUPT_STATUS_REG = 0x34,
  82. TX_CLOCK_DIVIDER_REG = 0x38,
  83. TX_FIFO_SIZE_REG = 0x40,
  84. RX_FIFO_SIZE_REG = 0x44,
  85. TX_FIFO_WORDS_REG = 0x48,
  86. RX_FIFO_WORDS_REG = 0x4c,
  87. INTERRUPT_EDGE_LEVEL_REG = 0x50,
  88. INTERRUPT_POLARITY_REG = 0x54,
  89. };
  90. int command_channel_valid(unsigned int channel)
  91. {
  92. if (channel == 0 || channel > 6) {
  93. printk(KERN_WARNING
  94. "gsc_hpdi: bug! invalid cable command channel\n");
  95. return 0;
  96. }
  97. return 1;
  98. }
  99. /* bit definitions */
  100. enum firmware_revision_bits {
  101. FEATURES_REG_PRESENT_BIT = 0x8000,
  102. };
  103. int firmware_revision(uint32_t fwr_bits)
  104. {
  105. return fwr_bits & 0xff;
  106. }
  107. int pcb_revision(uint32_t fwr_bits)
  108. {
  109. return (fwr_bits >> 8) & 0xff;
  110. }
  111. int hpdi_subid(uint32_t fwr_bits)
  112. {
  113. return (fwr_bits >> 16) & 0xff;
  114. }
  115. enum board_control_bits {
  116. BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */
  117. TX_FIFO_RESET_BIT = 0x2,
  118. RX_FIFO_RESET_BIT = 0x4,
  119. TX_ENABLE_BIT = 0x10,
  120. RX_ENABLE_BIT = 0x20,
  121. DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
  122. /* for ch 0, ch 1 can only transmit (when present) */
  123. LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
  124. START_TX_BIT = 0x10,
  125. CABLE_THROTTLE_ENABLE_BIT = 0x20,
  126. TEST_MODE_ENABLE_BIT = 0x80000000,
  127. };
  128. uint32_t command_discrete_output_bits(unsigned int channel, int output,
  129. int output_value)
  130. {
  131. uint32_t bits = 0;
  132. if (command_channel_valid(channel) == 0)
  133. return 0;
  134. if (output) {
  135. bits |= 0x1 << (16 + channel);
  136. if (output_value)
  137. bits |= 0x1 << (24 + channel);
  138. } else
  139. bits |= 0x1 << (24 + channel);
  140. return bits;
  141. }
  142. enum board_status_bits {
  143. COMMAND_LINE_STATUS_MASK = 0x7f,
  144. TX_IN_PROGRESS_BIT = 0x80,
  145. TX_NOT_EMPTY_BIT = 0x100,
  146. TX_NOT_ALMOST_EMPTY_BIT = 0x200,
  147. TX_NOT_ALMOST_FULL_BIT = 0x400,
  148. TX_NOT_FULL_BIT = 0x800,
  149. RX_NOT_EMPTY_BIT = 0x1000,
  150. RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
  151. RX_NOT_ALMOST_FULL_BIT = 0x4000,
  152. RX_NOT_FULL_BIT = 0x8000,
  153. BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
  154. BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
  155. TX_OVERRUN_BIT = 0x200000,
  156. RX_UNDERRUN_BIT = 0x400000,
  157. RX_OVERRUN_BIT = 0x800000,
  158. };
  159. uint32_t almost_full_bits(unsigned int num_words)
  160. {
  161. /* XXX need to add or subtract one? */
  162. return (num_words << 16) & 0xff0000;
  163. }
  164. uint32_t almost_empty_bits(unsigned int num_words)
  165. {
  166. return num_words & 0xffff;
  167. }
  168. unsigned int almost_full_num_words(uint32_t bits)
  169. {
  170. /* XXX need to add or subtract one? */
  171. return (bits >> 16) & 0xffff;
  172. }
  173. unsigned int almost_empty_num_words(uint32_t bits)
  174. {
  175. return bits & 0xffff;
  176. }
  177. enum features_bits {
  178. FIFO_SIZE_PRESENT_BIT = 0x1,
  179. FIFO_WORDS_PRESENT_BIT = 0x2,
  180. LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
  181. GPIO_SUPPORTED_BIT = 0x8,
  182. PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
  183. OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
  184. };
  185. enum interrupt_sources {
  186. FRAME_VALID_START_INTR = 0,
  187. FRAME_VALID_END_INTR = 1,
  188. TX_FIFO_EMPTY_INTR = 8,
  189. TX_FIFO_ALMOST_EMPTY_INTR = 9,
  190. TX_FIFO_ALMOST_FULL_INTR = 10,
  191. TX_FIFO_FULL_INTR = 11,
  192. RX_EMPTY_INTR = 12,
  193. RX_ALMOST_EMPTY_INTR = 13,
  194. RX_ALMOST_FULL_INTR = 14,
  195. RX_FULL_INTR = 15,
  196. };
  197. int command_intr_source(unsigned int channel)
  198. {
  199. if (command_channel_valid(channel) == 0)
  200. channel = 1;
  201. return channel + 1;
  202. }
  203. uint32_t intr_bit(int interrupt_source)
  204. {
  205. return 0x1 << interrupt_source;
  206. }
  207. uint32_t tx_clock_divisor_bits(unsigned int divisor)
  208. {
  209. return divisor & 0xff;
  210. }
  211. unsigned int fifo_size(uint32_t fifo_size_bits)
  212. {
  213. return fifo_size_bits & 0xfffff;
  214. }
  215. unsigned int fifo_words(uint32_t fifo_words_bits)
  216. {
  217. return fifo_words_bits & 0xfffff;
  218. }
  219. uint32_t intr_edge_bit(int interrupt_source)
  220. {
  221. return 0x1 << interrupt_source;
  222. }
  223. uint32_t intr_active_high_bit(int interrupt_source)
  224. {
  225. return 0x1 << interrupt_source;
  226. }
  227. struct hpdi_board {
  228. char *name;
  229. int device_id; /* pci device id */
  230. int subdevice_id; /* pci subdevice id */
  231. };
  232. static const struct hpdi_board hpdi_boards[] = {
  233. {
  234. .name = "pci-hpdi32",
  235. .device_id = PCI_DEVICE_ID_PLX_9080,
  236. .subdevice_id = 0x2400,
  237. },
  238. #if 0
  239. {
  240. .name = "pxi-hpdi32",
  241. .device_id = 0x9656,
  242. .subdevice_id = 0x2705,
  243. },
  244. #endif
  245. };
  246. static DEFINE_PCI_DEVICE_TABLE(hpdi_pci_table) = {
  247. {
  248. PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
  249. 0x2400, 0, 0, 0}, {
  250. 0}
  251. };
  252. MODULE_DEVICE_TABLE(pci, hpdi_pci_table);
  253. static inline struct hpdi_board *board(const struct comedi_device *dev)
  254. {
  255. return (struct hpdi_board *)dev->board_ptr;
  256. }
  257. struct hpdi_private {
  258. struct pci_dev *hw_dev; /* pointer to board's pci_dev struct */
  259. /* base addresses (physical) */
  260. resource_size_t plx9080_phys_iobase;
  261. resource_size_t hpdi_phys_iobase;
  262. /* base addresses (ioremapped) */
  263. void *plx9080_iobase;
  264. void *hpdi_iobase;
  265. uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
  266. /* physical addresses of dma buffers */
  267. dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
  268. /* array of dma descriptors read by plx9080, allocated to get proper
  269. * alignment */
  270. struct plx_dma_desc *dma_desc;
  271. /* physical address of dma descriptor array */
  272. dma_addr_t dma_desc_phys_addr;
  273. unsigned int num_dma_descriptors;
  274. /* pointer to start of buffers indexed by descriptor */
  275. uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
  276. /* index of the dma descriptor that is currently being used */
  277. volatile unsigned int dma_desc_index;
  278. unsigned int tx_fifo_size;
  279. unsigned int rx_fifo_size;
  280. volatile unsigned long dio_count;
  281. /* software copies of values written to hpdi registers */
  282. volatile uint32_t bits[24];
  283. /* number of bytes at which to generate COMEDI_CB_BLOCK events */
  284. volatile unsigned int block_size;
  285. unsigned dio_config_output:1;
  286. };
  287. static inline struct hpdi_private *priv(struct comedi_device *dev)
  288. {
  289. return dev->private;
  290. }
  291. static struct comedi_driver driver_hpdi = {
  292. .driver_name = "gsc_hpdi",
  293. .module = THIS_MODULE,
  294. .attach = hpdi_attach,
  295. .detach = hpdi_detach,
  296. };
  297. static int __devinit driver_hpdi_pci_probe(struct pci_dev *dev,
  298. const struct pci_device_id *ent)
  299. {
  300. return comedi_pci_auto_config(dev, driver_hpdi.driver_name);
  301. }
  302. static void __devexit driver_hpdi_pci_remove(struct pci_dev *dev)
  303. {
  304. comedi_pci_auto_unconfig(dev);
  305. }
  306. static struct pci_driver driver_hpdi_pci_driver = {
  307. .id_table = hpdi_pci_table,
  308. .probe = &driver_hpdi_pci_probe,
  309. .remove = __devexit_p(&driver_hpdi_pci_remove)
  310. };
  311. static int __init driver_hpdi_init_module(void)
  312. {
  313. int retval;
  314. retval = comedi_driver_register(&driver_hpdi);
  315. if (retval < 0)
  316. return retval;
  317. driver_hpdi_pci_driver.name = (char *)driver_hpdi.driver_name;
  318. return pci_register_driver(&driver_hpdi_pci_driver);
  319. }
  320. static void __exit driver_hpdi_cleanup_module(void)
  321. {
  322. pci_unregister_driver(&driver_hpdi_pci_driver);
  323. comedi_driver_unregister(&driver_hpdi);
  324. }
  325. module_init(driver_hpdi_init_module);
  326. module_exit(driver_hpdi_cleanup_module);
  327. static int dio_config_insn(struct comedi_device *dev,
  328. struct comedi_subdevice *s, struct comedi_insn *insn,
  329. unsigned int *data)
  330. {
  331. switch (data[0]) {
  332. case INSN_CONFIG_DIO_OUTPUT:
  333. priv(dev)->dio_config_output = 1;
  334. return insn->n;
  335. break;
  336. case INSN_CONFIG_DIO_INPUT:
  337. priv(dev)->dio_config_output = 0;
  338. return insn->n;
  339. break;
  340. case INSN_CONFIG_DIO_QUERY:
  341. data[1] =
  342. priv(dev)->dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT;
  343. return insn->n;
  344. break;
  345. case INSN_CONFIG_BLOCK_SIZE:
  346. return dio_config_block_size(dev, data);
  347. break;
  348. default:
  349. break;
  350. }
  351. return -EINVAL;
  352. }
  353. static void disable_plx_interrupts(struct comedi_device *dev)
  354. {
  355. writel(0, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
  356. }
  357. /* initialize plx9080 chip */
  358. static void init_plx9080(struct comedi_device *dev)
  359. {
  360. uint32_t bits;
  361. void *plx_iobase = priv(dev)->plx9080_iobase;
  362. /* plx9080 dump */
  363. DEBUG_PRINT(" plx interrupt status 0x%x\n",
  364. readl(plx_iobase + PLX_INTRCS_REG));
  365. DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
  366. DEBUG_PRINT(" plx control reg 0x%x\n",
  367. readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG));
  368. DEBUG_PRINT(" plx revision 0x%x\n",
  369. readl(plx_iobase + PLX_REVISION_REG));
  370. DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
  371. readl(plx_iobase + PLX_DMA0_MODE_REG));
  372. DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
  373. readl(plx_iobase + PLX_DMA1_MODE_REG));
  374. DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
  375. readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
  376. DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
  377. readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
  378. DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
  379. readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
  380. DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
  381. readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
  382. DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
  383. readb(plx_iobase + PLX_DMA0_CS_REG));
  384. DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
  385. readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
  386. DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
  387. #ifdef __BIG_ENDIAN
  388. bits = BIGEND_DMA0 | BIGEND_DMA1;
  389. #else
  390. bits = 0;
  391. #endif
  392. writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
  393. disable_plx_interrupts(dev);
  394. abort_dma(dev, 0);
  395. abort_dma(dev, 1);
  396. /* configure dma0 mode */
  397. bits = 0;
  398. /* enable ready input */
  399. bits |= PLX_DMA_EN_READYIN_BIT;
  400. /* enable dma chaining */
  401. bits |= PLX_EN_CHAIN_BIT;
  402. /* enable interrupt on dma done
  403. * (probably don't need this, since chain never finishes) */
  404. bits |= PLX_EN_DMA_DONE_INTR_BIT;
  405. /* don't increment local address during transfers
  406. * (we are transferring from a fixed fifo register) */
  407. bits |= PLX_LOCAL_ADDR_CONST_BIT;
  408. /* route dma interrupt to pci bus */
  409. bits |= PLX_DMA_INTR_PCI_BIT;
  410. /* enable demand mode */
  411. bits |= PLX_DEMAND_MODE_BIT;
  412. /* enable local burst mode */
  413. bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
  414. bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
  415. writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
  416. }
  417. /* Allocate and initialize the subdevice structures.
  418. */
  419. static int setup_subdevices(struct comedi_device *dev)
  420. {
  421. struct comedi_subdevice *s;
  422. if (alloc_subdevices(dev, 1) < 0)
  423. return -ENOMEM;
  424. s = dev->subdevices + 0;
  425. /* analog input subdevice */
  426. dev->read_subdev = s;
  427. /* dev->write_subdev = s; */
  428. s->type = COMEDI_SUBD_DIO;
  429. s->subdev_flags =
  430. SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
  431. s->n_chan = 32;
  432. s->len_chanlist = 32;
  433. s->maxdata = 1;
  434. s->range_table = &range_digital;
  435. s->insn_config = dio_config_insn;
  436. s->do_cmd = hpdi_cmd;
  437. s->do_cmdtest = hpdi_cmd_test;
  438. s->cancel = hpdi_cancel;
  439. return 0;
  440. }
  441. static int init_hpdi(struct comedi_device *dev)
  442. {
  443. uint32_t plx_intcsr_bits;
  444. writel(BOARD_RESET_BIT, priv(dev)->hpdi_iobase + BOARD_CONTROL_REG);
  445. udelay(10);
  446. writel(almost_empty_bits(32) | almost_full_bits(32),
  447. priv(dev)->hpdi_iobase + RX_PROG_ALMOST_REG);
  448. writel(almost_empty_bits(32) | almost_full_bits(32),
  449. priv(dev)->hpdi_iobase + TX_PROG_ALMOST_REG);
  450. priv(dev)->tx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
  451. TX_FIFO_SIZE_REG));
  452. priv(dev)->rx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
  453. RX_FIFO_SIZE_REG));
  454. writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
  455. /* enable interrupts */
  456. plx_intcsr_bits =
  457. ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
  458. ICS_DMA0_E;
  459. writel(plx_intcsr_bits, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
  460. return 0;
  461. }
  462. /* setup dma descriptors so a link completes every 'transfer_size' bytes */
  463. static int setup_dma_descriptors(struct comedi_device *dev,
  464. unsigned int transfer_size)
  465. {
  466. unsigned int buffer_index, buffer_offset;
  467. uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
  468. PLX_XFER_LOCAL_TO_PCI;
  469. unsigned int i;
  470. if (transfer_size > DMA_BUFFER_SIZE)
  471. transfer_size = DMA_BUFFER_SIZE;
  472. transfer_size -= transfer_size % sizeof(uint32_t);
  473. if (transfer_size == 0)
  474. return -1;
  475. DEBUG_PRINT(" transfer_size %i\n", transfer_size);
  476. DEBUG_PRINT(" descriptors at 0x%lx\n",
  477. (unsigned long)priv(dev)->dma_desc_phys_addr);
  478. buffer_offset = 0;
  479. buffer_index = 0;
  480. for (i = 0; i < NUM_DMA_DESCRIPTORS &&
  481. buffer_index < NUM_DMA_BUFFERS; i++) {
  482. priv(dev)->dma_desc[i].pci_start_addr =
  483. cpu_to_le32(priv(dev)->dio_buffer_phys_addr[buffer_index] +
  484. buffer_offset);
  485. priv(dev)->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
  486. priv(dev)->dma_desc[i].transfer_size =
  487. cpu_to_le32(transfer_size);
  488. priv(dev)->dma_desc[i].next =
  489. cpu_to_le32((priv(dev)->dma_desc_phys_addr + (i +
  490. 1) *
  491. sizeof(priv(dev)->dma_desc[0])) | next_bits);
  492. priv(dev)->desc_dio_buffer[i] =
  493. priv(dev)->dio_buffer[buffer_index] +
  494. (buffer_offset / sizeof(uint32_t));
  495. buffer_offset += transfer_size;
  496. if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
  497. buffer_offset = 0;
  498. buffer_index++;
  499. }
  500. DEBUG_PRINT(" desc %i\n", i);
  501. DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n",
  502. priv(dev)->desc_dio_buffer[i],
  503. (unsigned long)priv(dev)->dma_desc[i].
  504. pci_start_addr);
  505. DEBUG_PRINT(" next 0x%lx\n",
  506. (unsigned long)priv(dev)->dma_desc[i].next);
  507. }
  508. priv(dev)->num_dma_descriptors = i;
  509. /* fix last descriptor to point back to first */
  510. priv(dev)->dma_desc[i - 1].next =
  511. cpu_to_le32(priv(dev)->dma_desc_phys_addr | next_bits);
  512. DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1,
  513. (unsigned long)priv(dev)->dma_desc[i - 1].next);
  514. priv(dev)->block_size = transfer_size;
  515. return transfer_size;
  516. }
  517. static int hpdi_attach(struct comedi_device *dev, struct comedi_devconfig *it)
  518. {
  519. struct pci_dev *pcidev;
  520. int i;
  521. int retval;
  522. printk(KERN_WARNING "comedi%d: gsc_hpdi\n", dev->minor);
  523. if (alloc_private(dev, sizeof(struct hpdi_private)) < 0)
  524. return -ENOMEM;
  525. pcidev = NULL;
  526. for (i = 0; i < ARRAY_SIZE(hpdi_boards) &&
  527. dev->board_ptr == NULL; i++) {
  528. do {
  529. pcidev = pci_get_subsys(PCI_VENDOR_ID_PLX,
  530. hpdi_boards[i].device_id,
  531. PCI_VENDOR_ID_PLX,
  532. hpdi_boards[i].subdevice_id,
  533. pcidev);
  534. /* was a particular bus/slot requested? */
  535. if (it->options[0] || it->options[1]) {
  536. /* are we on the wrong bus/slot? */
  537. if (pcidev->bus->number != it->options[0] ||
  538. PCI_SLOT(pcidev->devfn) != it->options[1])
  539. continue;
  540. }
  541. if (pcidev) {
  542. priv(dev)->hw_dev = pcidev;
  543. dev->board_ptr = hpdi_boards + i;
  544. break;
  545. }
  546. } while (pcidev != NULL);
  547. }
  548. if (dev->board_ptr == NULL) {
  549. printk(KERN_WARNING "gsc_hpdi: no hpdi card found\n");
  550. return -EIO;
  551. }
  552. printk(KERN_WARNING
  553. "gsc_hpdi: found %s on bus %i, slot %i\n", board(dev)->name,
  554. pcidev->bus->number, PCI_SLOT(pcidev->devfn));
  555. if (comedi_pci_enable(pcidev, driver_hpdi.driver_name)) {
  556. printk(KERN_WARNING
  557. " failed enable PCI device and request regions\n");
  558. return -EIO;
  559. }
  560. pci_set_master(pcidev);
  561. /* Initialize dev->board_name */
  562. dev->board_name = board(dev)->name;
  563. priv(dev)->plx9080_phys_iobase =
  564. pci_resource_start(pcidev, PLX9080_BADDRINDEX);
  565. priv(dev)->hpdi_phys_iobase =
  566. pci_resource_start(pcidev, HPDI_BADDRINDEX);
  567. /* remap, won't work with 2.0 kernels but who cares */
  568. priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
  569. pci_resource_len(pcidev,
  570. PLX9080_BADDRINDEX));
  571. priv(dev)->hpdi_iobase =
  572. ioremap(priv(dev)->hpdi_phys_iobase,
  573. pci_resource_len(pcidev, HPDI_BADDRINDEX));
  574. if (!priv(dev)->plx9080_iobase || !priv(dev)->hpdi_iobase) {
  575. printk(KERN_WARNING " failed to remap io memory\n");
  576. return -ENOMEM;
  577. }
  578. DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
  579. DEBUG_PRINT(" hpdi remapped to 0x%p\n", priv(dev)->hpdi_iobase);
  580. init_plx9080(dev);
  581. /* get irq */
  582. if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
  583. driver_hpdi.driver_name, dev)) {
  584. printk(KERN_WARNING
  585. " unable to allocate irq %u\n", pcidev->irq);
  586. return -EINVAL;
  587. }
  588. dev->irq = pcidev->irq;
  589. printk(KERN_WARNING " irq %u\n", dev->irq);
  590. /* alocate pci dma buffers */
  591. for (i = 0; i < NUM_DMA_BUFFERS; i++) {
  592. priv(dev)->dio_buffer[i] =
  593. pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
  594. &priv(dev)->dio_buffer_phys_addr[i]);
  595. DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n",
  596. priv(dev)->dio_buffer[i],
  597. (unsigned long)priv(dev)->dio_buffer_phys_addr[i]);
  598. }
  599. /* allocate dma descriptors */
  600. priv(dev)->dma_desc = pci_alloc_consistent(priv(dev)->hw_dev,
  601. sizeof(struct plx_dma_desc) *
  602. NUM_DMA_DESCRIPTORS,
  603. &priv(dev)->
  604. dma_desc_phys_addr);
  605. if (priv(dev)->dma_desc_phys_addr & 0xf) {
  606. printk(KERN_WARNING
  607. " dma descriptors not quad-word aligned (bug)\n");
  608. return -EIO;
  609. }
  610. retval = setup_dma_descriptors(dev, 0x1000);
  611. if (retval < 0)
  612. return retval;
  613. retval = setup_subdevices(dev);
  614. if (retval < 0)
  615. return retval;
  616. return init_hpdi(dev);
  617. }
  618. static int hpdi_detach(struct comedi_device *dev)
  619. {
  620. unsigned int i;
  621. printk(KERN_WARNING "comedi%d: gsc_hpdi: remove\n", dev->minor);
  622. if (dev->irq)
  623. free_irq(dev->irq, dev);
  624. if ((priv(dev)) && (priv(dev)->hw_dev)) {
  625. if (priv(dev)->plx9080_iobase) {
  626. disable_plx_interrupts(dev);
  627. iounmap((void *)priv(dev)->plx9080_iobase);
  628. }
  629. if (priv(dev)->hpdi_iobase)
  630. iounmap((void *)priv(dev)->hpdi_iobase);
  631. /* free pci dma buffers */
  632. for (i = 0; i < NUM_DMA_BUFFERS; i++) {
  633. if (priv(dev)->dio_buffer[i])
  634. pci_free_consistent(priv(dev)->hw_dev,
  635. DMA_BUFFER_SIZE,
  636. priv(dev)->
  637. dio_buffer[i],
  638. priv
  639. (dev)->dio_buffer_phys_addr
  640. [i]);
  641. }
  642. /* free dma descriptors */
  643. if (priv(dev)->dma_desc)
  644. pci_free_consistent(priv(dev)->hw_dev,
  645. sizeof(struct plx_dma_desc)
  646. * NUM_DMA_DESCRIPTORS,
  647. priv(dev)->dma_desc,
  648. priv(dev)->
  649. dma_desc_phys_addr);
  650. if (priv(dev)->hpdi_phys_iobase)
  651. comedi_pci_disable(priv(dev)->hw_dev);
  652. pci_dev_put(priv(dev)->hw_dev);
  653. }
  654. return 0;
  655. }
  656. static int dio_config_block_size(struct comedi_device *dev, unsigned int *data)
  657. {
  658. unsigned int requested_block_size;
  659. int retval;
  660. requested_block_size = data[1];
  661. retval = setup_dma_descriptors(dev, requested_block_size);
  662. if (retval < 0)
  663. return retval;
  664. data[1] = retval;
  665. return 2;
  666. }
  667. static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
  668. struct comedi_cmd *cmd)
  669. {
  670. int err = 0;
  671. int tmp;
  672. int i;
  673. /* step 1: make sure trigger sources are trivially valid */
  674. tmp = cmd->start_src;
  675. cmd->start_src &= TRIG_NOW;
  676. if (!cmd->start_src || tmp != cmd->start_src)
  677. err++;
  678. tmp = cmd->scan_begin_src;
  679. cmd->scan_begin_src &= TRIG_EXT;
  680. if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
  681. err++;
  682. tmp = cmd->convert_src;
  683. cmd->convert_src &= TRIG_NOW;
  684. if (!cmd->convert_src || tmp != cmd->convert_src)
  685. err++;
  686. tmp = cmd->scan_end_src;
  687. cmd->scan_end_src &= TRIG_COUNT;
  688. if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
  689. err++;
  690. tmp = cmd->stop_src;
  691. cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
  692. if (!cmd->stop_src || tmp != cmd->stop_src)
  693. err++;
  694. if (err)
  695. return 1;
  696. /* step 2: make sure trigger sources are unique and mutually
  697. * compatible */
  698. /* uniqueness check */
  699. if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
  700. err++;
  701. if (err)
  702. return 2;
  703. /* step 3: make sure arguments are trivially compatible */
  704. if (!cmd->chanlist_len) {
  705. cmd->chanlist_len = 32;
  706. err++;
  707. }
  708. if (cmd->scan_end_arg != cmd->chanlist_len) {
  709. cmd->scan_end_arg = cmd->chanlist_len;
  710. err++;
  711. }
  712. switch (cmd->stop_src) {
  713. case TRIG_COUNT:
  714. if (!cmd->stop_arg) {
  715. cmd->stop_arg = 1;
  716. err++;
  717. }
  718. break;
  719. case TRIG_NONE:
  720. if (cmd->stop_arg != 0) {
  721. cmd->stop_arg = 0;
  722. err++;
  723. }
  724. break;
  725. default:
  726. break;
  727. }
  728. if (err)
  729. return 3;
  730. /* step 4: fix up any arguments */
  731. if (err)
  732. return 4;
  733. if (!cmd->chanlist)
  734. return 0;
  735. for (i = 1; i < cmd->chanlist_len; i++) {
  736. if (CR_CHAN(cmd->chanlist[i]) != i) {
  737. /* XXX could support 8 or 16 channels */
  738. comedi_error(dev,
  739. "chanlist must be ch 0 to 31 in order");
  740. err++;
  741. break;
  742. }
  743. }
  744. if (err)
  745. return 5;
  746. return 0;
  747. }
  748. static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
  749. struct comedi_cmd *cmd)
  750. {
  751. if (priv(dev)->dio_config_output)
  752. return -EINVAL;
  753. else
  754. return di_cmd_test(dev, s, cmd);
  755. }
  756. static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits,
  757. unsigned int offset)
  758. {
  759. writel(bits | priv(dev)->bits[offset / sizeof(uint32_t)],
  760. priv(dev)->hpdi_iobase + offset);
  761. }
  762. static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
  763. {
  764. uint32_t bits;
  765. unsigned long flags;
  766. struct comedi_async *async = s->async;
  767. struct comedi_cmd *cmd = &async->cmd;
  768. hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
  769. DEBUG_PRINT("hpdi: in di_cmd\n");
  770. abort_dma(dev, 0);
  771. priv(dev)->dma_desc_index = 0;
  772. /* These register are supposedly unused during chained dma,
  773. * but I have found that left over values from last operation
  774. * occasionally cause problems with transfer of first dma
  775. * block. Initializing them to zero seems to fix the problem. */
  776. writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
  777. writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
  778. writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
  779. /* give location of first dma descriptor */
  780. bits =
  781. priv(dev)->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
  782. PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
  783. writel(bits, priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
  784. /* spinlock for plx dma control/status reg */
  785. spin_lock_irqsave(&dev->spinlock, flags);
  786. /* enable dma transfer */
  787. writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
  788. priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
  789. spin_unlock_irqrestore(&dev->spinlock, flags);
  790. if (cmd->stop_src == TRIG_COUNT)
  791. priv(dev)->dio_count = cmd->stop_arg;
  792. else
  793. priv(dev)->dio_count = 1;
  794. /* clear over/under run status flags */
  795. writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
  796. priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
  797. /* enable interrupts */
  798. writel(intr_bit(RX_FULL_INTR),
  799. priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
  800. DEBUG_PRINT("hpdi: starting rx\n");
  801. hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
  802. return 0;
  803. }
  804. static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
  805. {
  806. if (priv(dev)->dio_config_output)
  807. return -EINVAL;
  808. else
  809. return di_cmd(dev, s);
  810. }
  811. static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
  812. {
  813. struct comedi_async *async = dev->read_subdev->async;
  814. uint32_t next_transfer_addr;
  815. int j;
  816. int num_samples = 0;
  817. void *pci_addr_reg;
  818. if (channel)
  819. pci_addr_reg =
  820. priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
  821. else
  822. pci_addr_reg =
  823. priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
  824. /* loop until we have read all the full buffers */
  825. j = 0;
  826. for (next_transfer_addr = readl(pci_addr_reg);
  827. (next_transfer_addr <
  828. le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index].
  829. pci_start_addr)
  830. || next_transfer_addr >=
  831. le32_to_cpu(priv(dev)->dma_desc[priv(dev)->dma_desc_index].
  832. pci_start_addr) + priv(dev)->block_size)
  833. && j < priv(dev)->num_dma_descriptors; j++) {
  834. /* transfer data from dma buffer to comedi buffer */
  835. num_samples = priv(dev)->block_size / sizeof(uint32_t);
  836. if (async->cmd.stop_src == TRIG_COUNT) {
  837. if (num_samples > priv(dev)->dio_count)
  838. num_samples = priv(dev)->dio_count;
  839. priv(dev)->dio_count -= num_samples;
  840. }
  841. cfc_write_array_to_buffer(dev->read_subdev,
  842. priv(dev)->desc_dio_buffer[priv(dev)->
  843. dma_desc_index],
  844. num_samples * sizeof(uint32_t));
  845. priv(dev)->dma_desc_index++;
  846. priv(dev)->dma_desc_index %= priv(dev)->num_dma_descriptors;
  847. DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long)
  848. priv(dev)->dma_desc[priv(dev)->dma_desc_index].
  849. next);
  850. DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
  851. }
  852. /* XXX check for buffer overrun somehow */
  853. }
  854. static irqreturn_t handle_interrupt(int irq, void *d)
  855. {
  856. struct comedi_device *dev = d;
  857. struct comedi_subdevice *s = dev->read_subdev;
  858. struct comedi_async *async = s->async;
  859. uint32_t hpdi_intr_status, hpdi_board_status;
  860. uint32_t plx_status;
  861. uint32_t plx_bits;
  862. uint8_t dma0_status, dma1_status;
  863. unsigned long flags;
  864. if (!dev->attached)
  865. return IRQ_NONE;
  866. plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
  867. if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
  868. return IRQ_NONE;
  869. hpdi_intr_status = readl(priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
  870. hpdi_board_status = readl(priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
  871. async->events = 0;
  872. if (hpdi_intr_status) {
  873. DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status);
  874. writel(hpdi_intr_status,
  875. priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
  876. }
  877. /* spin lock makes sure no one else changes plx dma control reg */
  878. spin_lock_irqsave(&dev->spinlock, flags);
  879. dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
  880. if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
  881. writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
  882. priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
  883. DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
  884. if (dma0_status & PLX_DMA_EN_BIT)
  885. drain_dma_buffers(dev, 0);
  886. DEBUG_PRINT(" cleared dma ch0 interrupt\n");
  887. }
  888. spin_unlock_irqrestore(&dev->spinlock, flags);
  889. /* spin lock makes sure no one else changes plx dma control reg */
  890. spin_lock_irqsave(&dev->spinlock, flags);
  891. dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
  892. if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */
  893. writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
  894. priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
  895. DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
  896. DEBUG_PRINT(" cleared dma ch1 interrupt\n");
  897. }
  898. spin_unlock_irqrestore(&dev->spinlock, flags);
  899. /* clear possible plx9080 interrupt sources */
  900. if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
  901. plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
  902. writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
  903. DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
  904. }
  905. if (hpdi_board_status & RX_OVERRUN_BIT) {
  906. comedi_error(dev, "rx fifo overrun");
  907. async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
  908. DEBUG_PRINT("dma0_status 0x%x\n",
  909. (int)readb(priv(dev)->plx9080_iobase +
  910. PLX_DMA0_CS_REG));
  911. }
  912. if (hpdi_board_status & RX_UNDERRUN_BIT) {
  913. comedi_error(dev, "rx fifo underrun");
  914. async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
  915. }
  916. if (priv(dev)->dio_count == 0)
  917. async->events |= COMEDI_CB_EOA;
  918. DEBUG_PRINT("board status 0x%x, ", hpdi_board_status);
  919. DEBUG_PRINT("plx status 0x%x\n", plx_status);
  920. if (async->events)
  921. DEBUG_PRINT(" events 0x%x\n", async->events);
  922. cfc_handle_events(dev, s);
  923. return IRQ_HANDLED;
  924. }
  925. static void abort_dma(struct comedi_device *dev, unsigned int channel)
  926. {
  927. unsigned long flags;
  928. /* spinlock for plx dma control/status reg */
  929. spin_lock_irqsave(&dev->spinlock, flags);
  930. plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
  931. spin_unlock_irqrestore(&dev->spinlock, flags);
  932. }
  933. static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
  934. {
  935. hpdi_writel(dev, 0, BOARD_CONTROL_REG);
  936. writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
  937. abort_dma(dev, 0);
  938. return 0;
  939. }
  940. MODULE_AUTHOR("Comedi http://www.comedi.org");
  941. MODULE_DESCRIPTION("Comedi low-level driver");
  942. MODULE_LICENSE("GPL");