/drivers/staging/brcm80211/brcmsmac/aiutils.h

https://bitbucket.org/slukk/jb-tsm-kernel-4.2 · C Header · 546 lines · 353 code · 74 blank · 119 comment · 23 complexity · 0d7a2542f118f94bfd83722a6cd963ce MD5 · raw file

  1. /*
  2. * Copyright (c) 2011 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _aiutils_h_
  17. #define _aiutils_h_
  18. /* cpp contortions to concatenate w/arg prescan */
  19. #ifndef PAD
  20. #define _PADLINE(line) pad ## line
  21. #define _XSTR(line) _PADLINE(line)
  22. #define PAD _XSTR(__LINE__)
  23. #endif
  24. /* Include the soci specific files */
  25. #include <aidmp.h>
  26. /*
  27. * SOC Interconnect Address Map.
  28. * All regions may not exist on all chips.
  29. */
  30. /* Physical SDRAM */
  31. #define SI_SDRAM_BASE 0x00000000
  32. /* Host Mode sb2pcitranslation0 (64 MB) */
  33. #define SI_PCI_MEM 0x08000000
  34. #define SI_PCI_MEM_SZ (64 * 1024 * 1024)
  35. /* Host Mode sb2pcitranslation1 (64 MB) */
  36. #define SI_PCI_CFG 0x0c000000
  37. /* Byteswapped Physical SDRAM */
  38. #define SI_SDRAM_SWAPPED 0x10000000
  39. /* Region 2 for sdram (512 MB) */
  40. #define SI_SDRAM_R2 0x80000000
  41. #ifdef SI_ENUM_BASE_VARIABLE
  42. #define SI_ENUM_BASE (sii->pub.si_enum_base)
  43. #else
  44. #define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
  45. #endif /* SI_ENUM_BASE_VARIABLE */
  46. /* Wrapper space base */
  47. #define SI_WRAP_BASE 0x18100000
  48. /* each core gets 4Kbytes for registers */
  49. #define SI_CORE_SIZE 0x1000
  50. /*
  51. * Max cores (this is arbitrary, for software
  52. * convenience and could be changed if we
  53. * make any larger chips
  54. */
  55. #define SI_MAXCORES 16
  56. /* On-chip RAM on chips that also have DDR */
  57. #define SI_FASTRAM 0x19000000
  58. #define SI_FASTRAM_SWAPPED 0x19800000
  59. /* Flash Region 2 (region 1 shadowed here) */
  60. #define SI_FLASH2 0x1c000000
  61. /* Size of Flash Region 2 */
  62. #define SI_FLASH2_SZ 0x02000000
  63. /* ARM Cortex-M3 ROM */
  64. #define SI_ARMCM3_ROM 0x1e000000
  65. /* MIPS Flash Region 1 */
  66. #define SI_FLASH1 0x1fc00000
  67. /* MIPS Size of Flash Region 1 */
  68. #define SI_FLASH1_SZ 0x00400000
  69. /* ARM7TDMI-S ROM */
  70. #define SI_ARM7S_ROM 0x20000000
  71. /* ARM Cortex-M3 SRAM Region 2 */
  72. #define SI_ARMCM3_SRAM2 0x60000000
  73. /* ARM7TDMI-S SRAM Region 2 */
  74. #define SI_ARM7S_SRAM2 0x80000000
  75. /* ARM Flash Region 1 */
  76. #define SI_ARM_FLASH1 0xffff0000
  77. /* ARM Size of Flash Region 1 */
  78. #define SI_ARM_FLASH1_SZ 0x00010000
  79. /* Client Mode sb2pcitranslation2 (1 GB) */
  80. #define SI_PCI_DMA 0x40000000
  81. /* Client Mode sb2pcitranslation2 (1 GB) */
  82. #define SI_PCI_DMA2 0x80000000
  83. /* Client Mode sb2pcitranslation2 size in bytes */
  84. #define SI_PCI_DMA_SZ 0x40000000
  85. /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
  86. #define SI_PCIE_DMA_L32 0x00000000
  87. /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
  88. #define SI_PCIE_DMA_H32 0x80000000
  89. /* core codes */
  90. #define NODEV_CORE_ID 0x700 /* Invalid coreid */
  91. #define CC_CORE_ID 0x800 /* chipcommon core */
  92. #define ILINE20_CORE_ID 0x801 /* iline20 core */
  93. #define SRAM_CORE_ID 0x802 /* sram core */
  94. #define SDRAM_CORE_ID 0x803 /* sdram core */
  95. #define PCI_CORE_ID 0x804 /* pci core */
  96. #define MIPS_CORE_ID 0x805 /* mips core */
  97. #define ENET_CORE_ID 0x806 /* enet mac core */
  98. #define CODEC_CORE_ID 0x807 /* v90 codec core */
  99. #define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
  100. #define ADSL_CORE_ID 0x809 /* ADSL core */
  101. #define ILINE100_CORE_ID 0x80a /* iline100 core */
  102. #define IPSEC_CORE_ID 0x80b /* ipsec core */
  103. #define UTOPIA_CORE_ID 0x80c /* utopia core */
  104. #define PCMCIA_CORE_ID 0x80d /* pcmcia core */
  105. #define SOCRAM_CORE_ID 0x80e /* internal memory core */
  106. #define MEMC_CORE_ID 0x80f /* memc sdram core */
  107. #define OFDM_CORE_ID 0x810 /* OFDM phy core */
  108. #define EXTIF_CORE_ID 0x811 /* external interface core */
  109. #define D11_CORE_ID 0x812 /* 802.11 MAC core */
  110. #define APHY_CORE_ID 0x813 /* 802.11a phy core */
  111. #define BPHY_CORE_ID 0x814 /* 802.11b phy core */
  112. #define GPHY_CORE_ID 0x815 /* 802.11g phy core */
  113. #define MIPS33_CORE_ID 0x816 /* mips3302 core */
  114. #define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
  115. #define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
  116. #define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
  117. #define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
  118. #define SDIOH_CORE_ID 0x81b /* sdio host core */
  119. #define ROBO_CORE_ID 0x81c /* roboswitch core */
  120. #define ATA100_CORE_ID 0x81d /* parallel ATA core */
  121. #define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
  122. #define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
  123. #define PCIE_CORE_ID 0x820 /* pci express core */
  124. #define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
  125. #define SRAMC_CORE_ID 0x822 /* SRAM controller core */
  126. #define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
  127. #define ARM11_CORE_ID 0x824 /* ARM 1176 core */
  128. #define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
  129. #define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
  130. #define PMU_CORE_ID 0x827 /* PMU core */
  131. #define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
  132. #define SDIOD_CORE_ID 0x829 /* SDIO device core */
  133. #define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
  134. #define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
  135. #define MIPS74K_CORE_ID 0x82c /* mips 74k core */
  136. #define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
  137. #define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
  138. #define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
  139. #define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
  140. #define SC_CORE_ID 0x831 /* shared common core */
  141. #define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
  142. #define SPIH_CORE_ID 0x833 /* SPI host core */
  143. #define I2S_CORE_ID 0x834 /* I2S core */
  144. #define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
  145. #define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
  146. #define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
  147. #define DEF_AI_COMP 0xfff /* Default component, in ai chips it
  148. * maps all unused address ranges
  149. */
  150. /* There are TWO constants on all HND chips: SI_ENUM_BASE above,
  151. * and chipcommon being the first core:
  152. */
  153. #define SI_CC_IDX 0
  154. /* SOC Interconnect types (aka chip types) */
  155. #define SOCI_AI 1
  156. /* Common core control flags */
  157. #define SICF_BIST_EN 0x8000
  158. #define SICF_PME_EN 0x4000
  159. #define SICF_CORE_BITS 0x3ffc
  160. #define SICF_FGC 0x0002
  161. #define SICF_CLOCK_EN 0x0001
  162. /* Common core status flags */
  163. #define SISF_BIST_DONE 0x8000
  164. #define SISF_BIST_ERROR 0x4000
  165. #define SISF_GATED_CLK 0x2000
  166. #define SISF_DMA64 0x1000
  167. #define SISF_CORE_BITS 0x0fff
  168. /* A register that is common to all cores to
  169. * communicate w/PMU regarding clock control.
  170. */
  171. #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
  172. /* clk_ctl_st register */
  173. #define CCS_FORCEALP 0x00000001 /* force ALP request */
  174. #define CCS_FORCEHT 0x00000002 /* force HT request */
  175. #define CCS_FORCEILP 0x00000004 /* force ILP request */
  176. #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
  177. #define CCS_HTAREQ 0x00000010 /* HT Avail Request */
  178. #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
  179. #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
  180. #define CCS_ERSRC_REQ_SHIFT 8
  181. #define CCS_ALPAVAIL 0x00010000 /* ALP is available */
  182. #define CCS_HTAVAIL 0x00020000 /* HT is available */
  183. #define CCS_BP_ON_APL 0x00040000 /* RO: running on ALP clock */
  184. #define CCS_BP_ON_HT 0x00080000 /* RO: running on HT clock */
  185. #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
  186. #define CCS_ERSRC_STS_SHIFT 24
  187. /* HT avail in chipc and pcmcia on 4328a0 */
  188. #define CCS0_HTAVAIL 0x00010000
  189. /* ALP avail in chipc and pcmcia on 4328a0 */
  190. #define CCS0_ALPAVAIL 0x00020000
  191. /* Not really related to SOC Interconnect, but a couple of software
  192. * conventions for the use the flash space:
  193. */
  194. /* Minumum amount of flash we support */
  195. #define FLASH_MIN 0x00020000 /* Minimum flash size */
  196. /* A boot/binary may have an embedded block that describes its size */
  197. #define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
  198. #define BISZ_MAGIC 0x4249535a /* Marked with value: 'BISZ' */
  199. #define BISZ_MAGIC_IDX 0 /* Word 0: magic */
  200. #define BISZ_TXTST_IDX 1 /* 1: text start */
  201. #define BISZ_TXTEND_IDX 2 /* 2: text end */
  202. #define BISZ_DATAST_IDX 3 /* 3: data start */
  203. #define BISZ_DATAEND_IDX 4 /* 4: data end */
  204. #define BISZ_BSSST_IDX 5 /* 5: bss start */
  205. #define BISZ_BSSEND_IDX 6 /* 6: bss end */
  206. #define BISZ_SIZE 7 /* descriptor size in 32-bit integers */
  207. #define SI_INFO(sih) (si_info_t *)sih
  208. #define GOODCOREADDR(x, b) \
  209. (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
  210. IS_ALIGNED((x), SI_CORE_SIZE))
  211. #define GOODREGS(regs) \
  212. ((regs) != NULL && IS_ALIGNED((unsigned long)(regs), SI_CORE_SIZE))
  213. #define BADCOREADDR 0
  214. #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
  215. #define NOREV -1 /* Invalid rev */
  216. /* Newer chips can access PCI/PCIE and CC core without requiring to change
  217. * PCI BAR0 WIN
  218. */
  219. #define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
  220. (((si)->pub.buscoretype == PCI_CORE_ID) && \
  221. (si)->pub.buscorerev >= 13))
  222. #define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
  223. #define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
  224. /*
  225. * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
  226. * before after core switching to avoid invalid register accesss inside ISR.
  227. */
  228. #define INTR_OFF(si, intr_val) \
  229. if ((si)->intrsoff_fn && \
  230. (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
  231. intr_val = (*(si)->intrsoff_fn)((si)->intr_arg)
  232. #define INTR_RESTORE(si, intr_val) \
  233. if ((si)->intrsrestore_fn && \
  234. (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
  235. (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val)
  236. /* dynamic clock control defines */
  237. #define LPOMINFREQ 25000 /* low power oscillator min */
  238. #define LPOMAXFREQ 43000 /* low power oscillator max */
  239. #define XTALMINFREQ 19800000 /* 20 MHz - 1% */
  240. #define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
  241. #define PCIMINFREQ 25000000 /* 25 MHz */
  242. #define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
  243. #define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
  244. #define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
  245. #define PCI(si) (((si)->pub.bustype == PCI_BUS) && \
  246. ((si)->pub.buscoretype == PCI_CORE_ID))
  247. #define PCIE(si) (((si)->pub.bustype == PCI_BUS) && \
  248. ((si)->pub.buscoretype == PCIE_CORE_ID))
  249. #define PCI_FORCEHT(si) \
  250. (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
  251. /* GPIO Based LED powersave defines */
  252. #define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
  253. #define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
  254. #ifndef DEFAULT_GPIOTIMERVAL
  255. #define DEFAULT_GPIOTIMERVAL \
  256. ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
  257. #endif
  258. /*
  259. * Data structure to export all chip specific common variables
  260. * public (read-only) portion of aiutils handle returned by si_attach()
  261. */
  262. struct si_pub {
  263. uint bustype; /* SI_BUS, PCI_BUS */
  264. uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
  265. uint buscorerev; /* buscore rev */
  266. uint buscoreidx; /* buscore index */
  267. int ccrev; /* chip common core rev */
  268. u32 cccaps; /* chip common capabilities */
  269. u32 cccaps_ext; /* chip common capabilities extension */
  270. int pmurev; /* pmu core rev */
  271. u32 pmucaps; /* pmu capabilities */
  272. uint boardtype; /* board type */
  273. uint boardvendor; /* board vendor */
  274. uint boardflags; /* board flags */
  275. uint boardflags2; /* board flags2 */
  276. uint chip; /* chip number */
  277. uint chiprev; /* chip revision */
  278. uint chippkg; /* chip package option */
  279. u32 chipst; /* chip status */
  280. bool issim; /* chip is in simulation or emulation */
  281. uint socirev; /* SOC interconnect rev */
  282. bool pci_pr32414;
  283. };
  284. /*
  285. * for HIGH_ONLY driver, the si_t must be writable to allow states sync from
  286. * BMAC to HIGH driver for monolithic driver, it is readonly to prevent accident
  287. * change
  288. */
  289. typedef const struct si_pub si_t;
  290. /*
  291. * Many of the routines below take an 'sih' handle as their first arg.
  292. * Allocate this by calling si_attach(). Free it by calling si_detach().
  293. * At any one time, the sih is logically focused on one particular si core
  294. * (the "current core").
  295. * Use si_setcore() or si_setcoreidx() to change the association to another core
  296. */
  297. #define BADIDX (SI_MAXCORES + 1)
  298. /* clkctl xtal what flags */
  299. #define XTAL 0x1 /* primary crystal oscillator (2050) */
  300. #define PLL 0x2 /* main chip pll */
  301. /* clkctl clk mode */
  302. #define CLK_FAST 0 /* force fast (pll) clock */
  303. #define CLK_DYNAMIC 2 /* enable dynamic clock control */
  304. /* GPIO usage priorities */
  305. #define GPIO_DRV_PRIORITY 0 /* Driver */
  306. #define GPIO_APP_PRIORITY 1 /* Application */
  307. #define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO
  308. * reservation
  309. */
  310. /* GPIO pull up/down */
  311. #define GPIO_PULLUP 0
  312. #define GPIO_PULLDN 1
  313. /* GPIO event regtype */
  314. #define GPIO_REGEVT 0 /* GPIO register event */
  315. #define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
  316. #define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
  317. /* device path */
  318. #define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
  319. /* SI routine enumeration: to be used by update function with multiple hooks */
  320. #define SI_DOATTACH 1
  321. #define SI_PCIDOWN 2
  322. #define SI_PCIUP 3
  323. #define ISSIM_ENAB(sih) 0
  324. /* PMU clock/power control */
  325. #if defined(BCMPMUCTL)
  326. #define PMUCTL_ENAB(sih) (BCMPMUCTL)
  327. #else
  328. #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
  329. #endif
  330. /* chipcommon clock/power control (exclusive with PMU's) */
  331. #if defined(BCMPMUCTL) && BCMPMUCTL
  332. #define CCCTL_ENAB(sih) (0)
  333. #define CCPLL_ENAB(sih) (0)
  334. #else
  335. #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
  336. #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
  337. #endif
  338. typedef void (*gpio_handler_t) (u32 stat, void *arg);
  339. /* External PA enable mask */
  340. #define GPIO_CTRL_EPA_EN_MASK 0x40
  341. #define SI_ERROR(args)
  342. #ifdef BCMDBG
  343. #define SI_MSG(args) printk args
  344. #else
  345. #define SI_MSG(args)
  346. #endif /* BCMDBG */
  347. /* Define SI_VMSG to printf for verbose debugging, but don't check it in */
  348. #define SI_VMSG(args)
  349. #define IS_SIM(chippkg) \
  350. ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
  351. typedef u32(*si_intrsoff_t) (void *intr_arg);
  352. typedef void (*si_intrsrestore_t) (void *intr_arg, u32 arg);
  353. typedef bool(*si_intrsenabled_t) (void *intr_arg);
  354. typedef struct gpioh_item {
  355. void *arg;
  356. bool level;
  357. gpio_handler_t handler;
  358. u32 event;
  359. struct gpioh_item *next;
  360. } gpioh_item_t;
  361. /* misc si info needed by some of the routines */
  362. typedef struct si_info {
  363. struct si_pub pub; /* back plane public state (must be first) */
  364. void *pbus; /* handle to bus (pci/sdio/..) */
  365. uint dev_coreid; /* the core provides driver functions */
  366. void *intr_arg; /* interrupt callback function arg */
  367. si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
  368. si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
  369. si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
  370. void *pch; /* PCI/E core handle */
  371. gpioh_item_t *gpioh_head; /* GPIO event handlers list */
  372. bool memseg; /* flag to toggle MEM_SEG register */
  373. char *vars;
  374. uint varsz;
  375. void *curmap; /* current regs va */
  376. void *regs[SI_MAXCORES]; /* other regs va */
  377. uint curidx; /* current core index */
  378. uint numcores; /* # discovered cores */
  379. uint coreid[SI_MAXCORES]; /* id of each core */
  380. u32 coresba[SI_MAXCORES]; /* backplane address of each core */
  381. void *regs2[SI_MAXCORES]; /* 2nd virtual address per core (usbh20) */
  382. u32 coresba2[SI_MAXCORES]; /* 2nd phys address per core (usbh20) */
  383. u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
  384. u32 coresba2_size[SI_MAXCORES]; /* second address space size */
  385. void *curwrap; /* current wrapper va */
  386. void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
  387. u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
  388. u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
  389. u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
  390. u32 oob_router; /* oob router registers for axi */
  391. } si_info_t;
  392. /* AMBA Interconnect exported externs */
  393. extern void ai_scan(si_t *sih, void *regs, uint devid);
  394. extern uint ai_flag(si_t *sih);
  395. extern void ai_setint(si_t *sih, int siflag);
  396. extern uint ai_coreidx(si_t *sih);
  397. extern uint ai_corevendor(si_t *sih);
  398. extern uint ai_corerev(si_t *sih);
  399. extern bool ai_iscoreup(si_t *sih);
  400. extern void *ai_setcoreidx(si_t *sih, uint coreidx);
  401. extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
  402. extern void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val);
  403. extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
  404. extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
  405. uint val);
  406. extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
  407. extern void ai_core_disable(si_t *sih, u32 bits);
  408. extern int ai_numaddrspaces(si_t *sih);
  409. extern u32 ai_addrspace(si_t *sih, uint asidx);
  410. extern u32 ai_addrspacesize(si_t *sih, uint asidx);
  411. extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);
  412. /* === exported functions === */
  413. extern si_t *ai_attach(uint pcidev, void *regs, uint bustype,
  414. void *sdh, char **vars, uint *varsz);
  415. extern void ai_detach(si_t *sih);
  416. extern bool ai_pci_war16165(si_t *sih);
  417. extern uint ai_coreid(si_t *sih);
  418. extern uint ai_corerev(si_t *sih);
  419. extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
  420. uint val);
  421. extern void ai_write_wrapperreg(si_t *sih, u32 offset, u32 val);
  422. extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
  423. extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
  424. extern bool ai_iscoreup(si_t *sih);
  425. extern uint ai_findcoreidx(si_t *sih, uint coreid, uint coreunit);
  426. extern void *ai_setcoreidx(si_t *sih, uint coreidx);
  427. extern void *ai_setcore(si_t *sih, uint coreid, uint coreunit);
  428. extern void *ai_switch_core(si_t *sih, uint coreid, uint *origidx,
  429. uint *intr_val);
  430. extern void ai_restore_core(si_t *sih, uint coreid, uint intr_val);
  431. extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
  432. extern void ai_core_disable(si_t *sih, u32 bits);
  433. extern u32 ai_alp_clock(si_t *sih);
  434. extern u32 ai_ilp_clock(si_t *sih);
  435. extern void ai_pci_setup(si_t *sih, uint coremask);
  436. extern void ai_setint(si_t *sih, int siflag);
  437. extern bool ai_backplane64(si_t *sih);
  438. extern void ai_register_intr_callback(si_t *sih, void *intrsoff_fn,
  439. void *intrsrestore_fn,
  440. void *intrsenabled_fn, void *intr_arg);
  441. extern void ai_deregister_intr_callback(si_t *sih);
  442. extern void ai_clkctl_init(si_t *sih);
  443. extern u16 ai_clkctl_fast_pwrup_delay(si_t *sih);
  444. extern bool ai_clkctl_cc(si_t *sih, uint mode);
  445. extern int ai_clkctl_xtal(si_t *sih, uint what, bool on);
  446. extern bool ai_deviceremoved(si_t *sih);
  447. extern u32 ai_gpiocontrol(si_t *sih, u32 mask, u32 val,
  448. u8 priority);
  449. /* OTP status */
  450. extern bool ai_is_otp_disabled(si_t *sih);
  451. extern bool ai_is_otp_powered(si_t *sih);
  452. extern void ai_otp_power(si_t *sih, bool on);
  453. /* SPROM availability */
  454. extern bool ai_is_sprom_available(si_t *sih);
  455. /*
  456. * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
  457. * The returned path is NULL terminated and has trailing '/'.
  458. * Return 0 on success, nonzero otherwise.
  459. */
  460. extern int ai_devpath(si_t *sih, char *path, int size);
  461. /* Read variable with prepending the devpath to the name */
  462. extern char *ai_getdevpathvar(si_t *sih, const char *name);
  463. extern int ai_getdevpathintvar(si_t *sih, const char *name);
  464. extern void ai_pci_sleep(si_t *sih);
  465. extern void ai_pci_down(si_t *sih);
  466. extern void ai_pci_up(si_t *sih);
  467. extern int ai_pci_fixcfg(si_t *sih);
  468. extern void ai_chipcontrl_epa4331(si_t *sih, bool on);
  469. /* Enable Ex-PA for 4313 */
  470. extern void ai_epa_4313war(si_t *sih);
  471. char *ai_getnvramflvar(si_t *sih, const char *name);
  472. #endif /* _aiutils_h_ */