/drivers/staging/brcm80211/brcmsmac/aiutils.h
C Header | 546 lines | 353 code | 74 blank | 119 comment | 23 complexity | 0d7a2542f118f94bfd83722a6cd963ce MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/*
2 * Copyright (c) 2011 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _aiutils_h_
18#define _aiutils_h_
19
20/* cpp contortions to concatenate w/arg prescan */
21#ifndef PAD
22#define _PADLINE(line) pad ## line
23#define _XSTR(line) _PADLINE(line)
24#define PAD _XSTR(__LINE__)
25#endif
26
27/* Include the soci specific files */
28#include <aidmp.h>
29
30/*
31 * SOC Interconnect Address Map.
32 * All regions may not exist on all chips.
33 */
34/* Physical SDRAM */
35#define SI_SDRAM_BASE 0x00000000
36/* Host Mode sb2pcitranslation0 (64 MB) */
37#define SI_PCI_MEM 0x08000000
38#define SI_PCI_MEM_SZ (64 * 1024 * 1024)
39/* Host Mode sb2pcitranslation1 (64 MB) */
40#define SI_PCI_CFG 0x0c000000
41/* Byteswapped Physical SDRAM */
42#define SI_SDRAM_SWAPPED 0x10000000
43/* Region 2 for sdram (512 MB) */
44#define SI_SDRAM_R2 0x80000000
45
46#ifdef SI_ENUM_BASE_VARIABLE
47#define SI_ENUM_BASE (sii->pub.si_enum_base)
48#else
49#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
50#endif /* SI_ENUM_BASE_VARIABLE */
51
52/* Wrapper space base */
53#define SI_WRAP_BASE 0x18100000
54/* each core gets 4Kbytes for registers */
55#define SI_CORE_SIZE 0x1000
56/*
57 * Max cores (this is arbitrary, for software
58 * convenience and could be changed if we
59 * make any larger chips
60 */
61#define SI_MAXCORES 16
62
63/* On-chip RAM on chips that also have DDR */
64#define SI_FASTRAM 0x19000000
65#define SI_FASTRAM_SWAPPED 0x19800000
66
67/* Flash Region 2 (region 1 shadowed here) */
68#define SI_FLASH2 0x1c000000
69/* Size of Flash Region 2 */
70#define SI_FLASH2_SZ 0x02000000
71/* ARM Cortex-M3 ROM */
72#define SI_ARMCM3_ROM 0x1e000000
73/* MIPS Flash Region 1 */
74#define SI_FLASH1 0x1fc00000
75/* MIPS Size of Flash Region 1 */
76#define SI_FLASH1_SZ 0x00400000
77/* ARM7TDMI-S ROM */
78#define SI_ARM7S_ROM 0x20000000
79/* ARM Cortex-M3 SRAM Region 2 */
80#define SI_ARMCM3_SRAM2 0x60000000
81/* ARM7TDMI-S SRAM Region 2 */
82#define SI_ARM7S_SRAM2 0x80000000
83/* ARM Flash Region 1 */
84#define SI_ARM_FLASH1 0xffff0000
85/* ARM Size of Flash Region 1 */
86#define SI_ARM_FLASH1_SZ 0x00010000
87
88/* Client Mode sb2pcitranslation2 (1 GB) */
89#define SI_PCI_DMA 0x40000000
90/* Client Mode sb2pcitranslation2 (1 GB) */
91#define SI_PCI_DMA2 0x80000000
92/* Client Mode sb2pcitranslation2 size in bytes */
93#define SI_PCI_DMA_SZ 0x40000000
94/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
95#define SI_PCIE_DMA_L32 0x00000000
96/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
97#define SI_PCIE_DMA_H32 0x80000000
98
99/* core codes */
100#define NODEV_CORE_ID 0x700 /* Invalid coreid */
101#define CC_CORE_ID 0x800 /* chipcommon core */
102#define ILINE20_CORE_ID 0x801 /* iline20 core */
103#define SRAM_CORE_ID 0x802 /* sram core */
104#define SDRAM_CORE_ID 0x803 /* sdram core */
105#define PCI_CORE_ID 0x804 /* pci core */
106#define MIPS_CORE_ID 0x805 /* mips core */
107#define ENET_CORE_ID 0x806 /* enet mac core */
108#define CODEC_CORE_ID 0x807 /* v90 codec core */
109#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
110#define ADSL_CORE_ID 0x809 /* ADSL core */
111#define ILINE100_CORE_ID 0x80a /* iline100 core */
112#define IPSEC_CORE_ID 0x80b /* ipsec core */
113#define UTOPIA_CORE_ID 0x80c /* utopia core */
114#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
115#define SOCRAM_CORE_ID 0x80e /* internal memory core */
116#define MEMC_CORE_ID 0x80f /* memc sdram core */
117#define OFDM_CORE_ID 0x810 /* OFDM phy core */
118#define EXTIF_CORE_ID 0x811 /* external interface core */
119#define D11_CORE_ID 0x812 /* 802.11 MAC core */
120#define APHY_CORE_ID 0x813 /* 802.11a phy core */
121#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
122#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
123#define MIPS33_CORE_ID 0x816 /* mips3302 core */
124#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
125#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
126#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
127#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
128#define SDIOH_CORE_ID 0x81b /* sdio host core */
129#define ROBO_CORE_ID 0x81c /* roboswitch core */
130#define ATA100_CORE_ID 0x81d /* parallel ATA core */
131#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
132#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
133#define PCIE_CORE_ID 0x820 /* pci express core */
134#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
135#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
136#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
137#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
138#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
139#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
140#define PMU_CORE_ID 0x827 /* PMU core */
141#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
142#define SDIOD_CORE_ID 0x829 /* SDIO device core */
143#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
144#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
145#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
146#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
147#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
148#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
149#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
150#define SC_CORE_ID 0x831 /* shared common core */
151#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
152#define SPIH_CORE_ID 0x833 /* SPI host core */
153#define I2S_CORE_ID 0x834 /* I2S core */
154#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
155#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
156#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
157#define DEF_AI_COMP 0xfff /* Default component, in ai chips it
158 * maps all unused address ranges
159 */
160
161/* There are TWO constants on all HND chips: SI_ENUM_BASE above,
162 * and chipcommon being the first core:
163 */
164#define SI_CC_IDX 0
165
166/* SOC Interconnect types (aka chip types) */
167#define SOCI_AI 1
168
169/* Common core control flags */
170#define SICF_BIST_EN 0x8000
171#define SICF_PME_EN 0x4000
172#define SICF_CORE_BITS 0x3ffc
173#define SICF_FGC 0x0002
174#define SICF_CLOCK_EN 0x0001
175
176/* Common core status flags */
177#define SISF_BIST_DONE 0x8000
178#define SISF_BIST_ERROR 0x4000
179#define SISF_GATED_CLK 0x2000
180#define SISF_DMA64 0x1000
181#define SISF_CORE_BITS 0x0fff
182
183/* A register that is common to all cores to
184 * communicate w/PMU regarding clock control.
185 */
186#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
187
188/* clk_ctl_st register */
189#define CCS_FORCEALP 0x00000001 /* force ALP request */
190#define CCS_FORCEHT 0x00000002 /* force HT request */
191#define CCS_FORCEILP 0x00000004 /* force ILP request */
192#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
193#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
194#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
195#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
196#define CCS_ERSRC_REQ_SHIFT 8
197#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
198#define CCS_HTAVAIL 0x00020000 /* HT is available */
199#define CCS_BP_ON_APL 0x00040000 /* RO: running on ALP clock */
200#define CCS_BP_ON_HT 0x00080000 /* RO: running on HT clock */
201#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
202#define CCS_ERSRC_STS_SHIFT 24
203
204/* HT avail in chipc and pcmcia on 4328a0 */
205#define CCS0_HTAVAIL 0x00010000
206/* ALP avail in chipc and pcmcia on 4328a0 */
207#define CCS0_ALPAVAIL 0x00020000
208
209/* Not really related to SOC Interconnect, but a couple of software
210 * conventions for the use the flash space:
211 */
212
213/* Minumum amount of flash we support */
214#define FLASH_MIN 0x00020000 /* Minimum flash size */
215
216/* A boot/binary may have an embedded block that describes its size */
217#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
218#define BISZ_MAGIC 0x4249535a /* Marked with value: 'BISZ' */
219#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
220#define BISZ_TXTST_IDX 1 /* 1: text start */
221#define BISZ_TXTEND_IDX 2 /* 2: text end */
222#define BISZ_DATAST_IDX 3 /* 3: data start */
223#define BISZ_DATAEND_IDX 4 /* 4: data end */
224#define BISZ_BSSST_IDX 5 /* 5: bss start */
225#define BISZ_BSSEND_IDX 6 /* 6: bss end */
226#define BISZ_SIZE 7 /* descriptor size in 32-bit integers */
227
228#define SI_INFO(sih) (si_info_t *)sih
229
230#define GOODCOREADDR(x, b) \
231 (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
232 IS_ALIGNED((x), SI_CORE_SIZE))
233#define GOODREGS(regs) \
234 ((regs) != NULL && IS_ALIGNED((unsigned long)(regs), SI_CORE_SIZE))
235#define BADCOREADDR 0
236#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
237#define NOREV -1 /* Invalid rev */
238
239/* Newer chips can access PCI/PCIE and CC core without requiring to change
240 * PCI BAR0 WIN
241 */
242#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
243 (((si)->pub.buscoretype == PCI_CORE_ID) && \
244 (si)->pub.buscorerev >= 13))
245
246#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
247#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
248
249/*
250 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
251 * before after core switching to avoid invalid register accesss inside ISR.
252 */
253#define INTR_OFF(si, intr_val) \
254 if ((si)->intrsoff_fn && \
255 (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
256 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg)
257#define INTR_RESTORE(si, intr_val) \
258 if ((si)->intrsrestore_fn && \
259 (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
260 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val)
261
262/* dynamic clock control defines */
263#define LPOMINFREQ 25000 /* low power oscillator min */
264#define LPOMAXFREQ 43000 /* low power oscillator max */
265#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
266#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
267#define PCIMINFREQ 25000000 /* 25 MHz */
268#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
269
270#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
271#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
272
273#define PCI(si) (((si)->pub.bustype == PCI_BUS) && \
274 ((si)->pub.buscoretype == PCI_CORE_ID))
275#define PCIE(si) (((si)->pub.bustype == PCI_BUS) && \
276 ((si)->pub.buscoretype == PCIE_CORE_ID))
277#define PCI_FORCEHT(si) \
278 (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
279
280/* GPIO Based LED powersave defines */
281#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
282#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
283
284#ifndef DEFAULT_GPIOTIMERVAL
285#define DEFAULT_GPIOTIMERVAL \
286 ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
287#endif
288
289/*
290 * Data structure to export all chip specific common variables
291 * public (read-only) portion of aiutils handle returned by si_attach()
292 */
293struct si_pub {
294 uint bustype; /* SI_BUS, PCI_BUS */
295 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
296 uint buscorerev; /* buscore rev */
297 uint buscoreidx; /* buscore index */
298 int ccrev; /* chip common core rev */
299 u32 cccaps; /* chip common capabilities */
300 u32 cccaps_ext; /* chip common capabilities extension */
301 int pmurev; /* pmu core rev */
302 u32 pmucaps; /* pmu capabilities */
303 uint boardtype; /* board type */
304 uint boardvendor; /* board vendor */
305 uint boardflags; /* board flags */
306 uint boardflags2; /* board flags2 */
307 uint chip; /* chip number */
308 uint chiprev; /* chip revision */
309 uint chippkg; /* chip package option */
310 u32 chipst; /* chip status */
311 bool issim; /* chip is in simulation or emulation */
312 uint socirev; /* SOC interconnect rev */
313 bool pci_pr32414;
314
315};
316
317/*
318 * for HIGH_ONLY driver, the si_t must be writable to allow states sync from
319 * BMAC to HIGH driver for monolithic driver, it is readonly to prevent accident
320 * change
321 */
322typedef const struct si_pub si_t;
323
324/*
325 * Many of the routines below take an 'sih' handle as their first arg.
326 * Allocate this by calling si_attach(). Free it by calling si_detach().
327 * At any one time, the sih is logically focused on one particular si core
328 * (the "current core").
329 * Use si_setcore() or si_setcoreidx() to change the association to another core
330 */
331
332#define BADIDX (SI_MAXCORES + 1)
333
334/* clkctl xtal what flags */
335#define XTAL 0x1 /* primary crystal oscillator (2050) */
336#define PLL 0x2 /* main chip pll */
337
338/* clkctl clk mode */
339#define CLK_FAST 0 /* force fast (pll) clock */
340#define CLK_DYNAMIC 2 /* enable dynamic clock control */
341
342/* GPIO usage priorities */
343#define GPIO_DRV_PRIORITY 0 /* Driver */
344#define GPIO_APP_PRIORITY 1 /* Application */
345#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO
346 * reservation
347 */
348
349/* GPIO pull up/down */
350#define GPIO_PULLUP 0
351#define GPIO_PULLDN 1
352
353/* GPIO event regtype */
354#define GPIO_REGEVT 0 /* GPIO register event */
355#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
356#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
357
358/* device path */
359#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
360
361/* SI routine enumeration: to be used by update function with multiple hooks */
362#define SI_DOATTACH 1
363#define SI_PCIDOWN 2
364#define SI_PCIUP 3
365
366#define ISSIM_ENAB(sih) 0
367
368/* PMU clock/power control */
369#if defined(BCMPMUCTL)
370#define PMUCTL_ENAB(sih) (BCMPMUCTL)
371#else
372#define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
373#endif
374
375/* chipcommon clock/power control (exclusive with PMU's) */
376#if defined(BCMPMUCTL) && BCMPMUCTL
377#define CCCTL_ENAB(sih) (0)
378#define CCPLL_ENAB(sih) (0)
379#else
380#define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
381#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
382#endif
383
384typedef void (*gpio_handler_t) (u32 stat, void *arg);
385
386/* External PA enable mask */
387#define GPIO_CTRL_EPA_EN_MASK 0x40
388
389#define SI_ERROR(args)
390
391#ifdef BCMDBG
392#define SI_MSG(args) printk args
393#else
394#define SI_MSG(args)
395#endif /* BCMDBG */
396
397/* Define SI_VMSG to printf for verbose debugging, but don't check it in */
398#define SI_VMSG(args)
399
400#define IS_SIM(chippkg) \
401 ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
402
403typedef u32(*si_intrsoff_t) (void *intr_arg);
404typedef void (*si_intrsrestore_t) (void *intr_arg, u32 arg);
405typedef bool(*si_intrsenabled_t) (void *intr_arg);
406
407typedef struct gpioh_item {
408 void *arg;
409 bool level;
410 gpio_handler_t handler;
411 u32 event;
412 struct gpioh_item *next;
413} gpioh_item_t;
414
415/* misc si info needed by some of the routines */
416typedef struct si_info {
417 struct si_pub pub; /* back plane public state (must be first) */
418 void *pbus; /* handle to bus (pci/sdio/..) */
419 uint dev_coreid; /* the core provides driver functions */
420 void *intr_arg; /* interrupt callback function arg */
421 si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
422 si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
423 si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
424
425 void *pch; /* PCI/E core handle */
426
427 gpioh_item_t *gpioh_head; /* GPIO event handlers list */
428
429 bool memseg; /* flag to toggle MEM_SEG register */
430
431 char *vars;
432 uint varsz;
433
434 void *curmap; /* current regs va */
435 void *regs[SI_MAXCORES]; /* other regs va */
436
437 uint curidx; /* current core index */
438 uint numcores; /* # discovered cores */
439 uint coreid[SI_MAXCORES]; /* id of each core */
440 u32 coresba[SI_MAXCORES]; /* backplane address of each core */
441 void *regs2[SI_MAXCORES]; /* 2nd virtual address per core (usbh20) */
442 u32 coresba2[SI_MAXCORES]; /* 2nd phys address per core (usbh20) */
443 u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
444 u32 coresba2_size[SI_MAXCORES]; /* second address space size */
445
446 void *curwrap; /* current wrapper va */
447 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
448 u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
449
450 u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
451 u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
452 u32 oob_router; /* oob router registers for axi */
453} si_info_t;
454
455/* AMBA Interconnect exported externs */
456extern void ai_scan(si_t *sih, void *regs, uint devid);
457
458extern uint ai_flag(si_t *sih);
459extern void ai_setint(si_t *sih, int siflag);
460extern uint ai_coreidx(si_t *sih);
461extern uint ai_corevendor(si_t *sih);
462extern uint ai_corerev(si_t *sih);
463extern bool ai_iscoreup(si_t *sih);
464extern void *ai_setcoreidx(si_t *sih, uint coreidx);
465extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
466extern void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val);
467extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
468extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
469 uint val);
470extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
471extern void ai_core_disable(si_t *sih, u32 bits);
472extern int ai_numaddrspaces(si_t *sih);
473extern u32 ai_addrspace(si_t *sih, uint asidx);
474extern u32 ai_addrspacesize(si_t *sih, uint asidx);
475extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);
476
477/* === exported functions === */
478extern si_t *ai_attach(uint pcidev, void *regs, uint bustype,
479 void *sdh, char **vars, uint *varsz);
480
481extern void ai_detach(si_t *sih);
482extern bool ai_pci_war16165(si_t *sih);
483
484extern uint ai_coreid(si_t *sih);
485extern uint ai_corerev(si_t *sih);
486extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
487 uint val);
488extern void ai_write_wrapperreg(si_t *sih, u32 offset, u32 val);
489extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
490extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
491extern bool ai_iscoreup(si_t *sih);
492extern uint ai_findcoreidx(si_t *sih, uint coreid, uint coreunit);
493extern void *ai_setcoreidx(si_t *sih, uint coreidx);
494extern void *ai_setcore(si_t *sih, uint coreid, uint coreunit);
495extern void *ai_switch_core(si_t *sih, uint coreid, uint *origidx,
496 uint *intr_val);
497extern void ai_restore_core(si_t *sih, uint coreid, uint intr_val);
498extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
499extern void ai_core_disable(si_t *sih, u32 bits);
500extern u32 ai_alp_clock(si_t *sih);
501extern u32 ai_ilp_clock(si_t *sih);
502extern void ai_pci_setup(si_t *sih, uint coremask);
503extern void ai_setint(si_t *sih, int siflag);
504extern bool ai_backplane64(si_t *sih);
505extern void ai_register_intr_callback(si_t *sih, void *intrsoff_fn,
506 void *intrsrestore_fn,
507 void *intrsenabled_fn, void *intr_arg);
508extern void ai_deregister_intr_callback(si_t *sih);
509extern void ai_clkctl_init(si_t *sih);
510extern u16 ai_clkctl_fast_pwrup_delay(si_t *sih);
511extern bool ai_clkctl_cc(si_t *sih, uint mode);
512extern int ai_clkctl_xtal(si_t *sih, uint what, bool on);
513extern bool ai_deviceremoved(si_t *sih);
514extern u32 ai_gpiocontrol(si_t *sih, u32 mask, u32 val,
515 u8 priority);
516
517/* OTP status */
518extern bool ai_is_otp_disabled(si_t *sih);
519extern bool ai_is_otp_powered(si_t *sih);
520extern void ai_otp_power(si_t *sih, bool on);
521
522/* SPROM availability */
523extern bool ai_is_sprom_available(si_t *sih);
524
525/*
526 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
527 * The returned path is NULL terminated and has trailing '/'.
528 * Return 0 on success, nonzero otherwise.
529 */
530extern int ai_devpath(si_t *sih, char *path, int size);
531/* Read variable with prepending the devpath to the name */
532extern char *ai_getdevpathvar(si_t *sih, const char *name);
533extern int ai_getdevpathintvar(si_t *sih, const char *name);
534
535extern void ai_pci_sleep(si_t *sih);
536extern void ai_pci_down(si_t *sih);
537extern void ai_pci_up(si_t *sih);
538extern int ai_pci_fixcfg(si_t *sih);
539
540extern void ai_chipcontrl_epa4331(si_t *sih, bool on);
541/* Enable Ex-PA for 4313 */
542extern void ai_epa_4313war(si_t *sih);
543
544char *ai_getnvramflvar(si_t *sih, const char *name);
545
546#endif /* _aiutils_h_ */