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/drivers/rtc/rtc-twl.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C | 589 lines | 399 code | 100 blank | 90 comment | 38 complexity | e16e7d5cabfa59b339e3e1b9aa3a1865 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * rtc-twl.c -- TWL Real Time Clock interface
  3. *
  4. * Copyright (C) 2007 MontaVista Software, Inc
  5. * Author: Alexandre Rusev <source@mvista.com>
  6. *
  7. * Based on original TI driver twl4030-rtc.c
  8. * Copyright (C) 2006 Texas Instruments, Inc.
  9. *
  10. * Based on rtc-omap.c
  11. * Copyright (C) 2003 MontaVista Software, Inc.
  12. * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
  13. * Copyright (C) 2006 David Brownell
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License
  17. * as published by the Free Software Foundation; either version
  18. * 2 of the License, or (at your option) any later version.
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/errno.h>
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/types.h>
  25. #include <linux/rtc.h>
  26. #include <linux/bcd.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/i2c/twl.h>
  30. /*
  31. * RTC block register offsets (use TWL_MODULE_RTC)
  32. */
  33. enum {
  34. REG_SECONDS_REG = 0,
  35. REG_MINUTES_REG,
  36. REG_HOURS_REG,
  37. REG_DAYS_REG,
  38. REG_MONTHS_REG,
  39. REG_YEARS_REG,
  40. REG_WEEKS_REG,
  41. REG_ALARM_SECONDS_REG,
  42. REG_ALARM_MINUTES_REG,
  43. REG_ALARM_HOURS_REG,
  44. REG_ALARM_DAYS_REG,
  45. REG_ALARM_MONTHS_REG,
  46. REG_ALARM_YEARS_REG,
  47. REG_RTC_CTRL_REG,
  48. REG_RTC_STATUS_REG,
  49. REG_RTC_INTERRUPTS_REG,
  50. REG_RTC_COMP_LSB_REG,
  51. REG_RTC_COMP_MSB_REG,
  52. };
  53. static const u8 twl4030_rtc_reg_map[] = {
  54. [REG_SECONDS_REG] = 0x00,
  55. [REG_MINUTES_REG] = 0x01,
  56. [REG_HOURS_REG] = 0x02,
  57. [REG_DAYS_REG] = 0x03,
  58. [REG_MONTHS_REG] = 0x04,
  59. [REG_YEARS_REG] = 0x05,
  60. [REG_WEEKS_REG] = 0x06,
  61. [REG_ALARM_SECONDS_REG] = 0x07,
  62. [REG_ALARM_MINUTES_REG] = 0x08,
  63. [REG_ALARM_HOURS_REG] = 0x09,
  64. [REG_ALARM_DAYS_REG] = 0x0A,
  65. [REG_ALARM_MONTHS_REG] = 0x0B,
  66. [REG_ALARM_YEARS_REG] = 0x0C,
  67. [REG_RTC_CTRL_REG] = 0x0D,
  68. [REG_RTC_STATUS_REG] = 0x0E,
  69. [REG_RTC_INTERRUPTS_REG] = 0x0F,
  70. [REG_RTC_COMP_LSB_REG] = 0x10,
  71. [REG_RTC_COMP_MSB_REG] = 0x11,
  72. };
  73. static const u8 twl6030_rtc_reg_map[] = {
  74. [REG_SECONDS_REG] = 0x00,
  75. [REG_MINUTES_REG] = 0x01,
  76. [REG_HOURS_REG] = 0x02,
  77. [REG_DAYS_REG] = 0x03,
  78. [REG_MONTHS_REG] = 0x04,
  79. [REG_YEARS_REG] = 0x05,
  80. [REG_WEEKS_REG] = 0x06,
  81. [REG_ALARM_SECONDS_REG] = 0x08,
  82. [REG_ALARM_MINUTES_REG] = 0x09,
  83. [REG_ALARM_HOURS_REG] = 0x0A,
  84. [REG_ALARM_DAYS_REG] = 0x0B,
  85. [REG_ALARM_MONTHS_REG] = 0x0C,
  86. [REG_ALARM_YEARS_REG] = 0x0D,
  87. [REG_RTC_CTRL_REG] = 0x10,
  88. [REG_RTC_STATUS_REG] = 0x11,
  89. [REG_RTC_INTERRUPTS_REG] = 0x12,
  90. [REG_RTC_COMP_LSB_REG] = 0x13,
  91. [REG_RTC_COMP_MSB_REG] = 0x14,
  92. };
  93. /* RTC_CTRL_REG bitfields */
  94. #define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
  95. #define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
  96. #define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
  97. #define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
  98. #define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
  99. #define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
  100. #define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
  101. /* RTC_STATUS_REG bitfields */
  102. #define BIT_RTC_STATUS_REG_RUN_M 0x02
  103. #define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
  104. #define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
  105. #define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
  106. #define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
  107. #define BIT_RTC_STATUS_REG_ALARM_M 0x40
  108. #define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
  109. /* RTC_INTERRUPTS_REG bitfields */
  110. #define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
  111. #define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
  112. #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
  113. /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
  114. #define ALL_TIME_REGS 6
  115. /*----------------------------------------------------------------------*/
  116. static u8 *rtc_reg_map;
  117. /*
  118. * Supports 1 byte read from TWL RTC register.
  119. */
  120. static int twl_rtc_read_u8(u8 *data, u8 reg)
  121. {
  122. int ret;
  123. ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
  124. if (ret < 0)
  125. pr_err("twl_rtc: Could not read TWL"
  126. "register %X - error %d\n", reg, ret);
  127. return ret;
  128. }
  129. /*
  130. * Supports 1 byte write to TWL RTC registers.
  131. */
  132. static int twl_rtc_write_u8(u8 data, u8 reg)
  133. {
  134. int ret;
  135. ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
  136. if (ret < 0)
  137. pr_err("twl_rtc: Could not write TWL"
  138. "register %X - error %d\n", reg, ret);
  139. return ret;
  140. }
  141. /*
  142. * Cache the value for timer/alarm interrupts register; this is
  143. * only changed by callers holding rtc ops lock (or resume).
  144. */
  145. static unsigned char rtc_irq_bits;
  146. /*
  147. * Enable 1/second update and/or alarm interrupts.
  148. */
  149. static int set_rtc_irq_bit(unsigned char bit)
  150. {
  151. unsigned char val;
  152. int ret;
  153. val = rtc_irq_bits | bit;
  154. val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
  155. ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
  156. if (ret == 0)
  157. rtc_irq_bits = val;
  158. return ret;
  159. }
  160. /*
  161. * Disable update and/or alarm interrupts.
  162. */
  163. static int mask_rtc_irq_bit(unsigned char bit)
  164. {
  165. unsigned char val;
  166. int ret;
  167. val = rtc_irq_bits & ~bit;
  168. ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
  169. if (ret == 0)
  170. rtc_irq_bits = val;
  171. return ret;
  172. }
  173. static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
  174. {
  175. int ret;
  176. if (enabled)
  177. ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
  178. else
  179. ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
  180. return ret;
  181. }
  182. /*
  183. * Gets current TWL RTC time and date parameters.
  184. *
  185. * The RTC's time/alarm representation is not what gmtime(3) requires
  186. * Linux to use:
  187. *
  188. * - Months are 1..12 vs Linux 0-11
  189. * - Years are 0..99 vs Linux 1900..N (we assume 21st century)
  190. */
  191. static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
  192. {
  193. unsigned char rtc_data[ALL_TIME_REGS + 1];
  194. int ret;
  195. u8 save_control;
  196. ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
  197. if (ret < 0)
  198. return ret;
  199. save_control |= BIT_RTC_CTRL_REG_GET_TIME_M;
  200. ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
  201. if (ret < 0)
  202. return ret;
  203. ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
  204. (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
  205. if (ret < 0) {
  206. dev_err(dev, "rtc_read_time error %d\n", ret);
  207. return ret;
  208. }
  209. tm->tm_sec = bcd2bin(rtc_data[0]);
  210. tm->tm_min = bcd2bin(rtc_data[1]);
  211. tm->tm_hour = bcd2bin(rtc_data[2]);
  212. tm->tm_mday = bcd2bin(rtc_data[3]);
  213. tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
  214. tm->tm_year = bcd2bin(rtc_data[5]) + 100;
  215. return ret;
  216. }
  217. static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
  218. {
  219. unsigned char save_control;
  220. unsigned char rtc_data[ALL_TIME_REGS + 1];
  221. int ret;
  222. rtc_data[1] = bin2bcd(tm->tm_sec);
  223. rtc_data[2] = bin2bcd(tm->tm_min);
  224. rtc_data[3] = bin2bcd(tm->tm_hour);
  225. rtc_data[4] = bin2bcd(tm->tm_mday);
  226. rtc_data[5] = bin2bcd(tm->tm_mon + 1);
  227. rtc_data[6] = bin2bcd(tm->tm_year - 100);
  228. /* Stop RTC while updating the TC registers */
  229. ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
  230. if (ret < 0)
  231. goto out;
  232. save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
  233. twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
  234. if (ret < 0)
  235. goto out;
  236. /* update all the time registers in one shot */
  237. ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
  238. (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
  239. if (ret < 0) {
  240. dev_err(dev, "rtc_set_time error %d\n", ret);
  241. goto out;
  242. }
  243. /* Start back RTC */
  244. save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
  245. ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
  246. out:
  247. return ret;
  248. }
  249. /*
  250. * Gets current TWL RTC alarm time.
  251. */
  252. static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
  253. {
  254. unsigned char rtc_data[ALL_TIME_REGS + 1];
  255. int ret;
  256. ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
  257. (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
  258. if (ret < 0) {
  259. dev_err(dev, "rtc_read_alarm error %d\n", ret);
  260. return ret;
  261. }
  262. /* some of these fields may be wildcard/"match all" */
  263. alm->time.tm_sec = bcd2bin(rtc_data[0]);
  264. alm->time.tm_min = bcd2bin(rtc_data[1]);
  265. alm->time.tm_hour = bcd2bin(rtc_data[2]);
  266. alm->time.tm_mday = bcd2bin(rtc_data[3]);
  267. alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
  268. alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
  269. /* report cached alarm enable state */
  270. if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
  271. alm->enabled = 1;
  272. return ret;
  273. }
  274. static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  275. {
  276. unsigned char alarm_data[ALL_TIME_REGS + 1];
  277. int ret;
  278. ret = twl_rtc_alarm_irq_enable(dev, 0);
  279. if (ret)
  280. goto out;
  281. alarm_data[1] = bin2bcd(alm->time.tm_sec);
  282. alarm_data[2] = bin2bcd(alm->time.tm_min);
  283. alarm_data[3] = bin2bcd(alm->time.tm_hour);
  284. alarm_data[4] = bin2bcd(alm->time.tm_mday);
  285. alarm_data[5] = bin2bcd(alm->time.tm_mon + 1);
  286. alarm_data[6] = bin2bcd(alm->time.tm_year - 100);
  287. /* update all the alarm registers in one shot */
  288. ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
  289. (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
  290. if (ret) {
  291. dev_err(dev, "rtc_set_alarm error %d\n", ret);
  292. goto out;
  293. }
  294. if (alm->enabled)
  295. ret = twl_rtc_alarm_irq_enable(dev, 1);
  296. out:
  297. return ret;
  298. }
  299. static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
  300. {
  301. unsigned long events = 0;
  302. int ret = IRQ_NONE;
  303. int res;
  304. u8 rd_reg;
  305. res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
  306. if (res)
  307. goto out;
  308. /*
  309. * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
  310. * only one (ALARM or RTC) interrupt source may be enabled
  311. * at time, we also could check our results
  312. * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
  313. */
  314. if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
  315. events |= RTC_IRQF | RTC_AF;
  316. else
  317. events |= RTC_IRQF | RTC_UF;
  318. res = twl_rtc_write_u8(rd_reg | BIT_RTC_STATUS_REG_ALARM_M,
  319. REG_RTC_STATUS_REG);
  320. if (res)
  321. goto out;
  322. if (twl_class_is_4030()) {
  323. /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
  324. * needs 2 reads to clear the interrupt. One read is done in
  325. * do_twl_pwrirq(). Doing the second read, to clear
  326. * the bit.
  327. *
  328. * FIXME the reason PWR_ISR1 needs an extra read is that
  329. * RTC_IF retriggered until we cleared REG_ALARM_M above.
  330. * But re-reading like this is a bad hack; by doing so we
  331. * risk wrongly clearing status for some other IRQ (losing
  332. * the interrupt). Be smarter about handling RTC_UF ...
  333. */
  334. res = twl_i2c_read_u8(TWL4030_MODULE_INT,
  335. &rd_reg, TWL4030_INT_PWR_ISR1);
  336. if (res)
  337. goto out;
  338. }
  339. /* Notify RTC core on event */
  340. rtc_update_irq(rtc, 1, events);
  341. ret = IRQ_HANDLED;
  342. out:
  343. return ret;
  344. }
  345. static struct rtc_class_ops twl_rtc_ops = {
  346. .read_time = twl_rtc_read_time,
  347. .set_time = twl_rtc_set_time,
  348. .read_alarm = twl_rtc_read_alarm,
  349. .set_alarm = twl_rtc_set_alarm,
  350. .alarm_irq_enable = twl_rtc_alarm_irq_enable,
  351. };
  352. /*----------------------------------------------------------------------*/
  353. static int __devinit twl_rtc_probe(struct platform_device *pdev)
  354. {
  355. struct rtc_device *rtc;
  356. int ret = -EINVAL;
  357. int irq = platform_get_irq(pdev, 0);
  358. u8 rd_reg;
  359. if (irq <= 0)
  360. goto out1;
  361. ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
  362. if (ret < 0)
  363. goto out1;
  364. if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
  365. dev_warn(&pdev->dev, "Power up reset detected.\n");
  366. if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
  367. dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
  368. /* Clear RTC Power up reset and pending alarm interrupts */
  369. ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
  370. if (ret < 0)
  371. goto out1;
  372. if (twl_class_is_6030()) {
  373. twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
  374. REG_INT_MSK_LINE_A);
  375. twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
  376. REG_INT_MSK_STS_A);
  377. }
  378. /* Check RTC module status, Enable if it is off */
  379. ret = twl_rtc_read_u8(&rd_reg, REG_RTC_CTRL_REG);
  380. if (ret < 0)
  381. goto out1;
  382. if (!(rd_reg & BIT_RTC_CTRL_REG_STOP_RTC_M)) {
  383. dev_info(&pdev->dev, "Enabling TWL-RTC.\n");
  384. rd_reg = BIT_RTC_CTRL_REG_STOP_RTC_M;
  385. ret = twl_rtc_write_u8(rd_reg, REG_RTC_CTRL_REG);
  386. if (ret < 0)
  387. goto out1;
  388. }
  389. /* init cached IRQ enable bits */
  390. ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
  391. if (ret < 0)
  392. goto out1;
  393. rtc = rtc_device_register(pdev->name,
  394. &pdev->dev, &twl_rtc_ops, THIS_MODULE);
  395. if (IS_ERR(rtc)) {
  396. ret = PTR_ERR(rtc);
  397. dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
  398. PTR_ERR(rtc));
  399. goto out1;
  400. }
  401. ret = request_threaded_irq(irq, NULL, twl_rtc_interrupt,
  402. IRQF_TRIGGER_RISING,
  403. dev_name(&rtc->dev), rtc);
  404. if (ret < 0) {
  405. dev_err(&pdev->dev, "IRQ is not free.\n");
  406. goto out2;
  407. }
  408. if (enable_irq_wake(irq) < 0)
  409. dev_warn(&pdev->dev, "Cannot enable wakeup for IRQ %d\n", irq);
  410. platform_set_drvdata(pdev, rtc);
  411. return 0;
  412. out2:
  413. rtc_device_unregister(rtc);
  414. out1:
  415. return ret;
  416. }
  417. /*
  418. * Disable all TWL RTC module interrupts.
  419. * Sets status flag to free.
  420. */
  421. static int __devexit twl_rtc_remove(struct platform_device *pdev)
  422. {
  423. /* leave rtc running, but disable irqs */
  424. struct rtc_device *rtc = platform_get_drvdata(pdev);
  425. int irq = platform_get_irq(pdev, 0);
  426. mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
  427. mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
  428. if (twl_class_is_6030()) {
  429. twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
  430. REG_INT_MSK_LINE_A);
  431. twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
  432. REG_INT_MSK_STS_A);
  433. }
  434. free_irq(irq, rtc);
  435. rtc_device_unregister(rtc);
  436. platform_set_drvdata(pdev, NULL);
  437. return 0;
  438. }
  439. static void twl_rtc_shutdown(struct platform_device *pdev)
  440. {
  441. /* mask timer interrupts, but leave alarm interrupts on to enable
  442. power-on when alarm is triggered */
  443. mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
  444. }
  445. #ifdef CONFIG_PM
  446. static unsigned char irqstat;
  447. static int twl_rtc_suspend(struct platform_device *pdev, pm_message_t state)
  448. {
  449. irqstat = rtc_irq_bits;
  450. mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
  451. return 0;
  452. }
  453. static int twl_rtc_resume(struct platform_device *pdev)
  454. {
  455. set_rtc_irq_bit(irqstat);
  456. return 0;
  457. }
  458. #else
  459. #define twl_rtc_suspend NULL
  460. #define twl_rtc_resume NULL
  461. #endif
  462. MODULE_ALIAS("platform:twl_rtc");
  463. static struct platform_driver twl4030rtc_driver = {
  464. .probe = twl_rtc_probe,
  465. .remove = __devexit_p(twl_rtc_remove),
  466. .shutdown = twl_rtc_shutdown,
  467. .suspend = twl_rtc_suspend,
  468. .resume = twl_rtc_resume,
  469. .driver = {
  470. .owner = THIS_MODULE,
  471. .name = "twl_rtc",
  472. },
  473. };
  474. static int __init twl_rtc_init(void)
  475. {
  476. if (twl_class_is_4030())
  477. rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
  478. else
  479. rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
  480. return platform_driver_register(&twl4030rtc_driver);
  481. }
  482. module_init(twl_rtc_init);
  483. static void __exit twl_rtc_exit(void)
  484. {
  485. platform_driver_unregister(&twl4030rtc_driver);
  486. }
  487. module_exit(twl_rtc_exit);
  488. MODULE_AUTHOR("Texas Instruments, MontaVista Software");
  489. MODULE_LICENSE("GPL");