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/drivers/net/cnic.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C | 5454 lines | 4415 code | 972 blank | 67 comment | 632 complexity | 3e06451f8280a2f355f843f82eb02300 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  29. #define BCM_VLAN 1
  30. #endif
  31. #include <net/ip.h>
  32. #include <net/tcp.h>
  33. #include <net/route.h>
  34. #include <net/ipv6.h>
  35. #include <net/ip6_route.h>
  36. #include <net/ip6_checksum.h>
  37. #include <scsi/iscsi_if.h>
  38. #include "cnic_if.h"
  39. #include "bnx2.h"
  40. #include "bnx2x/bnx2x_reg.h"
  41. #include "bnx2x/bnx2x_fw_defs.h"
  42. #include "bnx2x/bnx2x_hsi.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  44. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  45. #include "cnic.h"
  46. #include "cnic_defs.h"
  47. #define DRV_MODULE_NAME "cnic"
  48. static char version[] __devinitdata =
  49. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  50. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  51. "Chen (zongxi@broadcom.com");
  52. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  53. MODULE_LICENSE("GPL");
  54. MODULE_VERSION(CNIC_MODULE_VERSION);
  55. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  56. static LIST_HEAD(cnic_dev_list);
  57. static LIST_HEAD(cnic_udev_list);
  58. static DEFINE_RWLOCK(cnic_dev_lock);
  59. static DEFINE_MUTEX(cnic_lock);
  60. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  61. /* helper function, assuming cnic_lock is held */
  62. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  63. {
  64. return rcu_dereference_protected(cnic_ulp_tbl[type],
  65. lockdep_is_held(&cnic_lock));
  66. }
  67. static int cnic_service_bnx2(void *, void *);
  68. static int cnic_service_bnx2x(void *, void *);
  69. static int cnic_ctl(void *, struct cnic_ctl_info *);
  70. static struct cnic_ops cnic_bnx2_ops = {
  71. .cnic_owner = THIS_MODULE,
  72. .cnic_handler = cnic_service_bnx2,
  73. .cnic_ctl = cnic_ctl,
  74. };
  75. static struct cnic_ops cnic_bnx2x_ops = {
  76. .cnic_owner = THIS_MODULE,
  77. .cnic_handler = cnic_service_bnx2x,
  78. .cnic_ctl = cnic_ctl,
  79. };
  80. static struct workqueue_struct *cnic_wq;
  81. static void cnic_shutdown_rings(struct cnic_dev *);
  82. static void cnic_init_rings(struct cnic_dev *);
  83. static int cnic_cm_set_pg(struct cnic_sock *);
  84. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  85. {
  86. struct cnic_uio_dev *udev = uinfo->priv;
  87. struct cnic_dev *dev;
  88. if (!capable(CAP_NET_ADMIN))
  89. return -EPERM;
  90. if (udev->uio_dev != -1)
  91. return -EBUSY;
  92. rtnl_lock();
  93. dev = udev->dev;
  94. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  95. rtnl_unlock();
  96. return -ENODEV;
  97. }
  98. udev->uio_dev = iminor(inode);
  99. cnic_shutdown_rings(dev);
  100. cnic_init_rings(dev);
  101. rtnl_unlock();
  102. return 0;
  103. }
  104. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  105. {
  106. struct cnic_uio_dev *udev = uinfo->priv;
  107. udev->uio_dev = -1;
  108. return 0;
  109. }
  110. static inline void cnic_hold(struct cnic_dev *dev)
  111. {
  112. atomic_inc(&dev->ref_count);
  113. }
  114. static inline void cnic_put(struct cnic_dev *dev)
  115. {
  116. atomic_dec(&dev->ref_count);
  117. }
  118. static inline void csk_hold(struct cnic_sock *csk)
  119. {
  120. atomic_inc(&csk->ref_count);
  121. }
  122. static inline void csk_put(struct cnic_sock *csk)
  123. {
  124. atomic_dec(&csk->ref_count);
  125. }
  126. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  127. {
  128. struct cnic_dev *cdev;
  129. read_lock(&cnic_dev_lock);
  130. list_for_each_entry(cdev, &cnic_dev_list, list) {
  131. if (netdev == cdev->netdev) {
  132. cnic_hold(cdev);
  133. read_unlock(&cnic_dev_lock);
  134. return cdev;
  135. }
  136. }
  137. read_unlock(&cnic_dev_lock);
  138. return NULL;
  139. }
  140. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  141. {
  142. atomic_inc(&ulp_ops->ref_count);
  143. }
  144. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  145. {
  146. atomic_dec(&ulp_ops->ref_count);
  147. }
  148. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  149. {
  150. struct cnic_local *cp = dev->cnic_priv;
  151. struct cnic_eth_dev *ethdev = cp->ethdev;
  152. struct drv_ctl_info info;
  153. struct drv_ctl_io *io = &info.data.io;
  154. info.cmd = DRV_CTL_CTX_WR_CMD;
  155. io->cid_addr = cid_addr;
  156. io->offset = off;
  157. io->data = val;
  158. ethdev->drv_ctl(dev->netdev, &info);
  159. }
  160. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  161. {
  162. struct cnic_local *cp = dev->cnic_priv;
  163. struct cnic_eth_dev *ethdev = cp->ethdev;
  164. struct drv_ctl_info info;
  165. struct drv_ctl_io *io = &info.data.io;
  166. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  167. io->offset = off;
  168. io->dma_addr = addr;
  169. ethdev->drv_ctl(dev->netdev, &info);
  170. }
  171. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  172. {
  173. struct cnic_local *cp = dev->cnic_priv;
  174. struct cnic_eth_dev *ethdev = cp->ethdev;
  175. struct drv_ctl_info info;
  176. struct drv_ctl_l2_ring *ring = &info.data.ring;
  177. if (start)
  178. info.cmd = DRV_CTL_START_L2_CMD;
  179. else
  180. info.cmd = DRV_CTL_STOP_L2_CMD;
  181. ring->cid = cid;
  182. ring->client_id = cl_id;
  183. ethdev->drv_ctl(dev->netdev, &info);
  184. }
  185. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  186. {
  187. struct cnic_local *cp = dev->cnic_priv;
  188. struct cnic_eth_dev *ethdev = cp->ethdev;
  189. struct drv_ctl_info info;
  190. struct drv_ctl_io *io = &info.data.io;
  191. info.cmd = DRV_CTL_IO_WR_CMD;
  192. io->offset = off;
  193. io->data = val;
  194. ethdev->drv_ctl(dev->netdev, &info);
  195. }
  196. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  197. {
  198. struct cnic_local *cp = dev->cnic_priv;
  199. struct cnic_eth_dev *ethdev = cp->ethdev;
  200. struct drv_ctl_info info;
  201. struct drv_ctl_io *io = &info.data.io;
  202. info.cmd = DRV_CTL_IO_RD_CMD;
  203. io->offset = off;
  204. ethdev->drv_ctl(dev->netdev, &info);
  205. return io->data;
  206. }
  207. static int cnic_in_use(struct cnic_sock *csk)
  208. {
  209. return test_bit(SK_F_INUSE, &csk->flags);
  210. }
  211. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  212. {
  213. struct cnic_local *cp = dev->cnic_priv;
  214. struct cnic_eth_dev *ethdev = cp->ethdev;
  215. struct drv_ctl_info info;
  216. info.cmd = cmd;
  217. info.data.credit.credit_count = count;
  218. ethdev->drv_ctl(dev->netdev, &info);
  219. }
  220. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  221. {
  222. u32 i;
  223. for (i = 0; i < cp->max_cid_space; i++) {
  224. if (cp->ctx_tbl[i].cid == cid) {
  225. *l5_cid = i;
  226. return 0;
  227. }
  228. }
  229. return -EINVAL;
  230. }
  231. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  232. struct cnic_sock *csk)
  233. {
  234. struct iscsi_path path_req;
  235. char *buf = NULL;
  236. u16 len = 0;
  237. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  238. struct cnic_ulp_ops *ulp_ops;
  239. struct cnic_uio_dev *udev = cp->udev;
  240. int rc = 0, retry = 0;
  241. if (!udev || udev->uio_dev == -1)
  242. return -ENODEV;
  243. if (csk) {
  244. len = sizeof(path_req);
  245. buf = (char *) &path_req;
  246. memset(&path_req, 0, len);
  247. msg_type = ISCSI_KEVENT_PATH_REQ;
  248. path_req.handle = (u64) csk->l5_cid;
  249. if (test_bit(SK_F_IPV6, &csk->flags)) {
  250. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  251. sizeof(struct in6_addr));
  252. path_req.ip_addr_len = 16;
  253. } else {
  254. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  255. sizeof(struct in_addr));
  256. path_req.ip_addr_len = 4;
  257. }
  258. path_req.vlan_id = csk->vlan_id;
  259. path_req.pmtu = csk->mtu;
  260. }
  261. while (retry < 3) {
  262. rc = 0;
  263. rcu_read_lock();
  264. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  265. if (ulp_ops)
  266. rc = ulp_ops->iscsi_nl_send_msg(
  267. cp->ulp_handle[CNIC_ULP_ISCSI],
  268. msg_type, buf, len);
  269. rcu_read_unlock();
  270. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  271. break;
  272. msleep(100);
  273. retry++;
  274. }
  275. return 0;
  276. }
  277. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  278. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  279. char *buf, u16 len)
  280. {
  281. int rc = -EINVAL;
  282. switch (msg_type) {
  283. case ISCSI_UEVENT_PATH_UPDATE: {
  284. struct cnic_local *cp;
  285. u32 l5_cid;
  286. struct cnic_sock *csk;
  287. struct iscsi_path *path_resp;
  288. if (len < sizeof(*path_resp))
  289. break;
  290. path_resp = (struct iscsi_path *) buf;
  291. cp = dev->cnic_priv;
  292. l5_cid = (u32) path_resp->handle;
  293. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  294. break;
  295. rcu_read_lock();
  296. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  297. rc = -ENODEV;
  298. rcu_read_unlock();
  299. break;
  300. }
  301. csk = &cp->csk_tbl[l5_cid];
  302. csk_hold(csk);
  303. if (cnic_in_use(csk) &&
  304. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  305. memcpy(csk->ha, path_resp->mac_addr, 6);
  306. if (test_bit(SK_F_IPV6, &csk->flags))
  307. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  308. sizeof(struct in6_addr));
  309. else
  310. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  311. sizeof(struct in_addr));
  312. if (is_valid_ether_addr(csk->ha)) {
  313. cnic_cm_set_pg(csk);
  314. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  315. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  316. cnic_cm_upcall(cp, csk,
  317. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  318. clear_bit(SK_F_CONNECT_START, &csk->flags);
  319. }
  320. }
  321. csk_put(csk);
  322. rcu_read_unlock();
  323. rc = 0;
  324. }
  325. }
  326. return rc;
  327. }
  328. static int cnic_offld_prep(struct cnic_sock *csk)
  329. {
  330. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  331. return 0;
  332. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  333. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  334. return 0;
  335. }
  336. return 1;
  337. }
  338. static int cnic_close_prep(struct cnic_sock *csk)
  339. {
  340. clear_bit(SK_F_CONNECT_START, &csk->flags);
  341. smp_mb__after_clear_bit();
  342. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  343. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  344. msleep(1);
  345. return 1;
  346. }
  347. return 0;
  348. }
  349. static int cnic_abort_prep(struct cnic_sock *csk)
  350. {
  351. clear_bit(SK_F_CONNECT_START, &csk->flags);
  352. smp_mb__after_clear_bit();
  353. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  354. msleep(1);
  355. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  356. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  357. return 1;
  358. }
  359. return 0;
  360. }
  361. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  362. {
  363. struct cnic_dev *dev;
  364. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  365. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  366. return -EINVAL;
  367. }
  368. mutex_lock(&cnic_lock);
  369. if (cnic_ulp_tbl_prot(ulp_type)) {
  370. pr_err("%s: Type %d has already been registered\n",
  371. __func__, ulp_type);
  372. mutex_unlock(&cnic_lock);
  373. return -EBUSY;
  374. }
  375. read_lock(&cnic_dev_lock);
  376. list_for_each_entry(dev, &cnic_dev_list, list) {
  377. struct cnic_local *cp = dev->cnic_priv;
  378. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  379. }
  380. read_unlock(&cnic_dev_lock);
  381. atomic_set(&ulp_ops->ref_count, 0);
  382. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  383. mutex_unlock(&cnic_lock);
  384. /* Prevent race conditions with netdev_event */
  385. rtnl_lock();
  386. list_for_each_entry(dev, &cnic_dev_list, list) {
  387. struct cnic_local *cp = dev->cnic_priv;
  388. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  389. ulp_ops->cnic_init(dev);
  390. }
  391. rtnl_unlock();
  392. return 0;
  393. }
  394. int cnic_unregister_driver(int ulp_type)
  395. {
  396. struct cnic_dev *dev;
  397. struct cnic_ulp_ops *ulp_ops;
  398. int i = 0;
  399. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  400. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  401. return -EINVAL;
  402. }
  403. mutex_lock(&cnic_lock);
  404. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  405. if (!ulp_ops) {
  406. pr_err("%s: Type %d has not been registered\n",
  407. __func__, ulp_type);
  408. goto out_unlock;
  409. }
  410. read_lock(&cnic_dev_lock);
  411. list_for_each_entry(dev, &cnic_dev_list, list) {
  412. struct cnic_local *cp = dev->cnic_priv;
  413. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  414. pr_err("%s: Type %d still has devices registered\n",
  415. __func__, ulp_type);
  416. read_unlock(&cnic_dev_lock);
  417. goto out_unlock;
  418. }
  419. }
  420. read_unlock(&cnic_dev_lock);
  421. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  422. mutex_unlock(&cnic_lock);
  423. synchronize_rcu();
  424. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  425. msleep(100);
  426. i++;
  427. }
  428. if (atomic_read(&ulp_ops->ref_count) != 0)
  429. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  430. return 0;
  431. out_unlock:
  432. mutex_unlock(&cnic_lock);
  433. return -EINVAL;
  434. }
  435. static int cnic_start_hw(struct cnic_dev *);
  436. static void cnic_stop_hw(struct cnic_dev *);
  437. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  438. void *ulp_ctx)
  439. {
  440. struct cnic_local *cp = dev->cnic_priv;
  441. struct cnic_ulp_ops *ulp_ops;
  442. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  443. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  444. return -EINVAL;
  445. }
  446. mutex_lock(&cnic_lock);
  447. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  448. pr_err("%s: Driver with type %d has not been registered\n",
  449. __func__, ulp_type);
  450. mutex_unlock(&cnic_lock);
  451. return -EAGAIN;
  452. }
  453. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  454. pr_err("%s: Type %d has already been registered to this device\n",
  455. __func__, ulp_type);
  456. mutex_unlock(&cnic_lock);
  457. return -EBUSY;
  458. }
  459. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  460. cp->ulp_handle[ulp_type] = ulp_ctx;
  461. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  462. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  463. cnic_hold(dev);
  464. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  465. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  466. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  467. mutex_unlock(&cnic_lock);
  468. return 0;
  469. }
  470. EXPORT_SYMBOL(cnic_register_driver);
  471. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  472. {
  473. struct cnic_local *cp = dev->cnic_priv;
  474. int i = 0;
  475. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  476. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  477. return -EINVAL;
  478. }
  479. mutex_lock(&cnic_lock);
  480. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  481. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  482. cnic_put(dev);
  483. } else {
  484. pr_err("%s: device not registered to this ulp type %d\n",
  485. __func__, ulp_type);
  486. mutex_unlock(&cnic_lock);
  487. return -EINVAL;
  488. }
  489. mutex_unlock(&cnic_lock);
  490. if (ulp_type == CNIC_ULP_ISCSI)
  491. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  492. synchronize_rcu();
  493. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  494. i < 20) {
  495. msleep(100);
  496. i++;
  497. }
  498. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  499. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  500. return 0;
  501. }
  502. EXPORT_SYMBOL(cnic_unregister_driver);
  503. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  504. u32 next)
  505. {
  506. id_tbl->start = start_id;
  507. id_tbl->max = size;
  508. id_tbl->next = next;
  509. spin_lock_init(&id_tbl->lock);
  510. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  511. if (!id_tbl->table)
  512. return -ENOMEM;
  513. return 0;
  514. }
  515. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  516. {
  517. kfree(id_tbl->table);
  518. id_tbl->table = NULL;
  519. }
  520. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  521. {
  522. int ret = -1;
  523. id -= id_tbl->start;
  524. if (id >= id_tbl->max)
  525. return ret;
  526. spin_lock(&id_tbl->lock);
  527. if (!test_bit(id, id_tbl->table)) {
  528. set_bit(id, id_tbl->table);
  529. ret = 0;
  530. }
  531. spin_unlock(&id_tbl->lock);
  532. return ret;
  533. }
  534. /* Returns -1 if not successful */
  535. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  536. {
  537. u32 id;
  538. spin_lock(&id_tbl->lock);
  539. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  540. if (id >= id_tbl->max) {
  541. id = -1;
  542. if (id_tbl->next != 0) {
  543. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  544. if (id >= id_tbl->next)
  545. id = -1;
  546. }
  547. }
  548. if (id < id_tbl->max) {
  549. set_bit(id, id_tbl->table);
  550. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  551. id += id_tbl->start;
  552. }
  553. spin_unlock(&id_tbl->lock);
  554. return id;
  555. }
  556. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  557. {
  558. if (id == -1)
  559. return;
  560. id -= id_tbl->start;
  561. if (id >= id_tbl->max)
  562. return;
  563. clear_bit(id, id_tbl->table);
  564. }
  565. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  566. {
  567. int i;
  568. if (!dma->pg_arr)
  569. return;
  570. for (i = 0; i < dma->num_pages; i++) {
  571. if (dma->pg_arr[i]) {
  572. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  573. dma->pg_arr[i], dma->pg_map_arr[i]);
  574. dma->pg_arr[i] = NULL;
  575. }
  576. }
  577. if (dma->pgtbl) {
  578. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  579. dma->pgtbl, dma->pgtbl_map);
  580. dma->pgtbl = NULL;
  581. }
  582. kfree(dma->pg_arr);
  583. dma->pg_arr = NULL;
  584. dma->num_pages = 0;
  585. }
  586. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  587. {
  588. int i;
  589. __le32 *page_table = (__le32 *) dma->pgtbl;
  590. for (i = 0; i < dma->num_pages; i++) {
  591. /* Each entry needs to be in big endian format. */
  592. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  593. page_table++;
  594. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  595. page_table++;
  596. }
  597. }
  598. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  599. {
  600. int i;
  601. __le32 *page_table = (__le32 *) dma->pgtbl;
  602. for (i = 0; i < dma->num_pages; i++) {
  603. /* Each entry needs to be in little endian format. */
  604. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  605. page_table++;
  606. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  607. page_table++;
  608. }
  609. }
  610. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  611. int pages, int use_pg_tbl)
  612. {
  613. int i, size;
  614. struct cnic_local *cp = dev->cnic_priv;
  615. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  616. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  617. if (dma->pg_arr == NULL)
  618. return -ENOMEM;
  619. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  620. dma->num_pages = pages;
  621. for (i = 0; i < pages; i++) {
  622. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  623. BCM_PAGE_SIZE,
  624. &dma->pg_map_arr[i],
  625. GFP_ATOMIC);
  626. if (dma->pg_arr[i] == NULL)
  627. goto error;
  628. }
  629. if (!use_pg_tbl)
  630. return 0;
  631. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  632. ~(BCM_PAGE_SIZE - 1);
  633. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  634. &dma->pgtbl_map, GFP_ATOMIC);
  635. if (dma->pgtbl == NULL)
  636. goto error;
  637. cp->setup_pgtbl(dev, dma);
  638. return 0;
  639. error:
  640. cnic_free_dma(dev, dma);
  641. return -ENOMEM;
  642. }
  643. static void cnic_free_context(struct cnic_dev *dev)
  644. {
  645. struct cnic_local *cp = dev->cnic_priv;
  646. int i;
  647. for (i = 0; i < cp->ctx_blks; i++) {
  648. if (cp->ctx_arr[i].ctx) {
  649. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  650. cp->ctx_arr[i].ctx,
  651. cp->ctx_arr[i].mapping);
  652. cp->ctx_arr[i].ctx = NULL;
  653. }
  654. }
  655. }
  656. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  657. {
  658. uio_unregister_device(&udev->cnic_uinfo);
  659. if (udev->l2_buf) {
  660. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  661. udev->l2_buf, udev->l2_buf_map);
  662. udev->l2_buf = NULL;
  663. }
  664. if (udev->l2_ring) {
  665. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  666. udev->l2_ring, udev->l2_ring_map);
  667. udev->l2_ring = NULL;
  668. }
  669. pci_dev_put(udev->pdev);
  670. kfree(udev);
  671. }
  672. static void cnic_free_uio(struct cnic_uio_dev *udev)
  673. {
  674. if (!udev)
  675. return;
  676. write_lock(&cnic_dev_lock);
  677. list_del_init(&udev->list);
  678. write_unlock(&cnic_dev_lock);
  679. __cnic_free_uio(udev);
  680. }
  681. static void cnic_free_resc(struct cnic_dev *dev)
  682. {
  683. struct cnic_local *cp = dev->cnic_priv;
  684. struct cnic_uio_dev *udev = cp->udev;
  685. if (udev) {
  686. udev->dev = NULL;
  687. cp->udev = NULL;
  688. }
  689. cnic_free_context(dev);
  690. kfree(cp->ctx_arr);
  691. cp->ctx_arr = NULL;
  692. cp->ctx_blks = 0;
  693. cnic_free_dma(dev, &cp->gbl_buf_info);
  694. cnic_free_dma(dev, &cp->conn_buf_info);
  695. cnic_free_dma(dev, &cp->kwq_info);
  696. cnic_free_dma(dev, &cp->kwq_16_data_info);
  697. cnic_free_dma(dev, &cp->kcq2.dma);
  698. cnic_free_dma(dev, &cp->kcq1.dma);
  699. kfree(cp->iscsi_tbl);
  700. cp->iscsi_tbl = NULL;
  701. kfree(cp->ctx_tbl);
  702. cp->ctx_tbl = NULL;
  703. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  704. cnic_free_id_tbl(&cp->cid_tbl);
  705. }
  706. static int cnic_alloc_context(struct cnic_dev *dev)
  707. {
  708. struct cnic_local *cp = dev->cnic_priv;
  709. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  710. int i, k, arr_size;
  711. cp->ctx_blk_size = BCM_PAGE_SIZE;
  712. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  713. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  714. sizeof(struct cnic_ctx);
  715. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  716. if (cp->ctx_arr == NULL)
  717. return -ENOMEM;
  718. k = 0;
  719. for (i = 0; i < 2; i++) {
  720. u32 j, reg, off, lo, hi;
  721. if (i == 0)
  722. off = BNX2_PG_CTX_MAP;
  723. else
  724. off = BNX2_ISCSI_CTX_MAP;
  725. reg = cnic_reg_rd_ind(dev, off);
  726. lo = reg >> 16;
  727. hi = reg & 0xffff;
  728. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  729. cp->ctx_arr[k].cid = j;
  730. }
  731. cp->ctx_blks = k;
  732. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  733. cp->ctx_blks = 0;
  734. return -ENOMEM;
  735. }
  736. for (i = 0; i < cp->ctx_blks; i++) {
  737. cp->ctx_arr[i].ctx =
  738. dma_alloc_coherent(&dev->pcidev->dev,
  739. BCM_PAGE_SIZE,
  740. &cp->ctx_arr[i].mapping,
  741. GFP_KERNEL);
  742. if (cp->ctx_arr[i].ctx == NULL)
  743. return -ENOMEM;
  744. }
  745. }
  746. return 0;
  747. }
  748. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  749. {
  750. int err, i, is_bnx2 = 0;
  751. struct kcqe **kcq;
  752. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  753. is_bnx2 = 1;
  754. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  755. if (err)
  756. return err;
  757. kcq = (struct kcqe **) info->dma.pg_arr;
  758. info->kcq = kcq;
  759. if (is_bnx2)
  760. return 0;
  761. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  762. struct bnx2x_bd_chain_next *next =
  763. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  764. int j = i + 1;
  765. if (j >= KCQ_PAGE_CNT)
  766. j = 0;
  767. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  768. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  769. }
  770. return 0;
  771. }
  772. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  773. {
  774. struct cnic_local *cp = dev->cnic_priv;
  775. struct cnic_uio_dev *udev;
  776. read_lock(&cnic_dev_lock);
  777. list_for_each_entry(udev, &cnic_udev_list, list) {
  778. if (udev->pdev == dev->pcidev) {
  779. udev->dev = dev;
  780. cp->udev = udev;
  781. read_unlock(&cnic_dev_lock);
  782. return 0;
  783. }
  784. }
  785. read_unlock(&cnic_dev_lock);
  786. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  787. if (!udev)
  788. return -ENOMEM;
  789. udev->uio_dev = -1;
  790. udev->dev = dev;
  791. udev->pdev = dev->pcidev;
  792. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  793. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  794. &udev->l2_ring_map,
  795. GFP_KERNEL | __GFP_COMP);
  796. if (!udev->l2_ring)
  797. goto err_udev;
  798. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  799. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  800. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  801. &udev->l2_buf_map,
  802. GFP_KERNEL | __GFP_COMP);
  803. if (!udev->l2_buf)
  804. goto err_dma;
  805. write_lock(&cnic_dev_lock);
  806. list_add(&udev->list, &cnic_udev_list);
  807. write_unlock(&cnic_dev_lock);
  808. pci_dev_get(udev->pdev);
  809. cp->udev = udev;
  810. return 0;
  811. err_dma:
  812. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  813. udev->l2_ring, udev->l2_ring_map);
  814. err_udev:
  815. kfree(udev);
  816. return -ENOMEM;
  817. }
  818. static int cnic_init_uio(struct cnic_dev *dev)
  819. {
  820. struct cnic_local *cp = dev->cnic_priv;
  821. struct cnic_uio_dev *udev = cp->udev;
  822. struct uio_info *uinfo;
  823. int ret = 0;
  824. if (!udev)
  825. return -ENOMEM;
  826. uinfo = &udev->cnic_uinfo;
  827. uinfo->mem[0].addr = dev->netdev->base_addr;
  828. uinfo->mem[0].internal_addr = dev->regview;
  829. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  830. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  831. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  832. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  833. PAGE_MASK;
  834. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  835. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  836. else
  837. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  838. uinfo->name = "bnx2_cnic";
  839. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  840. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  841. PAGE_MASK;
  842. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  843. uinfo->name = "bnx2x_cnic";
  844. }
  845. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  846. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  847. uinfo->mem[2].size = udev->l2_ring_size;
  848. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  849. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  850. uinfo->mem[3].size = udev->l2_buf_size;
  851. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  852. uinfo->version = CNIC_MODULE_VERSION;
  853. uinfo->irq = UIO_IRQ_CUSTOM;
  854. uinfo->open = cnic_uio_open;
  855. uinfo->release = cnic_uio_close;
  856. if (udev->uio_dev == -1) {
  857. if (!uinfo->priv) {
  858. uinfo->priv = udev;
  859. ret = uio_register_device(&udev->pdev->dev, uinfo);
  860. }
  861. } else {
  862. cnic_init_rings(dev);
  863. }
  864. return ret;
  865. }
  866. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  867. {
  868. struct cnic_local *cp = dev->cnic_priv;
  869. int ret;
  870. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  871. if (ret)
  872. goto error;
  873. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  874. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  875. if (ret)
  876. goto error;
  877. ret = cnic_alloc_context(dev);
  878. if (ret)
  879. goto error;
  880. ret = cnic_alloc_uio_rings(dev, 2);
  881. if (ret)
  882. goto error;
  883. ret = cnic_init_uio(dev);
  884. if (ret)
  885. goto error;
  886. return 0;
  887. error:
  888. cnic_free_resc(dev);
  889. return ret;
  890. }
  891. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  892. {
  893. struct cnic_local *cp = dev->cnic_priv;
  894. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  895. int total_mem, blks, i;
  896. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  897. blks = total_mem / ctx_blk_size;
  898. if (total_mem % ctx_blk_size)
  899. blks++;
  900. if (blks > cp->ethdev->ctx_tbl_len)
  901. return -ENOMEM;
  902. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  903. if (cp->ctx_arr == NULL)
  904. return -ENOMEM;
  905. cp->ctx_blks = blks;
  906. cp->ctx_blk_size = ctx_blk_size;
  907. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  908. cp->ctx_align = 0;
  909. else
  910. cp->ctx_align = ctx_blk_size;
  911. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  912. for (i = 0; i < blks; i++) {
  913. cp->ctx_arr[i].ctx =
  914. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  915. &cp->ctx_arr[i].mapping,
  916. GFP_KERNEL);
  917. if (cp->ctx_arr[i].ctx == NULL)
  918. return -ENOMEM;
  919. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  920. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  921. cnic_free_context(dev);
  922. cp->ctx_blk_size += cp->ctx_align;
  923. i = -1;
  924. continue;
  925. }
  926. }
  927. }
  928. return 0;
  929. }
  930. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  931. {
  932. struct cnic_local *cp = dev->cnic_priv;
  933. struct cnic_eth_dev *ethdev = cp->ethdev;
  934. u32 start_cid = ethdev->starting_cid;
  935. int i, j, n, ret, pages;
  936. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  937. cp->iro_arr = ethdev->iro_arr;
  938. cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
  939. cp->iscsi_start_cid = start_cid;
  940. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  941. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  942. cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
  943. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  944. if (!cp->fcoe_init_cid)
  945. cp->fcoe_init_cid = 0x10;
  946. }
  947. if (start_cid < BNX2X_ISCSI_START_CID) {
  948. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  949. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  950. cp->fcoe_start_cid += delta;
  951. cp->max_cid_space += delta;
  952. }
  953. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  954. GFP_KERNEL);
  955. if (!cp->iscsi_tbl)
  956. goto error;
  957. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  958. cp->max_cid_space, GFP_KERNEL);
  959. if (!cp->ctx_tbl)
  960. goto error;
  961. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  962. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  963. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  964. }
  965. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  966. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  967. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  968. PAGE_SIZE;
  969. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  970. if (ret)
  971. return -ENOMEM;
  972. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  973. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  974. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  975. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  976. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  977. off;
  978. if ((i % n) == (n - 1))
  979. j++;
  980. }
  981. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  982. if (ret)
  983. goto error;
  984. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  985. ret = cnic_alloc_kcq(dev, &cp->kcq2);
  986. if (ret)
  987. goto error;
  988. }
  989. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  990. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  991. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  992. if (ret)
  993. goto error;
  994. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  995. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  996. if (ret)
  997. goto error;
  998. ret = cnic_alloc_bnx2x_context(dev);
  999. if (ret)
  1000. goto error;
  1001. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1002. cp->l2_rx_ring_size = 15;
  1003. ret = cnic_alloc_uio_rings(dev, 4);
  1004. if (ret)
  1005. goto error;
  1006. ret = cnic_init_uio(dev);
  1007. if (ret)
  1008. goto error;
  1009. return 0;
  1010. error:
  1011. cnic_free_resc(dev);
  1012. return -ENOMEM;
  1013. }
  1014. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1015. {
  1016. return cp->max_kwq_idx -
  1017. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1018. }
  1019. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1020. u32 num_wqes)
  1021. {
  1022. struct cnic_local *cp = dev->cnic_priv;
  1023. struct kwqe *prod_qe;
  1024. u16 prod, sw_prod, i;
  1025. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1026. return -EAGAIN; /* bnx2 is down */
  1027. spin_lock_bh(&cp->cnic_ulp_lock);
  1028. if (num_wqes > cnic_kwq_avail(cp) &&
  1029. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1030. spin_unlock_bh(&cp->cnic_ulp_lock);
  1031. return -EAGAIN;
  1032. }
  1033. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1034. prod = cp->kwq_prod_idx;
  1035. sw_prod = prod & MAX_KWQ_IDX;
  1036. for (i = 0; i < num_wqes; i++) {
  1037. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1038. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1039. prod++;
  1040. sw_prod = prod & MAX_KWQ_IDX;
  1041. }
  1042. cp->kwq_prod_idx = prod;
  1043. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1044. spin_unlock_bh(&cp->cnic_ulp_lock);
  1045. return 0;
  1046. }
  1047. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1048. union l5cm_specific_data *l5_data)
  1049. {
  1050. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1051. dma_addr_t map;
  1052. map = ctx->kwqe_data_mapping;
  1053. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1054. l5_data->phy_address.hi = (u64) map >> 32;
  1055. return ctx->kwqe_data;
  1056. }
  1057. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1058. u32 type, union l5cm_specific_data *l5_data)
  1059. {
  1060. struct cnic_local *cp = dev->cnic_priv;
  1061. struct l5cm_spe kwqe;
  1062. struct kwqe_16 *kwq[1];
  1063. u16 type_16;
  1064. int ret;
  1065. kwqe.hdr.conn_and_cmd_data =
  1066. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1067. BNX2X_HW_CID(cp, cid)));
  1068. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1069. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1070. SPE_HDR_FUNCTION_ID;
  1071. kwqe.hdr.type = cpu_to_le16(type_16);
  1072. kwqe.hdr.reserved1 = 0;
  1073. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1074. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1075. kwq[0] = (struct kwqe_16 *) &kwqe;
  1076. spin_lock_bh(&cp->cnic_ulp_lock);
  1077. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1078. spin_unlock_bh(&cp->cnic_ulp_lock);
  1079. if (ret == 1)
  1080. return 0;
  1081. return -EBUSY;
  1082. }
  1083. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1084. struct kcqe *cqes[], u32 num_cqes)
  1085. {
  1086. struct cnic_local *cp = dev->cnic_priv;
  1087. struct cnic_ulp_ops *ulp_ops;
  1088. rcu_read_lock();
  1089. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1090. if (likely(ulp_ops)) {
  1091. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1092. cqes, num_cqes);
  1093. }
  1094. rcu_read_unlock();
  1095. }
  1096. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1097. {
  1098. struct cnic_local *cp = dev->cnic_priv;
  1099. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1100. int hq_bds, pages;
  1101. u32 pfid = cp->pfid;
  1102. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1103. cp->num_ccells = req1->num_ccells_per_conn;
  1104. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1105. cp->num_iscsi_tasks;
  1106. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1107. BNX2X_ISCSI_R2TQE_SIZE;
  1108. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1109. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1110. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1111. cp->num_cqs = req1->num_cqs;
  1112. if (!dev->max_iscsi_conn)
  1113. return 0;
  1114. /* init Tstorm RAM */
  1115. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1116. req1->rq_num_wqes);
  1117. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1118. PAGE_SIZE);
  1119. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1120. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1121. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1122. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1123. req1->num_tasks_per_conn);
  1124. /* init Ustorm RAM */
  1125. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1126. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1127. req1->rq_buffer_size);
  1128. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1129. PAGE_SIZE);
  1130. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1131. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1132. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1133. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1134. req1->num_tasks_per_conn);
  1135. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1136. req1->rq_num_wqes);
  1137. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1138. req1->cq_num_wqes);
  1139. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1140. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1141. /* init Xstorm RAM */
  1142. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1143. PAGE_SIZE);
  1144. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1145. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1146. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1147. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1148. req1->num_tasks_per_conn);
  1149. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1150. hq_bds);
  1151. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1152. req1->num_tasks_per_conn);
  1153. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1154. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1155. /* init Cstorm RAM */
  1156. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1157. PAGE_SIZE);
  1158. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1159. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1160. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1161. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1162. req1->num_tasks_per_conn);
  1163. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1164. req1->cq_num_wqes);
  1165. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1166. hq_bds);
  1167. return 0;
  1168. }
  1169. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1170. {
  1171. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1172. struct cnic_local *cp = dev->cnic_priv;
  1173. u32 pfid = cp->pfid;
  1174. struct iscsi_kcqe kcqe;
  1175. struct kcqe *cqes[1];
  1176. memset(&kcqe, 0, sizeof(kcqe));
  1177. if (!dev->max_iscsi_conn) {
  1178. kcqe.completion_status =
  1179. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1180. goto done;
  1181. }
  1182. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1183. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1184. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1185. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1186. req2->error_bit_map[1]);
  1187. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1188. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1189. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1190. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1191. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1192. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1193. req2->error_bit_map[1]);
  1194. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1195. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1196. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1197. done:
  1198. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1199. cqes[0] = (struct kcqe *) &kcqe;
  1200. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1201. return 0;
  1202. }
  1203. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1204. {
  1205. struct cnic_local *cp = dev->cnic_priv;
  1206. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1207. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1208. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1209. cnic_free_dma(dev, &iscsi->hq_info);
  1210. cnic_free_dma(dev, &iscsi->r2tq_info);
  1211. cnic_free_dma(dev, &iscsi->task_array_info);
  1212. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1213. } else {
  1214. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1215. }
  1216. ctx->cid = 0;
  1217. }
  1218. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1219. {
  1220. u32 cid;
  1221. int ret, pages;
  1222. struct cnic_local *cp = dev->cnic_priv;
  1223. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1224. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1225. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1226. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1227. if (cid == -1) {
  1228. ret = -ENOMEM;
  1229. goto error;
  1230. }
  1231. ctx->cid = cid;
  1232. return 0;
  1233. }
  1234. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1235. if (cid == -1) {
  1236. ret = -ENOMEM;
  1237. goto error;
  1238. }
  1239. ctx->cid = cid;
  1240. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1241. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1242. if (ret)
  1243. goto error;
  1244. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1245. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1246. if (ret)
  1247. goto error;
  1248. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1249. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1250. if (ret)
  1251. goto error;
  1252. return 0;
  1253. error:
  1254. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1255. return ret;
  1256. }
  1257. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1258. struct regpair *ctx_addr)
  1259. {
  1260. struct cnic_local *cp = dev->cnic_priv;
  1261. struct cnic_eth_dev *ethdev = cp->ethdev;
  1262. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1263. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1264. unsigned long align_off = 0;
  1265. dma_addr_t ctx_map;
  1266. void *ctx;
  1267. if (cp->ctx_align) {
  1268. unsigned long mask = cp->ctx_align - 1;
  1269. if (cp->ctx_arr[blk].mapping & mask)
  1270. align_off = cp->ctx_align -
  1271. (cp->ctx_arr[blk].mapping & mask);
  1272. }
  1273. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1274. (off * BNX2X_CONTEXT_MEM_SIZE);
  1275. ctx = cp->ctx_arr[blk].ctx + align_off +
  1276. (off * BNX2X_CONTEXT_MEM_SIZE);
  1277. if (init)
  1278. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1279. ctx_addr->lo = ctx_map & 0xffffffff;
  1280. ctx_addr->hi = (u64) ctx_map >> 32;
  1281. return ctx;
  1282. }
  1283. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1284. u32 num)
  1285. {
  1286. struct cnic_local *cp = dev->cnic_priv;
  1287. struct iscsi_kwqe_conn_offload1 *req1 =
  1288. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1289. struct iscsi_kwqe_conn_offload2 *req2 =
  1290. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1291. struct iscsi_kwqe_conn_offload3 *req3;
  1292. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1293. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1294. u32 cid = ctx->cid;
  1295. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1296. struct iscsi_context *ictx;
  1297. struct regpair context_addr;
  1298. int i, j, n = 2, n_max;
  1299. ctx->ctx_flags = 0;
  1300. if (!req2->num_additional_wqes)
  1301. return -EINVAL;
  1302. n_max = req2->num_additional_wqes + 2;
  1303. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1304. if (ictx == NULL)
  1305. return -ENOMEM;
  1306. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1307. ictx->xstorm_ag_context.hq_prod = 1;
  1308. ictx->xstorm_st_context.iscsi.first_burst_length =
  1309. ISCSI_DEF_FIRST_BURST_LEN;
  1310. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1311. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1312. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1313. req1->sq_page_table_addr_lo;
  1314. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1315. req1->sq_page_table_addr_hi;
  1316. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1317. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1318. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1319. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1320. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1321. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1322. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1323. iscsi->hq_info.pgtbl[0];
  1324. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1325. iscsi->hq_info.pgtbl[1];
  1326. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1327. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1328. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1329. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1330. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1331. iscsi->r2tq_info.pgtbl[0];
  1332. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1333. iscsi->r2tq_info.pgtbl[1];
  1334. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1335. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1336. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1337. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1338. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1339. BNX2X_ISCSI_PBL_NOT_CACHED;
  1340. ictx->xstorm_st_context.iscsi.flags.flags |=
  1341. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1342. ictx->xstorm_st_context.iscsi.flags.flags |=
  1343. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1344. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1345. /* TSTORM requires the base address of RQ DB & not PTE */
  1346. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1347. req2->rq_page_table_addr_lo & PAGE_MASK;
  1348. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1349. req2->rq_page_table_addr_hi;
  1350. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1351. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1352. ictx->tstorm_st_context.tcp.flags2 |=
  1353. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1354. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1355. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1356. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1357. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1358. req2->rq_page_table_addr_lo;
  1359. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1360. req2->rq_page_table_addr_hi;
  1361. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1362. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1363. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1364. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1365. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1366. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1367. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1368. iscsi->r2tq_info.pgtbl[0];
  1369. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1370. iscsi->r2tq_info.pgtbl[1];
  1371. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1372. req1->cq_page_table_addr_lo;
  1373. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1374. req1->cq_page_table_addr_hi;
  1375. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1376. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1377. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1378. ictx->ustorm_st_context.task_pbe_cache_index =
  1379. BNX2X_ISCSI_PBL_NOT_CACHED;
  1380. ictx->ustorm_st_context.task_pdu_cache_index =
  1381. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1382. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1383. if (j == 3) {
  1384. if (n >= n_max)
  1385. break;
  1386. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1387. j = 0;
  1388. }
  1389. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1390. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1391. req3->qp_first_pte[j].hi;
  1392. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1393. req3->qp_first_pte[j].lo;
  1394. }
  1395. ictx->ustorm_st_context.task_pbl_base.lo =
  1396. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1397. ictx->ustorm_st_context.task_pbl_base.hi =
  1398. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1399. ictx->ustorm_st_context.tce_phy_addr.lo =
  1400. iscsi->task_array_info.pgtbl[0];
  1401. ictx->ustorm_st_context.tce_phy_addr.hi =
  1402. iscsi->task_array_info.pgtbl[1];
  1403. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1404. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1405. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1406. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1407. ISCSI_DEF_MAX_BURST_LEN;
  1408. ictx->ustorm_st_context.negotiated_rx |=
  1409. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1410. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1411. ictx->cstorm_st_context.hq_pbl_base.lo =
  1412. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1413. ictx->cstorm_st_context.hq_pbl_base.hi =
  1414. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1415. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1416. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1417. ictx->cstorm_st_context.task_pbl_base.lo =
  1418. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1419. ictx->cstorm_st_context.task_pbl_base.hi =
  1420. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1421. /* CSTORM and USTORM initialization is different, CSTORM requires
  1422. * CQ DB base & not PTE addr */
  1423. ictx->cstorm_st_context.cq_db_base.lo =
  1424. req1->cq_page_table_addr_lo & PAGE_MASK;
  1425. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1426. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1427. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1428. for (i = 0; i < cp->num_cqs; i++) {
  1429. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1430. ISCSI_INITIAL_SN;
  1431. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1432. ISCSI_INITIAL_SN;
  1433. }
  1434. ictx->xstorm_ag_context.cdu_reserved =
  1435. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1436. ISCSI_CONNECTION_TYPE);
  1437. ictx->ustorm_ag_context.cdu_usage =
  1438. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1439. ISCSI_CONNECTION_TYPE);
  1440. return 0;
  1441. }
  1442. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1443. u32 num, int *work)
  1444. {
  1445. struct iscsi_kwqe_conn_offload1 *req1;
  1446. struct iscsi_kwqe_conn_offload2 *req2;
  1447. struct cnic_local *cp = dev->cnic_priv;
  1448. struct cnic_context *ctx;
  1449. struct iscsi_kcqe kcqe;
  1450. struct kcqe *cqes[1];
  1451. u32 l5_cid;
  1452. int ret = 0;
  1453. if (num < 2) {
  1454. *work = num;
  1455. return -EINVAL;
  1456. }
  1457. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1458. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1459. if ((num - 2) < req2->num_additional_wqes) {
  1460. *work = num;
  1461. return -EINVAL;
  1462. }
  1463. *work = 2 + req2->num_additional_wqes;
  1464. l5_cid = req1->iscsi_conn_id;
  1465. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1466. return -EINVAL;
  1467. memset(&kcqe, 0, sizeof(kcqe));
  1468. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1469. kcqe.iscsi_conn_id = l5_cid;
  1470. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1471. ctx = &cp->ctx_tbl[l5_cid];
  1472. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1473. kcqe.completion_status =
  1474. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1475. goto done;
  1476. }
  1477. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1478. atomic_dec(&cp->iscsi_conn);
  1479. goto done;
  1480. }
  1481. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1482. if (ret) {
  1483. atomic_dec(&cp->iscsi_conn);
  1484. ret = 0;
  1485. goto done;
  1486. }
  1487. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1488. if (ret < 0) {
  1489. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1490. atomic_dec(&cp->iscsi_conn);
  1491. goto done;
  1492. }
  1493. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1494. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1495. done:
  1496. cqes[0] = (struct kcqe *) &kcqe;
  1497. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1498. return ret;
  1499. }
  1500. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1501. {
  1502. struct cnic_local *cp = dev->cnic_priv;
  1503. struct iscsi_kwqe_conn_update *req =
  1504. (struct iscsi_kwqe_conn_update *) kwqe;
  1505. void *data;
  1506. union l5cm_specific_data l5_data;
  1507. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1508. int ret;
  1509. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1510. return -EINVAL;
  1511. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1512. if (!data)
  1513. return -ENOMEM;
  1514. memcpy(data, kwqe, sizeof(struct kwqe));
  1515. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1516. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1517. return ret;
  1518. }
  1519. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1520. {
  1521. struct cnic_local *cp = dev->cnic_priv;
  1522. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1523. union l5cm_specific_data l5_data;
  1524. int ret;
  1525. u32 hw_cid;
  1526. init_waitqueue_head(&ctx->waitq);
  1527. ctx->wait_cond = 0;
  1528. memset(&l5_data, 0, sizeof(l5_data));
  1529. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1530. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1531. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1532. if (ret == 0)
  1533. wait_event(ctx->waitq, ctx->wait_cond);
  1534. return ret;
  1535. }
  1536. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1537. {
  1538. struct cnic_local *cp = dev->cnic_priv;
  1539. struct iscsi_kwqe_conn_destroy *req =
  1540. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1541. u32 l5_cid = req->reserved0;
  1542. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1543. int ret = 0;
  1544. struct iscsi_kcqe kcqe;
  1545. struct kcqe *cqes[1];
  1546. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1547. goto skip_cfc_delete;
  1548. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1549. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1550. if (delta > (2 * HZ))
  1551. delta = 0;
  1552. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1553. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1554. goto destroy_reply;
  1555. }
  1556. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1557. skip_cfc_delete:
  1558. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1559. atomic_dec(&cp->iscsi_conn);
  1560. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1561. destroy_reply:
  1562. memset(&kcqe, 0, sizeof(kcqe));
  1563. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1564. kcqe.iscsi_conn_id = l5_cid;
  1565. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1566. kcqe.iscsi_conn_context_id = req->context_id;
  1567. cqes[0] = (struct kcqe *) &kcqe;
  1568. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1569. return ret;
  1570. }
  1571. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1572. struct l4_kwq_connect_req1 *kwqe1,
  1573. struct l4_kwq_connect_req3 *kwqe3,
  1574. struct l5cm_active_conn_buffer *conn_buf)
  1575. {
  1576. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1577. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1578. &conn_buf->xstorm_conn_buffer;
  1579. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1580. &conn_buf->tstorm_conn_buffer;
  1581. struct regpair context_addr;
  1582. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1583. struct in6_addr src_ip, dst_ip;
  1584. int i;
  1585. u32 *addrp;
  1586. addrp = (u32 *) &conn_addr->local_ip_addr;
  1587. for (i = 0; i < 4; i++, addrp++)
  1588. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1589. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1590. for (i = 0; i < 4; i++, addrp+

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