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/drivers/net/wireless/bcm4329/include/sbconfig.h

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C Header | 276 lines | 198 code | 53 blank | 25 comment | 0 complexity | 3cd59490a8279564c19556222c81436a MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * Broadcom SiliconBackplane hardware register definitions.
  3. *
  4. * Copyright (C) 1999-2010, Broadcom Corporation
  5. *
  6. * Unless you and Broadcom execute a separate written software license
  7. * agreement governing use of this software, this software is licensed to you
  8. * under the terms of the GNU General Public License version 2 (the "GPL"),
  9. * available at http://www.broadcom.com/licenses/GPLv2.php, with the
  10. * following added to such license:
  11. *
  12. * As a special exception, the copyright holders of this software give you
  13. * permission to link this software with independent modules, and to copy and
  14. * distribute the resulting executable under terms of your choice, provided that
  15. * you also meet, for each linked independent module, the terms and conditions of
  16. * the license of that module. An independent module is a module which is not
  17. * derived from this software. The special exception does not apply to any
  18. * modifications of the software.
  19. *
  20. * Notwithstanding the above, under no circumstances may you combine this
  21. * software in any way with any other Broadcom software provided under a license
  22. * other than the GPL, without Broadcom's express prior written consent.
  23. *
  24. * $Id: sbconfig.h,v 13.67.30.1 2008/05/07 20:17:27 Exp $
  25. */
  26. #ifndef _SBCONFIG_H
  27. #define _SBCONFIG_H
  28. #ifndef PAD
  29. #define _PADLINE(line) pad ## line
  30. #define _XSTR(line) _PADLINE(line)
  31. #define PAD _XSTR(__LINE__)
  32. #endif
  33. #define SB_BUS_SIZE 0x10000
  34. #define SB_BUS_BASE(b) (SI_ENUM_BASE + (b) * SB_BUS_SIZE)
  35. #define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE)
  36. #define SBCONFIGOFF 0xf00
  37. #define SBCONFIGSIZE 256
  38. #define SBIPSFLAG 0x08
  39. #define SBTPSFLAG 0x18
  40. #define SBTMERRLOGA 0x48
  41. #define SBTMERRLOG 0x50
  42. #define SBADMATCH3 0x60
  43. #define SBADMATCH2 0x68
  44. #define SBADMATCH1 0x70
  45. #define SBIMSTATE 0x90
  46. #define SBINTVEC 0x94
  47. #define SBTMSTATELOW 0x98
  48. #define SBTMSTATEHIGH 0x9c
  49. #define SBBWA0 0xa0
  50. #define SBIMCONFIGLOW 0xa8
  51. #define SBIMCONFIGHIGH 0xac
  52. #define SBADMATCH0 0xb0
  53. #define SBTMCONFIGLOW 0xb8
  54. #define SBTMCONFIGHIGH 0xbc
  55. #define SBBCONFIG 0xc0
  56. #define SBBSTATE 0xc8
  57. #define SBACTCNFG 0xd8
  58. #define SBFLAGST 0xe8
  59. #define SBIDLOW 0xf8
  60. #define SBIDHIGH 0xfc
  61. #define SBIMERRLOGA 0xea8
  62. #define SBIMERRLOG 0xeb0
  63. #define SBTMPORTCONNID0 0xed8
  64. #define SBTMPORTLOCK0 0xef8
  65. #ifndef _LANGUAGE_ASSEMBLY
  66. typedef volatile struct _sbconfig {
  67. uint32 PAD[2];
  68. uint32 sbipsflag;
  69. uint32 PAD[3];
  70. uint32 sbtpsflag;
  71. uint32 PAD[11];
  72. uint32 sbtmerrloga;
  73. uint32 PAD;
  74. uint32 sbtmerrlog;
  75. uint32 PAD[3];
  76. uint32 sbadmatch3;
  77. uint32 PAD;
  78. uint32 sbadmatch2;
  79. uint32 PAD;
  80. uint32 sbadmatch1;
  81. uint32 PAD[7];
  82. uint32 sbimstate;
  83. uint32 sbintvec;
  84. uint32 sbtmstatelow;
  85. uint32 sbtmstatehigh;
  86. uint32 sbbwa0;
  87. uint32 PAD;
  88. uint32 sbimconfiglow;
  89. uint32 sbimconfighigh;
  90. uint32 sbadmatch0;
  91. uint32 PAD;
  92. uint32 sbtmconfiglow;
  93. uint32 sbtmconfighigh;
  94. uint32 sbbconfig;
  95. uint32 PAD;
  96. uint32 sbbstate;
  97. uint32 PAD[3];
  98. uint32 sbactcnfg;
  99. uint32 PAD[3];
  100. uint32 sbflagst;
  101. uint32 PAD[3];
  102. uint32 sbidlow;
  103. uint32 sbidhigh;
  104. } sbconfig_t;
  105. #endif
  106. #define SBIPS_INT1_MASK 0x3f
  107. #define SBIPS_INT1_SHIFT 0
  108. #define SBIPS_INT2_MASK 0x3f00
  109. #define SBIPS_INT2_SHIFT 8
  110. #define SBIPS_INT3_MASK 0x3f0000
  111. #define SBIPS_INT3_SHIFT 16
  112. #define SBIPS_INT4_MASK 0x3f000000
  113. #define SBIPS_INT4_SHIFT 24
  114. #define SBTPS_NUM0_MASK 0x3f
  115. #define SBTPS_F0EN0 0x40
  116. #define SBTMEL_CM 0x00000007
  117. #define SBTMEL_CI 0x0000ff00
  118. #define SBTMEL_EC 0x0f000000
  119. #define SBTMEL_ME 0x80000000
  120. #define SBIM_PC 0xf
  121. #define SBIM_AP_MASK 0x30
  122. #define SBIM_AP_BOTH 0x00
  123. #define SBIM_AP_TS 0x10
  124. #define SBIM_AP_TK 0x20
  125. #define SBIM_AP_RSV 0x30
  126. #define SBIM_IBE 0x20000
  127. #define SBIM_TO 0x40000
  128. #define SBIM_BY 0x01800000
  129. #define SBIM_RJ 0x02000000
  130. #define SBTML_RESET 0x0001
  131. #define SBTML_REJ_MASK 0x0006
  132. #define SBTML_REJ 0x0002
  133. #define SBTML_TMPREJ 0x0004
  134. #define SBTML_SICF_SHIFT 16
  135. #define SBTMH_SERR 0x0001
  136. #define SBTMH_INT 0x0002
  137. #define SBTMH_BUSY 0x0004
  138. #define SBTMH_TO 0x0020
  139. #define SBTMH_SISF_SHIFT 16
  140. #define SBBWA_TAB0_MASK 0xffff
  141. #define SBBWA_TAB1_MASK 0xffff
  142. #define SBBWA_TAB1_SHIFT 16
  143. #define SBIMCL_STO_MASK 0x7
  144. #define SBIMCL_RTO_MASK 0x70
  145. #define SBIMCL_RTO_SHIFT 4
  146. #define SBIMCL_CID_MASK 0xff0000
  147. #define SBIMCL_CID_SHIFT 16
  148. #define SBIMCH_IEM_MASK 0xc
  149. #define SBIMCH_TEM_MASK 0x30
  150. #define SBIMCH_TEM_SHIFT 4
  151. #define SBIMCH_BEM_MASK 0xc0
  152. #define SBIMCH_BEM_SHIFT 6
  153. #define SBAM_TYPE_MASK 0x3
  154. #define SBAM_AD64 0x4
  155. #define SBAM_ADINT0_MASK 0xf8
  156. #define SBAM_ADINT0_SHIFT 3
  157. #define SBAM_ADINT1_MASK 0x1f8
  158. #define SBAM_ADINT1_SHIFT 3
  159. #define SBAM_ADINT2_MASK 0x1f8
  160. #define SBAM_ADINT2_SHIFT 3
  161. #define SBAM_ADEN 0x400
  162. #define SBAM_ADNEG 0x800
  163. #define SBAM_BASE0_MASK 0xffffff00
  164. #define SBAM_BASE0_SHIFT 8
  165. #define SBAM_BASE1_MASK 0xfffff000
  166. #define SBAM_BASE1_SHIFT 12
  167. #define SBAM_BASE2_MASK 0xffff0000
  168. #define SBAM_BASE2_SHIFT 16
  169. #define SBTMCL_CD_MASK 0xff
  170. #define SBTMCL_CO_MASK 0xf800
  171. #define SBTMCL_CO_SHIFT 11
  172. #define SBTMCL_IF_MASK 0xfc0000
  173. #define SBTMCL_IF_SHIFT 18
  174. #define SBTMCL_IM_MASK 0x3000000
  175. #define SBTMCL_IM_SHIFT 24
  176. #define SBTMCH_BM_MASK 0x3
  177. #define SBTMCH_RM_MASK 0x3
  178. #define SBTMCH_RM_SHIFT 2
  179. #define SBTMCH_SM_MASK 0x30
  180. #define SBTMCH_SM_SHIFT 4
  181. #define SBTMCH_EM_MASK 0x300
  182. #define SBTMCH_EM_SHIFT 8
  183. #define SBTMCH_IM_MASK 0xc00
  184. #define SBTMCH_IM_SHIFT 10
  185. #define SBBC_LAT_MASK 0x3
  186. #define SBBC_MAX0_MASK 0xf0000
  187. #define SBBC_MAX0_SHIFT 16
  188. #define SBBC_MAX1_MASK 0xf00000
  189. #define SBBC_MAX1_SHIFT 20
  190. #define SBBS_SRD 0x1
  191. #define SBBS_HRD 0x2
  192. #define SBIDL_CS_MASK 0x3
  193. #define SBIDL_AR_MASK 0x38
  194. #define SBIDL_AR_SHIFT 3
  195. #define SBIDL_SYNCH 0x40
  196. #define SBIDL_INIT 0x80
  197. #define SBIDL_MINLAT_MASK 0xf00
  198. #define SBIDL_MINLAT_SHIFT 8
  199. #define SBIDL_MAXLAT 0xf000
  200. #define SBIDL_MAXLAT_SHIFT 12
  201. #define SBIDL_FIRST 0x10000
  202. #define SBIDL_CW_MASK 0xc0000
  203. #define SBIDL_CW_SHIFT 18
  204. #define SBIDL_TP_MASK 0xf00000
  205. #define SBIDL_TP_SHIFT 20
  206. #define SBIDL_IP_MASK 0xf000000
  207. #define SBIDL_IP_SHIFT 24
  208. #define SBIDL_RV_MASK 0xf0000000
  209. #define SBIDL_RV_SHIFT 28
  210. #define SBIDL_RV_2_2 0x00000000
  211. #define SBIDL_RV_2_3 0x10000000
  212. #define SBIDH_RC_MASK 0x000f
  213. #define SBIDH_RCE_MASK 0x7000
  214. #define SBIDH_RCE_SHIFT 8
  215. #define SBCOREREV(sbidh) \
  216. ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
  217. #define SBIDH_CC_MASK 0x8ff0
  218. #define SBIDH_CC_SHIFT 4
  219. #define SBIDH_VC_MASK 0xffff0000
  220. #define SBIDH_VC_SHIFT 16
  221. #define SB_COMMIT 0xfd8
  222. #define SB_VEND_BCM 0x4243
  223. #endif