/drivers/net/stmmac/dwmac1000_dma.c

  1/*******************************************************************************
  2  This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
  3  DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
  4  developing this code.
  5
  6  This contains the functions to handle the dma.
  7
  8  Copyright (C) 2007-2009  STMicroelectronics Ltd
  9
 10  This program is free software; you can redistribute it and/or modify it
 11  under the terms and conditions of the GNU General Public License,
 12  version 2, as published by the Free Software Foundation.
 13
 14  This program is distributed in the hope it will be useful, but WITHOUT
 15  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 16  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 17  more details.
 18
 19  You should have received a copy of the GNU General Public License along with
 20  this program; if not, write to the Free Software Foundation, Inc.,
 21  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 22
 23  The full GNU General Public License is included in this distribution in
 24  the file called "COPYING".
 25
 26  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 27*******************************************************************************/
 28
 29#include "dwmac1000.h"
 30#include "dwmac_dma.h"
 31
 32static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx,
 33			      u32 dma_rx)
 34{
 35	u32 value = readl(ioaddr + DMA_BUS_MODE);
 36	int limit;
 37
 38	/* DMA SW reset */
 39	value |= DMA_BUS_MODE_SFT_RESET;
 40	writel(value, ioaddr + DMA_BUS_MODE);
 41	limit = 15000;
 42	while (limit--) {
 43		if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
 44			break;
 45	}
 46	if (limit < 0)
 47		return -EBUSY;
 48
 49	value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL |
 50	    ((pbl << DMA_BUS_MODE_PBL_SHIFT) |
 51	     (pbl << DMA_BUS_MODE_RPBL_SHIFT));
 52
 53#ifdef CONFIG_STMMAC_DA
 54	value |= DMA_BUS_MODE_DA;	/* Rx has priority over tx */
 55#endif
 56	writel(value, ioaddr + DMA_BUS_MODE);
 57
 58	/* Mask interrupts by writing to CSR7 */
 59	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
 60
 61	/* The base address of the RX/TX descriptor lists must be written into
 62	 * DMA CSR3 and CSR4, respectively. */
 63	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
 64	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
 65
 66	return 0;
 67}
 68
 69static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,
 70				    int rxmode)
 71{
 72	u32 csr6 = readl(ioaddr + DMA_CONTROL);
 73
 74	if (txmode == SF_DMA_MODE) {
 75		CHIP_DBG(KERN_DEBUG "GMAC: enable TX store and forward mode\n");
 76		/* Transmit COE type 2 cannot be done in cut-through mode. */
 77		csr6 |= DMA_CONTROL_TSF;
 78		/* Operating on second frame increase the performance
 79		 * especially when transmit store-and-forward is used.*/
 80		csr6 |= DMA_CONTROL_OSF;
 81	} else {
 82		CHIP_DBG(KERN_DEBUG "GMAC: disabling TX store and forward mode"
 83			      " (threshold = %d)\n", txmode);
 84		csr6 &= ~DMA_CONTROL_TSF;
 85		csr6 &= DMA_CONTROL_TC_TX_MASK;
 86		/* Set the transmit threshold */
 87		if (txmode <= 32)
 88			csr6 |= DMA_CONTROL_TTC_32;
 89		else if (txmode <= 64)
 90			csr6 |= DMA_CONTROL_TTC_64;
 91		else if (txmode <= 128)
 92			csr6 |= DMA_CONTROL_TTC_128;
 93		else if (txmode <= 192)
 94			csr6 |= DMA_CONTROL_TTC_192;
 95		else
 96			csr6 |= DMA_CONTROL_TTC_256;
 97	}
 98
 99	if (rxmode == SF_DMA_MODE) {
100		CHIP_DBG(KERN_DEBUG "GMAC: enable RX store and forward mode\n");
101		csr6 |= DMA_CONTROL_RSF;
102	} else {
103		CHIP_DBG(KERN_DEBUG "GMAC: disabling RX store and forward mode"
104			      " (threshold = %d)\n", rxmode);
105		csr6 &= ~DMA_CONTROL_RSF;
106		csr6 &= DMA_CONTROL_TC_RX_MASK;
107		if (rxmode <= 32)
108			csr6 |= DMA_CONTROL_RTC_32;
109		else if (rxmode <= 64)
110			csr6 |= DMA_CONTROL_RTC_64;
111		else if (rxmode <= 96)
112			csr6 |= DMA_CONTROL_RTC_96;
113		else
114			csr6 |= DMA_CONTROL_RTC_128;
115	}
116
117	writel(csr6, ioaddr + DMA_CONTROL);
118}
119
120/* Not yet implemented --- no RMON module */
121static void dwmac1000_dma_diagnostic_fr(void *data,
122		  struct stmmac_extra_stats *x, void __iomem *ioaddr)
123{
124	return;
125}
126
127static void dwmac1000_dump_dma_regs(void __iomem *ioaddr)
128{
129	int i;
130	pr_info(" DMA registers\n");
131	for (i = 0; i < 22; i++) {
132		if ((i < 9) || (i > 17)) {
133			int offset = i * 4;
134			pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
135			       (DMA_BUS_MODE + offset),
136			       readl(ioaddr + DMA_BUS_MODE + offset));
137		}
138	}
139}
140
141const struct stmmac_dma_ops dwmac1000_dma_ops = {
142	.init = dwmac1000_dma_init,
143	.dump_regs = dwmac1000_dump_dma_regs,
144	.dma_mode = dwmac1000_dma_operation_mode,
145	.dma_diagnostic_fr = dwmac1000_dma_diagnostic_fr,
146	.enable_dma_transmission = dwmac_enable_dma_transmission,
147	.enable_dma_irq = dwmac_enable_dma_irq,
148	.disable_dma_irq = dwmac_disable_dma_irq,
149	.start_tx = dwmac_dma_start_tx,
150	.stop_tx = dwmac_dma_stop_tx,
151	.start_rx = dwmac_dma_start_rx,
152	.stop_rx = dwmac_dma_stop_rx,
153	.dma_interrupt = dwmac_dma_interrupt,
154};