/drivers/net/ixgbevf/defines.h
C Header | 297 lines | 221 code | 31 blank | 45 comment | 0 complexity | ec8ac0983d90cac619aa4212dba777eb MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBEVF_DEFINES_H_
29#define _IXGBEVF_DEFINES_H_
30
31/* Device IDs */
32#define IXGBE_DEV_ID_82599_VF 0x10ED
33#define IXGBE_DEV_ID_X540_VF 0x1515
34
35#define IXGBE_VF_IRQ_CLEAR_MASK 7
36#define IXGBE_VF_MAX_TX_QUEUES 1
37#define IXGBE_VF_MAX_RX_QUEUES 1
38#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
39
40/* Link speed */
41typedef u32 ixgbe_link_speed;
42#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
43#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
44
45#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
46#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
47#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
48#define IXGBE_LINKS_UP 0x40000000
49#define IXGBE_LINKS_SPEED_82599 0x30000000
50#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
51#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
52
53/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
54#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
55#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
56#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
57
58/* Interrupt Vector Allocation Registers */
59#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
60
61#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
62
63/* Receive Config masks */
64#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
65#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
66#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
67#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
68#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */
69#define IXGBE_RXDCTL_RLPML_EN 0x00008000
70
71/* DCA Control */
72#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
73
74/* PSRTYPE bit definitions */
75#define IXGBE_PSRTYPE_TCPHDR 0x00000010
76#define IXGBE_PSRTYPE_UDPHDR 0x00000020
77#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
78#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
79#define IXGBE_PSRTYPE_L2HDR 0x00001000
80
81/* SRRCTL bit definitions */
82#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
83#define IXGBE_SRRCTL_RDMTS_SHIFT 22
84#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
85#define IXGBE_SRRCTL_DROP_EN 0x10000000
86#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
87#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
88#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
89#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
90#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
91#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
92#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
93#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
94
95/* Receive Descriptor bit definitions */
96#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
97#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
98#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
99#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
100#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
101#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
102#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
103#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
104#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
105#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
106#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
107#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
108#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
109#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
110#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
111#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
112#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
113#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
114#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
115#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
116#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
117#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
118#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
119#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
120#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
121#define IXGBE_RXDADV_ERR_MASK 0xFFF00000 /* RDESC.ERRORS mask */
122#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
123#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
124#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
125#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
126#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
127#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
128#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
129#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
130#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
131#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
132#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
133#define IXGBE_RXD_PRI_SHIFT 13
134#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
135#define IXGBE_RXD_CFI_SHIFT 12
136
137#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
138#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
139#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
140#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
141#define IXGBE_RXDADV_STAT_MASK 0x000FFFFF /* Stat/NEXTP: bit 0-19 */
142#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
143#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
144#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
145#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
146#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
147#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
148
149#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
150#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
151#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
152#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
153#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
154#define IXGBE_RXDADV_RSCCNT_SHIFT 17
155#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
156#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
157#define IXGBE_RXDADV_SPH 0x8000
158
159#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
160 IXGBE_RXD_ERR_CE | \
161 IXGBE_RXD_ERR_LE | \
162 IXGBE_RXD_ERR_PE | \
163 IXGBE_RXD_ERR_OSE | \
164 IXGBE_RXD_ERR_USE)
165
166#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
167 IXGBE_RXDADV_ERR_CE | \
168 IXGBE_RXDADV_ERR_LE | \
169 IXGBE_RXDADV_ERR_PE | \
170 IXGBE_RXDADV_ERR_OSE | \
171 IXGBE_RXDADV_ERR_USE)
172
173#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
174#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
175#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
176#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
177#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
178#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
179#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
180#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
181#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
182
183/* Transmit Descriptor - Advanced */
184union ixgbe_adv_tx_desc {
185 struct {
186 __le64 buffer_addr; /* Address of descriptor's data buf */
187 __le32 cmd_type_len;
188 __le32 olinfo_status;
189 } read;
190 struct {
191 __le64 rsvd; /* Reserved */
192 __le32 nxtseq_seed;
193 __le32 status;
194 } wb;
195};
196
197/* Receive Descriptor - Advanced */
198union ixgbe_adv_rx_desc {
199 struct {
200 __le64 pkt_addr; /* Packet buffer address */
201 __le64 hdr_addr; /* Header buffer address */
202 } read;
203 struct {
204 struct {
205 union {
206 __le32 data;
207 struct {
208 __le16 pkt_info; /* RSS, Pkt type */
209 __le16 hdr_info; /* Splithdr, hdrlen */
210 } hs_rss;
211 } lo_dword;
212 union {
213 __le32 rss; /* RSS Hash */
214 struct {
215 __le16 ip_id; /* IP id */
216 __le16 csum; /* Packet Checksum */
217 } csum_ip;
218 } hi_dword;
219 } lower;
220 struct {
221 __le32 status_error; /* ext status/error */
222 __le16 length; /* Packet length */
223 __le16 vlan; /* VLAN tag */
224 } upper;
225 } wb; /* writeback */
226};
227
228/* Context descriptors */
229struct ixgbe_adv_tx_context_desc {
230 __le32 vlan_macip_lens;
231 __le32 seqnum_seed;
232 __le32 type_tucmd_mlhl;
233 __le32 mss_l4len_idx;
234};
235
236/* Adv Transmit Descriptor Config Masks */
237#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
238#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
239#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
240#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
241#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
242#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
243#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
244#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
245#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
246#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
247#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
248#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
249#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
250#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
251#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
252#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
253#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
254#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
255 IXGBE_ADVTXD_POPTS_SHIFT)
256#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
257 IXGBE_ADVTXD_POPTS_SHIFT)
258#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
259#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
260#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
261#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
262#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
263
264/* Interrupt register bitmasks */
265
266/* Extended Interrupt Cause Read */
267#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
268#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
269#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
270
271/* Extended Interrupt Cause Set */
272#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
273#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
274#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
275
276/* Extended Interrupt Mask Set */
277#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
278#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
279#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
280
281/* Extended Interrupt Mask Clear */
282#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
283#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
284#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
285
286#define IXGBE_EIMS_ENABLE_MASK ( \
287 IXGBE_EIMS_RTX_QUEUE | \
288 IXGBE_EIMS_MAILBOX | \
289 IXGBE_EIMS_OTHER)
290
291#define IXGBE_EITR_CNT_WDIS 0x80000000
292
293/* Error Codes */
294#define IXGBE_ERR_INVALID_MAC_ADDR -1
295#define IXGBE_ERR_RESET_FAILED -2
296
297#endif /* _IXGBEVF_DEFINES_H_ */