/drivers/net/ixgb/ixgb_hw.c
C | 1260 lines | 686 code | 183 blank | 391 comment | 84 complexity | d4f563f87787675a4d9d8b78f42177f1 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/*******************************************************************************
2
3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* ixgb_hw.c
30 * Shared functions for accessing and configuring the adapter
31 */
32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35#include "ixgb_hw.h"
36#include "ixgb_ids.h"
37
38#include <linux/etherdevice.h>
39
40/* Local function prototypes */
41
42static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
43
44static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
45
46static void ixgb_get_bus_info(struct ixgb_hw *hw);
47
48static bool ixgb_link_reset(struct ixgb_hw *hw);
49
50static void ixgb_optics_reset(struct ixgb_hw *hw);
51
52static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
53
54static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
55
56static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
57
58static void ixgb_clear_vfta(struct ixgb_hw *hw);
59
60static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
61
62static u16 ixgb_read_phy_reg(struct ixgb_hw *hw,
63 u32 reg_address,
64 u32 phy_address,
65 u32 device_type);
66
67static bool ixgb_setup_fc(struct ixgb_hw *hw);
68
69static bool mac_addr_valid(u8 *mac_addr);
70
71static u32 ixgb_mac_reset(struct ixgb_hw *hw)
72{
73 u32 ctrl_reg;
74
75 ctrl_reg = IXGB_CTRL0_RST |
76 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
77 IXGB_CTRL0_SDP2_DIR |
78 IXGB_CTRL0_SDP1_DIR |
79 IXGB_CTRL0_SDP0_DIR |
80 IXGB_CTRL0_SDP3 | /* Initial value 1101 */
81 IXGB_CTRL0_SDP2 |
82 IXGB_CTRL0_SDP0;
83
84#ifdef HP_ZX1
85 /* Workaround for 82597EX reset errata */
86 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
87#else
88 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
89#endif
90
91 /* Delay a few ms just to allow the reset to complete */
92 msleep(IXGB_DELAY_AFTER_RESET);
93 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
94#ifdef DBG
95 /* Make sure the self-clearing global reset bit did self clear */
96 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
97#endif
98
99 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID) {
100 ctrl_reg = /* Enable interrupt from XFP and SerDes */
101 IXGB_CTRL1_GPI0_EN |
102 IXGB_CTRL1_SDP6_DIR |
103 IXGB_CTRL1_SDP7_DIR |
104 IXGB_CTRL1_SDP6 |
105 IXGB_CTRL1_SDP7;
106 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
107 ixgb_optics_reset_bcm(hw);
108 }
109
110 if (hw->phy_type == ixgb_phy_type_txn17401)
111 ixgb_optics_reset(hw);
112
113 return ctrl_reg;
114}
115
116/******************************************************************************
117 * Reset the transmit and receive units; mask and clear all interrupts.
118 *
119 * hw - Struct containing variables accessed by shared code
120 *****************************************************************************/
121bool
122ixgb_adapter_stop(struct ixgb_hw *hw)
123{
124 u32 ctrl_reg;
125 u32 icr_reg;
126
127 ENTER();
128
129 /* If we are stopped or resetting exit gracefully and wait to be
130 * started again before accessing the hardware.
131 */
132 if (hw->adapter_stopped) {
133 pr_debug("Exiting because the adapter is already stopped!!!\n");
134 return false;
135 }
136
137 /* Set the Adapter Stopped flag so other driver functions stop
138 * touching the Hardware.
139 */
140 hw->adapter_stopped = true;
141
142 /* Clear interrupt mask to stop board from generating interrupts */
143 pr_debug("Masking off all interrupts\n");
144 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
145
146 /* Disable the Transmit and Receive units. Then delay to allow
147 * any pending transactions to complete before we hit the MAC with
148 * the global reset.
149 */
150 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
151 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
152 msleep(IXGB_DELAY_BEFORE_RESET);
153
154 /* Issue a global reset to the MAC. This will reset the chip's
155 * transmit, receive, DMA, and link units. It will not effect
156 * the current PCI configuration. The global reset bit is self-
157 * clearing, and should clear within a microsecond.
158 */
159 pr_debug("Issuing a global reset to MAC\n");
160
161 ctrl_reg = ixgb_mac_reset(hw);
162
163 /* Clear interrupt mask to stop board from generating interrupts */
164 pr_debug("Masking off all interrupts\n");
165 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
166
167 /* Clear any pending interrupt events. */
168 icr_reg = IXGB_READ_REG(hw, ICR);
169
170 return ctrl_reg & IXGB_CTRL0_RST;
171}
172
173
174/******************************************************************************
175 * Identifies the vendor of the optics module on the adapter. The SR adapters
176 * support two different types of XPAK optics, so it is necessary to determine
177 * which optics are present before applying any optics-specific workarounds.
178 *
179 * hw - Struct containing variables accessed by shared code.
180 *
181 * Returns: the vendor of the XPAK optics module.
182 *****************************************************************************/
183static ixgb_xpak_vendor
184ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
185{
186 u32 i;
187 u16 vendor_name[5];
188 ixgb_xpak_vendor xpak_vendor;
189
190 ENTER();
191
192 /* Read the first few bytes of the vendor string from the XPAK NVR
193 * registers. These are standard XENPAK/XPAK registers, so all XPAK
194 * devices should implement them. */
195 for (i = 0; i < 5; i++) {
196 vendor_name[i] = ixgb_read_phy_reg(hw,
197 MDIO_PMA_PMD_XPAK_VENDOR_NAME
198 + i, IXGB_PHY_ADDRESS,
199 MDIO_MMD_PMAPMD);
200 }
201
202 /* Determine the actual vendor */
203 if (vendor_name[0] == 'I' &&
204 vendor_name[1] == 'N' &&
205 vendor_name[2] == 'T' &&
206 vendor_name[3] == 'E' && vendor_name[4] == 'L') {
207 xpak_vendor = ixgb_xpak_vendor_intel;
208 } else {
209 xpak_vendor = ixgb_xpak_vendor_infineon;
210 }
211
212 return xpak_vendor;
213}
214
215/******************************************************************************
216 * Determine the physical layer module on the adapter.
217 *
218 * hw - Struct containing variables accessed by shared code. The device_id
219 * field must be (correctly) populated before calling this routine.
220 *
221 * Returns: the phy type of the adapter.
222 *****************************************************************************/
223static ixgb_phy_type
224ixgb_identify_phy(struct ixgb_hw *hw)
225{
226 ixgb_phy_type phy_type;
227 ixgb_xpak_vendor xpak_vendor;
228
229 ENTER();
230
231 /* Infer the transceiver/phy type from the device id */
232 switch (hw->device_id) {
233 case IXGB_DEVICE_ID_82597EX:
234 pr_debug("Identified TXN17401 optics\n");
235 phy_type = ixgb_phy_type_txn17401;
236 break;
237
238 case IXGB_DEVICE_ID_82597EX_SR:
239 /* The SR adapters carry two different types of XPAK optics
240 * modules; read the vendor identifier to determine the exact
241 * type of optics. */
242 xpak_vendor = ixgb_identify_xpak_vendor(hw);
243 if (xpak_vendor == ixgb_xpak_vendor_intel) {
244 pr_debug("Identified TXN17201 optics\n");
245 phy_type = ixgb_phy_type_txn17201;
246 } else {
247 pr_debug("Identified G6005 optics\n");
248 phy_type = ixgb_phy_type_g6005;
249 }
250 break;
251 case IXGB_DEVICE_ID_82597EX_LR:
252 pr_debug("Identified G6104 optics\n");
253 phy_type = ixgb_phy_type_g6104;
254 break;
255 case IXGB_DEVICE_ID_82597EX_CX4:
256 pr_debug("Identified CX4\n");
257 xpak_vendor = ixgb_identify_xpak_vendor(hw);
258 if (xpak_vendor == ixgb_xpak_vendor_intel) {
259 pr_debug("Identified TXN17201 optics\n");
260 phy_type = ixgb_phy_type_txn17201;
261 } else {
262 pr_debug("Identified G6005 optics\n");
263 phy_type = ixgb_phy_type_g6005;
264 }
265 break;
266 default:
267 pr_debug("Unknown physical layer module\n");
268 phy_type = ixgb_phy_type_unknown;
269 break;
270 }
271
272 /* update phy type for sun specific board */
273 if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID)
274 phy_type = ixgb_phy_type_bcm;
275
276 return phy_type;
277}
278
279/******************************************************************************
280 * Performs basic configuration of the adapter.
281 *
282 * hw - Struct containing variables accessed by shared code
283 *
284 * Resets the controller.
285 * Reads and validates the EEPROM.
286 * Initializes the receive address registers.
287 * Initializes the multicast table.
288 * Clears all on-chip counters.
289 * Calls routine to setup flow control settings.
290 * Leaves the transmit and receive units disabled and uninitialized.
291 *
292 * Returns:
293 * true if successful,
294 * false if unrecoverable problems were encountered.
295 *****************************************************************************/
296bool
297ixgb_init_hw(struct ixgb_hw *hw)
298{
299 u32 i;
300 u32 ctrl_reg;
301 bool status;
302
303 ENTER();
304
305 /* Issue a global reset to the MAC. This will reset the chip's
306 * transmit, receive, DMA, and link units. It will not effect
307 * the current PCI configuration. The global reset bit is self-
308 * clearing, and should clear within a microsecond.
309 */
310 pr_debug("Issuing a global reset to MAC\n");
311
312 ctrl_reg = ixgb_mac_reset(hw);
313
314 pr_debug("Issuing an EE reset to MAC\n");
315#ifdef HP_ZX1
316 /* Workaround for 82597EX reset errata */
317 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
318#else
319 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
320#endif
321
322 /* Delay a few ms just to allow the reset to complete */
323 msleep(IXGB_DELAY_AFTER_EE_RESET);
324
325 if (!ixgb_get_eeprom_data(hw))
326 return false;
327
328 /* Use the device id to determine the type of phy/transceiver. */
329 hw->device_id = ixgb_get_ee_device_id(hw);
330 hw->phy_type = ixgb_identify_phy(hw);
331
332 /* Setup the receive addresses.
333 * Receive Address Registers (RARs 0 - 15).
334 */
335 ixgb_init_rx_addrs(hw);
336
337 /*
338 * Check that a valid MAC address has been set.
339 * If it is not valid, we fail hardware init.
340 */
341 if (!mac_addr_valid(hw->curr_mac_addr)) {
342 pr_debug("MAC address invalid after ixgb_init_rx_addrs\n");
343 return(false);
344 }
345
346 /* tell the routines in this file they can access hardware again */
347 hw->adapter_stopped = false;
348
349 /* Fill in the bus_info structure */
350 ixgb_get_bus_info(hw);
351
352 /* Zero out the Multicast HASH table */
353 pr_debug("Zeroing the MTA\n");
354 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
355 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
356
357 /* Zero out the VLAN Filter Table Array */
358 ixgb_clear_vfta(hw);
359
360 /* Zero all of the hardware counters */
361 ixgb_clear_hw_cntrs(hw);
362
363 /* Call a subroutine to setup flow control. */
364 status = ixgb_setup_fc(hw);
365
366 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
367 ixgb_check_for_link(hw);
368
369 return status;
370}
371
372/******************************************************************************
373 * Initializes receive address filters.
374 *
375 * hw - Struct containing variables accessed by shared code
376 *
377 * Places the MAC address in receive address register 0 and clears the rest
378 * of the receive address registers. Clears the multicast table. Assumes
379 * the receiver is in reset when the routine is called.
380 *****************************************************************************/
381static void
382ixgb_init_rx_addrs(struct ixgb_hw *hw)
383{
384 u32 i;
385
386 ENTER();
387
388 /*
389 * If the current mac address is valid, assume it is a software override
390 * to the permanent address.
391 * Otherwise, use the permanent address from the eeprom.
392 */
393 if (!mac_addr_valid(hw->curr_mac_addr)) {
394
395 /* Get the MAC address from the eeprom for later reference */
396 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
397
398 pr_debug("Keeping Permanent MAC Addr = %pM\n",
399 hw->curr_mac_addr);
400 } else {
401
402 /* Setup the receive address. */
403 pr_debug("Overriding MAC Address in RAR[0]\n");
404 pr_debug("New MAC Addr = %pM\n", hw->curr_mac_addr);
405
406 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
407 }
408
409 /* Zero out the other 15 receive addresses. */
410 pr_debug("Clearing RAR[1-15]\n");
411 for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
412 /* Write high reg first to disable the AV bit first */
413 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
414 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
415 }
416}
417
418/******************************************************************************
419 * Updates the MAC's list of multicast addresses.
420 *
421 * hw - Struct containing variables accessed by shared code
422 * mc_addr_list - the list of new multicast addresses
423 * mc_addr_count - number of addresses
424 * pad - number of bytes between addresses in the list
425 *
426 * The given list replaces any existing list. Clears the last 15 receive
427 * address registers and the multicast table. Uses receive address registers
428 * for the first 15 multicast addresses, and hashes the rest into the
429 * multicast table.
430 *****************************************************************************/
431void
432ixgb_mc_addr_list_update(struct ixgb_hw *hw,
433 u8 *mc_addr_list,
434 u32 mc_addr_count,
435 u32 pad)
436{
437 u32 hash_value;
438 u32 i;
439 u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */
440 u8 *mca;
441
442 ENTER();
443
444 /* Set the new number of MC addresses that we are being requested to use. */
445 hw->num_mc_addrs = mc_addr_count;
446
447 /* Clear RAR[1-15] */
448 pr_debug("Clearing RAR[1-15]\n");
449 for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
450 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
451 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
452 }
453
454 /* Clear the MTA */
455 pr_debug("Clearing MTA\n");
456 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
457 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
458
459 /* Add the new addresses */
460 mca = mc_addr_list;
461 for (i = 0; i < mc_addr_count; i++) {
462 pr_debug("Adding the multicast addresses:\n");
463 pr_debug("MC Addr #%d = %pM\n", i, mca);
464
465 /* Place this multicast address in the RAR if there is room, *
466 * else put it in the MTA
467 */
468 if (rar_used_count < IXGB_RAR_ENTRIES) {
469 ixgb_rar_set(hw, mca, rar_used_count);
470 pr_debug("Added a multicast address to RAR[%d]\n", i);
471 rar_used_count++;
472 } else {
473 hash_value = ixgb_hash_mc_addr(hw, mca);
474
475 pr_debug("Hash value = 0x%03X\n", hash_value);
476
477 ixgb_mta_set(hw, hash_value);
478 }
479
480 mca += IXGB_ETH_LENGTH_OF_ADDRESS + pad;
481 }
482
483 pr_debug("MC Update Complete\n");
484}
485
486/******************************************************************************
487 * Hashes an address to determine its location in the multicast table
488 *
489 * hw - Struct containing variables accessed by shared code
490 * mc_addr - the multicast address to hash
491 *
492 * Returns:
493 * The hash value
494 *****************************************************************************/
495static u32
496ixgb_hash_mc_addr(struct ixgb_hw *hw,
497 u8 *mc_addr)
498{
499 u32 hash_value = 0;
500
501 ENTER();
502
503 /* The portion of the address that is used for the hash table is
504 * determined by the mc_filter_type setting.
505 */
506 switch (hw->mc_filter_type) {
507 /* [0] [1] [2] [3] [4] [5]
508 * 01 AA 00 12 34 56
509 * LSB MSB - According to H/W docs */
510 case 0:
511 /* [47:36] i.e. 0x563 for above example address */
512 hash_value =
513 ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
514 break;
515 case 1: /* [46:35] i.e. 0xAC6 for above example address */
516 hash_value =
517 ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
518 break;
519 case 2: /* [45:34] i.e. 0x5D8 for above example address */
520 hash_value =
521 ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
522 break;
523 case 3: /* [43:32] i.e. 0x634 for above example address */
524 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
525 break;
526 default:
527 /* Invalid mc_filter_type, what should we do? */
528 pr_debug("MC filter type param set incorrectly\n");
529 ASSERT(0);
530 break;
531 }
532
533 hash_value &= 0xFFF;
534 return hash_value;
535}
536
537/******************************************************************************
538 * Sets the bit in the multicast table corresponding to the hash value.
539 *
540 * hw - Struct containing variables accessed by shared code
541 * hash_value - Multicast address hash value
542 *****************************************************************************/
543static void
544ixgb_mta_set(struct ixgb_hw *hw,
545 u32 hash_value)
546{
547 u32 hash_bit, hash_reg;
548 u32 mta_reg;
549
550 /* The MTA is a register array of 128 32-bit registers.
551 * It is treated like an array of 4096 bits. We want to set
552 * bit BitArray[hash_value]. So we figure out what register
553 * the bit is in, read it, OR in the new bit, then write
554 * back the new value. The register is determined by the
555 * upper 7 bits of the hash value and the bit within that
556 * register are determined by the lower 5 bits of the value.
557 */
558 hash_reg = (hash_value >> 5) & 0x7F;
559 hash_bit = hash_value & 0x1F;
560
561 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
562
563 mta_reg |= (1 << hash_bit);
564
565 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
566}
567
568/******************************************************************************
569 * Puts an ethernet address into a receive address register.
570 *
571 * hw - Struct containing variables accessed by shared code
572 * addr - Address to put into receive address register
573 * index - Receive address register to write
574 *****************************************************************************/
575void
576ixgb_rar_set(struct ixgb_hw *hw,
577 u8 *addr,
578 u32 index)
579{
580 u32 rar_low, rar_high;
581
582 ENTER();
583
584 /* HW expects these in little endian so we reverse the byte order
585 * from network order (big endian) to little endian
586 */
587 rar_low = ((u32) addr[0] |
588 ((u32)addr[1] << 8) |
589 ((u32)addr[2] << 16) |
590 ((u32)addr[3] << 24));
591
592 rar_high = ((u32) addr[4] |
593 ((u32)addr[5] << 8) |
594 IXGB_RAH_AV);
595
596 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
597 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
598}
599
600/******************************************************************************
601 * Writes a value to the specified offset in the VLAN filter table.
602 *
603 * hw - Struct containing variables accessed by shared code
604 * offset - Offset in VLAN filer table to write
605 * value - Value to write into VLAN filter table
606 *****************************************************************************/
607void
608ixgb_write_vfta(struct ixgb_hw *hw,
609 u32 offset,
610 u32 value)
611{
612 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
613}
614
615/******************************************************************************
616 * Clears the VLAN filer table
617 *
618 * hw - Struct containing variables accessed by shared code
619 *****************************************************************************/
620static void
621ixgb_clear_vfta(struct ixgb_hw *hw)
622{
623 u32 offset;
624
625 for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
626 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
627}
628
629/******************************************************************************
630 * Configures the flow control settings based on SW configuration.
631 *
632 * hw - Struct containing variables accessed by shared code
633 *****************************************************************************/
634
635static bool
636ixgb_setup_fc(struct ixgb_hw *hw)
637{
638 u32 ctrl_reg;
639 u32 pap_reg = 0; /* by default, assume no pause time */
640 bool status = true;
641
642 ENTER();
643
644 /* Get the current control reg 0 settings */
645 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
646
647 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
648 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
649
650 /* The possible values of the "flow_control" parameter are:
651 * 0: Flow control is completely disabled
652 * 1: Rx flow control is enabled (we can receive pause frames
653 * but not send pause frames).
654 * 2: Tx flow control is enabled (we can send pause frames
655 * but we do not support receiving pause frames).
656 * 3: Both Rx and TX flow control (symmetric) are enabled.
657 * other: Invalid.
658 */
659 switch (hw->fc.type) {
660 case ixgb_fc_none: /* 0 */
661 /* Set CMDC bit to disable Rx Flow control */
662 ctrl_reg |= (IXGB_CTRL0_CMDC);
663 break;
664 case ixgb_fc_rx_pause: /* 1 */
665 /* RX Flow control is enabled, and TX Flow control is
666 * disabled.
667 */
668 ctrl_reg |= (IXGB_CTRL0_RPE);
669 break;
670 case ixgb_fc_tx_pause: /* 2 */
671 /* TX Flow control is enabled, and RX Flow control is
672 * disabled, by a software over-ride.
673 */
674 ctrl_reg |= (IXGB_CTRL0_TPE);
675 pap_reg = hw->fc.pause_time;
676 break;
677 case ixgb_fc_full: /* 3 */
678 /* Flow control (both RX and TX) is enabled by a software
679 * over-ride.
680 */
681 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
682 pap_reg = hw->fc.pause_time;
683 break;
684 default:
685 /* We should never get here. The value should be 0-3. */
686 pr_debug("Flow control param set incorrectly\n");
687 ASSERT(0);
688 break;
689 }
690
691 /* Write the new settings */
692 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
693
694 if (pap_reg != 0)
695 IXGB_WRITE_REG(hw, PAP, pap_reg);
696
697 /* Set the flow control receive threshold registers. Normally,
698 * these registers will be set to a default threshold that may be
699 * adjusted later by the driver's runtime code. However, if the
700 * ability to transmit pause frames in not enabled, then these
701 * registers will be set to 0.
702 */
703 if (!(hw->fc.type & ixgb_fc_tx_pause)) {
704 IXGB_WRITE_REG(hw, FCRTL, 0);
705 IXGB_WRITE_REG(hw, FCRTH, 0);
706 } else {
707 /* We need to set up the Receive Threshold high and low water
708 * marks as well as (optionally) enabling the transmission of XON
709 * frames. */
710 if (hw->fc.send_xon) {
711 IXGB_WRITE_REG(hw, FCRTL,
712 (hw->fc.low_water | IXGB_FCRTL_XONE));
713 } else {
714 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
715 }
716 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
717 }
718 return status;
719}
720
721/******************************************************************************
722 * Reads a word from a device over the Management Data Interface (MDI) bus.
723 * This interface is used to manage Physical layer devices.
724 *
725 * hw - Struct containing variables accessed by hw code
726 * reg_address - Offset of device register being read.
727 * phy_address - Address of device on MDI.
728 *
729 * Returns: Data word (16 bits) from MDI device.
730 *
731 * The 82597EX has support for several MDI access methods. This routine
732 * uses the new protocol MDI Single Command and Address Operation.
733 * This requires that first an address cycle command is sent, followed by a
734 * read command.
735 *****************************************************************************/
736static u16
737ixgb_read_phy_reg(struct ixgb_hw *hw,
738 u32 reg_address,
739 u32 phy_address,
740 u32 device_type)
741{
742 u32 i;
743 u32 data;
744 u32 command = 0;
745
746 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
747 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
748 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
749
750 /* Setup and write the address cycle command */
751 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
752 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
753 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
754 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
755
756 IXGB_WRITE_REG(hw, MSCA, command);
757
758 /**************************************************************
759 ** Check every 10 usec to see if the address cycle completed
760 ** The COMMAND bit will clear when the operation is complete.
761 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
762 ** from the CPU Write to the Ready bit assertion.
763 **************************************************************/
764
765 for (i = 0; i < 10; i++)
766 {
767 udelay(10);
768
769 command = IXGB_READ_REG(hw, MSCA);
770
771 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
772 break;
773 }
774
775 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
776
777 /* Address cycle complete, setup and write the read command */
778 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
779 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
780 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
781 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
782
783 IXGB_WRITE_REG(hw, MSCA, command);
784
785 /**************************************************************
786 ** Check every 10 usec to see if the read command completed
787 ** The COMMAND bit will clear when the operation is complete.
788 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
789 ** from the CPU Write to the Ready bit assertion.
790 **************************************************************/
791
792 for (i = 0; i < 10; i++)
793 {
794 udelay(10);
795
796 command = IXGB_READ_REG(hw, MSCA);
797
798 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
799 break;
800 }
801
802 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
803
804 /* Operation is complete, get the data from the MDIO Read/Write Data
805 * register and return.
806 */
807 data = IXGB_READ_REG(hw, MSRWD);
808 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
809 return((u16) data);
810}
811
812/******************************************************************************
813 * Writes a word to a device over the Management Data Interface (MDI) bus.
814 * This interface is used to manage Physical layer devices.
815 *
816 * hw - Struct containing variables accessed by hw code
817 * reg_address - Offset of device register being read.
818 * phy_address - Address of device on MDI.
819 * device_type - Also known as the Device ID or DID.
820 * data - 16-bit value to be written
821 *
822 * Returns: void.
823 *
824 * The 82597EX has support for several MDI access methods. This routine
825 * uses the new protocol MDI Single Command and Address Operation.
826 * This requires that first an address cycle command is sent, followed by a
827 * write command.
828 *****************************************************************************/
829static void
830ixgb_write_phy_reg(struct ixgb_hw *hw,
831 u32 reg_address,
832 u32 phy_address,
833 u32 device_type,
834 u16 data)
835{
836 u32 i;
837 u32 command = 0;
838
839 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
840 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
841 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
842
843 /* Put the data in the MDIO Read/Write Data register */
844 IXGB_WRITE_REG(hw, MSRWD, (u32)data);
845
846 /* Setup and write the address cycle command */
847 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
848 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
849 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
850 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
851
852 IXGB_WRITE_REG(hw, MSCA, command);
853
854 /**************************************************************
855 ** Check every 10 usec to see if the address cycle completed
856 ** The COMMAND bit will clear when the operation is complete.
857 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
858 ** from the CPU Write to the Ready bit assertion.
859 **************************************************************/
860
861 for (i = 0; i < 10; i++)
862 {
863 udelay(10);
864
865 command = IXGB_READ_REG(hw, MSCA);
866
867 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
868 break;
869 }
870
871 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
872
873 /* Address cycle complete, setup and write the write command */
874 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
875 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
876 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
877 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
878
879 IXGB_WRITE_REG(hw, MSCA, command);
880
881 /**************************************************************
882 ** Check every 10 usec to see if the read command completed
883 ** The COMMAND bit will clear when the operation is complete.
884 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
885 ** from the CPU Write to the Ready bit assertion.
886 **************************************************************/
887
888 for (i = 0; i < 10; i++)
889 {
890 udelay(10);
891
892 command = IXGB_READ_REG(hw, MSCA);
893
894 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
895 break;
896 }
897
898 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
899
900 /* Operation is complete, return. */
901}
902
903/******************************************************************************
904 * Checks to see if the link status of the hardware has changed.
905 *
906 * hw - Struct containing variables accessed by hw code
907 *
908 * Called by any function that needs to check the link status of the adapter.
909 *****************************************************************************/
910void
911ixgb_check_for_link(struct ixgb_hw *hw)
912{
913 u32 status_reg;
914 u32 xpcss_reg;
915
916 ENTER();
917
918 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
919 status_reg = IXGB_READ_REG(hw, STATUS);
920
921 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
922 (status_reg & IXGB_STATUS_LU)) {
923 hw->link_up = true;
924 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
925 (status_reg & IXGB_STATUS_LU)) {
926 pr_debug("XPCSS Not Aligned while Status:LU is set\n");
927 hw->link_up = ixgb_link_reset(hw);
928 } else {
929 /*
930 * 82597EX errata. Since the lane deskew problem may prevent
931 * link, reset the link before reporting link down.
932 */
933 hw->link_up = ixgb_link_reset(hw);
934 }
935 /* Anything else for 10 Gig?? */
936}
937
938/******************************************************************************
939 * Check for a bad link condition that may have occurred.
940 * The indication is that the RFC / LFC registers may be incrementing
941 * continually. A full adapter reset is required to recover.
942 *
943 * hw - Struct containing variables accessed by hw code
944 *
945 * Called by any function that needs to check the link status of the adapter.
946 *****************************************************************************/
947bool ixgb_check_for_bad_link(struct ixgb_hw *hw)
948{
949 u32 newLFC, newRFC;
950 bool bad_link_returncode = false;
951
952 if (hw->phy_type == ixgb_phy_type_txn17401) {
953 newLFC = IXGB_READ_REG(hw, LFC);
954 newRFC = IXGB_READ_REG(hw, RFC);
955 if ((hw->lastLFC + 250 < newLFC)
956 || (hw->lastRFC + 250 < newRFC)) {
957 pr_debug("BAD LINK! too many LFC/RFC since last check\n");
958 bad_link_returncode = true;
959 }
960 hw->lastLFC = newLFC;
961 hw->lastRFC = newRFC;
962 }
963
964 return bad_link_returncode;
965}
966
967/******************************************************************************
968 * Clears all hardware statistics counters.
969 *
970 * hw - Struct containing variables accessed by shared code
971 *****************************************************************************/
972static void
973ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
974{
975 volatile u32 temp_reg;
976
977 ENTER();
978
979 /* if we are stopped or resetting exit gracefully */
980 if (hw->adapter_stopped) {
981 pr_debug("Exiting because the adapter is stopped!!!\n");
982 return;
983 }
984
985 temp_reg = IXGB_READ_REG(hw, TPRL);
986 temp_reg = IXGB_READ_REG(hw, TPRH);
987 temp_reg = IXGB_READ_REG(hw, GPRCL);
988 temp_reg = IXGB_READ_REG(hw, GPRCH);
989 temp_reg = IXGB_READ_REG(hw, BPRCL);
990 temp_reg = IXGB_READ_REG(hw, BPRCH);
991 temp_reg = IXGB_READ_REG(hw, MPRCL);
992 temp_reg = IXGB_READ_REG(hw, MPRCH);
993 temp_reg = IXGB_READ_REG(hw, UPRCL);
994 temp_reg = IXGB_READ_REG(hw, UPRCH);
995 temp_reg = IXGB_READ_REG(hw, VPRCL);
996 temp_reg = IXGB_READ_REG(hw, VPRCH);
997 temp_reg = IXGB_READ_REG(hw, JPRCL);
998 temp_reg = IXGB_READ_REG(hw, JPRCH);
999 temp_reg = IXGB_READ_REG(hw, GORCL);
1000 temp_reg = IXGB_READ_REG(hw, GORCH);
1001 temp_reg = IXGB_READ_REG(hw, TORL);
1002 temp_reg = IXGB_READ_REG(hw, TORH);
1003 temp_reg = IXGB_READ_REG(hw, RNBC);
1004 temp_reg = IXGB_READ_REG(hw, RUC);
1005 temp_reg = IXGB_READ_REG(hw, ROC);
1006 temp_reg = IXGB_READ_REG(hw, RLEC);
1007 temp_reg = IXGB_READ_REG(hw, CRCERRS);
1008 temp_reg = IXGB_READ_REG(hw, ICBC);
1009 temp_reg = IXGB_READ_REG(hw, ECBC);
1010 temp_reg = IXGB_READ_REG(hw, MPC);
1011 temp_reg = IXGB_READ_REG(hw, TPTL);
1012 temp_reg = IXGB_READ_REG(hw, TPTH);
1013 temp_reg = IXGB_READ_REG(hw, GPTCL);
1014 temp_reg = IXGB_READ_REG(hw, GPTCH);
1015 temp_reg = IXGB_READ_REG(hw, BPTCL);
1016 temp_reg = IXGB_READ_REG(hw, BPTCH);
1017 temp_reg = IXGB_READ_REG(hw, MPTCL);
1018 temp_reg = IXGB_READ_REG(hw, MPTCH);
1019 temp_reg = IXGB_READ_REG(hw, UPTCL);
1020 temp_reg = IXGB_READ_REG(hw, UPTCH);
1021 temp_reg = IXGB_READ_REG(hw, VPTCL);
1022 temp_reg = IXGB_READ_REG(hw, VPTCH);
1023 temp_reg = IXGB_READ_REG(hw, JPTCL);
1024 temp_reg = IXGB_READ_REG(hw, JPTCH);
1025 temp_reg = IXGB_READ_REG(hw, GOTCL);
1026 temp_reg = IXGB_READ_REG(hw, GOTCH);
1027 temp_reg = IXGB_READ_REG(hw, TOTL);
1028 temp_reg = IXGB_READ_REG(hw, TOTH);
1029 temp_reg = IXGB_READ_REG(hw, DC);
1030 temp_reg = IXGB_READ_REG(hw, PLT64C);
1031 temp_reg = IXGB_READ_REG(hw, TSCTC);
1032 temp_reg = IXGB_READ_REG(hw, TSCTFC);
1033 temp_reg = IXGB_READ_REG(hw, IBIC);
1034 temp_reg = IXGB_READ_REG(hw, RFC);
1035 temp_reg = IXGB_READ_REG(hw, LFC);
1036 temp_reg = IXGB_READ_REG(hw, PFRC);
1037 temp_reg = IXGB_READ_REG(hw, PFTC);
1038 temp_reg = IXGB_READ_REG(hw, MCFRC);
1039 temp_reg = IXGB_READ_REG(hw, MCFTC);
1040 temp_reg = IXGB_READ_REG(hw, XONRXC);
1041 temp_reg = IXGB_READ_REG(hw, XONTXC);
1042 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1043 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1044 temp_reg = IXGB_READ_REG(hw, RJC);
1045}
1046
1047/******************************************************************************
1048 * Turns on the software controllable LED
1049 *
1050 * hw - Struct containing variables accessed by shared code
1051 *****************************************************************************/
1052void
1053ixgb_led_on(struct ixgb_hw *hw)
1054{
1055 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1056
1057 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1058 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1059 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1060}
1061
1062/******************************************************************************
1063 * Turns off the software controllable LED
1064 *
1065 * hw - Struct containing variables accessed by shared code
1066 *****************************************************************************/
1067void
1068ixgb_led_off(struct ixgb_hw *hw)
1069{
1070 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1071
1072 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1073 ctrl0_reg |= IXGB_CTRL0_SDP0;
1074 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1075}
1076
1077/******************************************************************************
1078 * Gets the current PCI bus type, speed, and width of the hardware
1079 *
1080 * hw - Struct containing variables accessed by shared code
1081 *****************************************************************************/
1082static void
1083ixgb_get_bus_info(struct ixgb_hw *hw)
1084{
1085 u32 status_reg;
1086
1087 status_reg = IXGB_READ_REG(hw, STATUS);
1088
1089 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
1090 ixgb_bus_type_pcix : ixgb_bus_type_pci;
1091
1092 if (hw->bus.type == ixgb_bus_type_pci) {
1093 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
1094 ixgb_bus_speed_66 : ixgb_bus_speed_33;
1095 } else {
1096 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1097 case IXGB_STATUS_PCIX_SPD_66:
1098 hw->bus.speed = ixgb_bus_speed_66;
1099 break;
1100 case IXGB_STATUS_PCIX_SPD_100:
1101 hw->bus.speed = ixgb_bus_speed_100;
1102 break;
1103 case IXGB_STATUS_PCIX_SPD_133:
1104 hw->bus.speed = ixgb_bus_speed_133;
1105 break;
1106 default:
1107 hw->bus.speed = ixgb_bus_speed_reserved;
1108 break;
1109 }
1110 }
1111
1112 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
1113 ixgb_bus_width_64 : ixgb_bus_width_32;
1114}
1115
1116/******************************************************************************
1117 * Tests a MAC address to ensure it is a valid Individual Address
1118 *
1119 * mac_addr - pointer to MAC address.
1120 *
1121 *****************************************************************************/
1122static bool
1123mac_addr_valid(u8 *mac_addr)
1124{
1125 bool is_valid = true;
1126 ENTER();
1127
1128 /* Make sure it is not a multicast address */
1129 if (is_multicast_ether_addr(mac_addr)) {
1130 pr_debug("MAC address is multicast\n");
1131 is_valid = false;
1132 }
1133 /* Not a broadcast address */
1134 else if (is_broadcast_ether_addr(mac_addr)) {
1135 pr_debug("MAC address is broadcast\n");
1136 is_valid = false;
1137 }
1138 /* Reject the zero address */
1139 else if (is_zero_ether_addr(mac_addr)) {
1140 pr_debug("MAC address is all zeros\n");
1141 is_valid = false;
1142 }
1143 return is_valid;
1144}
1145
1146/******************************************************************************
1147 * Resets the 10GbE link. Waits the settle time and returns the state of
1148 * the link.
1149 *
1150 * hw - Struct containing variables accessed by shared code
1151 *****************************************************************************/
1152static bool
1153ixgb_link_reset(struct ixgb_hw *hw)
1154{
1155 bool link_status = false;
1156 u8 wait_retries = MAX_RESET_ITERATIONS;
1157 u8 lrst_retries = MAX_RESET_ITERATIONS;
1158
1159 do {
1160 /* Reset the link */
1161 IXGB_WRITE_REG(hw, CTRL0,
1162 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1163
1164 /* Wait for link-up and lane re-alignment */
1165 do {
1166 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1167 link_status =
1168 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
1169 && (IXGB_READ_REG(hw, XPCSS) &
1170 IXGB_XPCSS_ALIGN_STATUS)) ? true : false;
1171 } while (!link_status && --wait_retries);
1172
1173 } while (!link_status && --lrst_retries);
1174
1175 return link_status;
1176}
1177
1178/******************************************************************************
1179 * Resets the 10GbE optics module.
1180 *
1181 * hw - Struct containing variables accessed by shared code
1182 *****************************************************************************/
1183static void
1184ixgb_optics_reset(struct ixgb_hw *hw)
1185{
1186 if (hw->phy_type == ixgb_phy_type_txn17401) {
1187 u16 mdio_reg;
1188
1189 ixgb_write_phy_reg(hw,
1190 MDIO_CTRL1,
1191 IXGB_PHY_ADDRESS,
1192 MDIO_MMD_PMAPMD,
1193 MDIO_CTRL1_RESET);
1194
1195 mdio_reg = ixgb_read_phy_reg(hw,
1196 MDIO_CTRL1,
1197 IXGB_PHY_ADDRESS,
1198 MDIO_MMD_PMAPMD);
1199 }
1200}
1201
1202/******************************************************************************
1203 * Resets the 10GbE optics module for Sun variant NIC.
1204 *
1205 * hw - Struct containing variables accessed by shared code
1206 *****************************************************************************/
1207
1208#define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
1209#define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
1210#define IXGB_BCM8704_USER_CTRL_REG 0xC800
1211#define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
1212#define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
1213#define IXGB_SUN_PHY_ADDRESS 0x0000
1214#define IXGB_SUN_PHY_RESET_DELAY 305
1215
1216static void
1217ixgb_optics_reset_bcm(struct ixgb_hw *hw)
1218{
1219 u32 ctrl = IXGB_READ_REG(hw, CTRL0);
1220 ctrl &= ~IXGB_CTRL0_SDP2;
1221 ctrl |= IXGB_CTRL0_SDP3;
1222 IXGB_WRITE_REG(hw, CTRL0, ctrl);
1223
1224 /* SerDes needs extra delay */
1225 msleep(IXGB_SUN_PHY_RESET_DELAY);
1226
1227 /* Broadcom 7408L configuration */
1228 /* Reference clock config */
1229 ixgb_write_phy_reg(hw,
1230 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1231 IXGB_SUN_PHY_ADDRESS,
1232 IXGB_BCM8704_USER_DEV3_ADDR,
1233 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL);
1234 /* we must read the registers twice */
1235 ixgb_read_phy_reg(hw,
1236 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1237 IXGB_SUN_PHY_ADDRESS,
1238 IXGB_BCM8704_USER_DEV3_ADDR);
1239 ixgb_read_phy_reg(hw,
1240 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1241 IXGB_SUN_PHY_ADDRESS,
1242 IXGB_BCM8704_USER_DEV3_ADDR);
1243
1244 ixgb_write_phy_reg(hw,
1245 IXGB_BCM8704_USER_CTRL_REG,
1246 IXGB_SUN_PHY_ADDRESS,
1247 IXGB_BCM8704_USER_DEV3_ADDR,
1248 IXGB_BCM8704_USER_CTRL_REG_VAL);
1249 ixgb_read_phy_reg(hw,
1250 IXGB_BCM8704_USER_CTRL_REG,
1251 IXGB_SUN_PHY_ADDRESS,
1252 IXGB_BCM8704_USER_DEV3_ADDR);
1253 ixgb_read_phy_reg(hw,
1254 IXGB_BCM8704_USER_CTRL_REG,
1255 IXGB_SUN_PHY_ADDRESS,
1256 IXGB_BCM8704_USER_DEV3_ADDR);
1257
1258 /* SerDes needs extra delay */
1259 msleep(IXGB_SUN_PHY_RESET_DELAY);
1260}