/drivers/net/enic/vnic_rq.h

  1/*
  2 * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.
  3 * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
  4 *
  5 * This program is free software; you may redistribute it and/or modify
  6 * it under the terms of the GNU General Public License as published by
  7 * the Free Software Foundation; version 2 of the License.
  8 *
  9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 16 * SOFTWARE.
 17 *
 18 */
 19
 20#ifndef _VNIC_RQ_H_
 21#define _VNIC_RQ_H_
 22
 23#include <linux/pci.h>
 24
 25#include "vnic_dev.h"
 26#include "vnic_cq.h"
 27
 28/* Receive queue control */
 29struct vnic_rq_ctrl {
 30	u64 ring_base;			/* 0x00 */
 31	u32 ring_size;			/* 0x08 */
 32	u32 pad0;
 33	u32 posted_index;		/* 0x10 */
 34	u32 pad1;
 35	u32 cq_index;			/* 0x18 */
 36	u32 pad2;
 37	u32 enable;			/* 0x20 */
 38	u32 pad3;
 39	u32 running;			/* 0x28 */
 40	u32 pad4;
 41	u32 fetch_index;		/* 0x30 */
 42	u32 pad5;
 43	u32 error_interrupt_enable;	/* 0x38 */
 44	u32 pad6;
 45	u32 error_interrupt_offset;	/* 0x40 */
 46	u32 pad7;
 47	u32 error_status;		/* 0x48 */
 48	u32 pad8;
 49	u32 dropped_packet_count;	/* 0x50 */
 50	u32 pad9;
 51	u32 dropped_packet_count_rc;	/* 0x58 */
 52	u32 pad10;
 53};
 54
 55/* Break the vnic_rq_buf allocations into blocks of 32/64 entries */
 56#define VNIC_RQ_BUF_MIN_BLK_ENTRIES 32
 57#define VNIC_RQ_BUF_DFLT_BLK_ENTRIES 64
 58#define VNIC_RQ_BUF_BLK_ENTRIES(entries) \
 59	((unsigned int)((entries < VNIC_RQ_BUF_DFLT_BLK_ENTRIES) ? \
 60	VNIC_RQ_BUF_MIN_BLK_ENTRIES : VNIC_RQ_BUF_DFLT_BLK_ENTRIES))
 61#define VNIC_RQ_BUF_BLK_SZ(entries) \
 62	(VNIC_RQ_BUF_BLK_ENTRIES(entries) * sizeof(struct vnic_rq_buf))
 63#define VNIC_RQ_BUF_BLKS_NEEDED(entries) \
 64	DIV_ROUND_UP(entries, VNIC_RQ_BUF_BLK_ENTRIES(entries))
 65#define VNIC_RQ_BUF_BLKS_MAX VNIC_RQ_BUF_BLKS_NEEDED(4096)
 66
 67struct vnic_rq_buf {
 68	struct vnic_rq_buf *next;
 69	dma_addr_t dma_addr;
 70	void *os_buf;
 71	unsigned int os_buf_index;
 72	unsigned int len;
 73	unsigned int index;
 74	void *desc;
 75};
 76
 77struct vnic_rq {
 78	unsigned int index;
 79	struct vnic_dev *vdev;
 80	struct vnic_rq_ctrl __iomem *ctrl;              /* memory-mapped */
 81	struct vnic_dev_ring ring;
 82	struct vnic_rq_buf *bufs[VNIC_RQ_BUF_BLKS_MAX];
 83	struct vnic_rq_buf *to_use;
 84	struct vnic_rq_buf *to_clean;
 85	void *os_buf_head;
 86	unsigned int pkts_outstanding;
 87};
 88
 89static inline unsigned int vnic_rq_desc_avail(struct vnic_rq *rq)
 90{
 91	/* how many does SW own? */
 92	return rq->ring.desc_avail;
 93}
 94
 95static inline unsigned int vnic_rq_desc_used(struct vnic_rq *rq)
 96{
 97	/* how many does HW own? */
 98	return rq->ring.desc_count - rq->ring.desc_avail - 1;
 99}
100
101static inline void *vnic_rq_next_desc(struct vnic_rq *rq)
102{
103	return rq->to_use->desc;
104}
105
106static inline unsigned int vnic_rq_next_index(struct vnic_rq *rq)
107{
108	return rq->to_use->index;
109}
110
111static inline void vnic_rq_post(struct vnic_rq *rq,
112	void *os_buf, unsigned int os_buf_index,
113	dma_addr_t dma_addr, unsigned int len)
114{
115	struct vnic_rq_buf *buf = rq->to_use;
116
117	buf->os_buf = os_buf;
118	buf->os_buf_index = os_buf_index;
119	buf->dma_addr = dma_addr;
120	buf->len = len;
121
122	buf = buf->next;
123	rq->to_use = buf;
124	rq->ring.desc_avail--;
125
126	/* Move the posted_index every nth descriptor
127	 */
128
129#ifndef VNIC_RQ_RETURN_RATE
130#define VNIC_RQ_RETURN_RATE		0xf	/* keep 2^n - 1 */
131#endif
132
133	if ((buf->index & VNIC_RQ_RETURN_RATE) == 0) {
134		/* Adding write memory barrier prevents compiler and/or CPU
135		 * reordering, thus avoiding descriptor posting before
136		 * descriptor is initialized. Otherwise, hardware can read
137		 * stale descriptor fields.
138		 */
139		wmb();
140		iowrite32(buf->index, &rq->ctrl->posted_index);
141	}
142}
143
144static inline void vnic_rq_return_descs(struct vnic_rq *rq, unsigned int count)
145{
146	rq->ring.desc_avail += count;
147}
148
149enum desc_return_options {
150	VNIC_RQ_RETURN_DESC,
151	VNIC_RQ_DEFER_RETURN_DESC,
152};
153
154static inline void vnic_rq_service(struct vnic_rq *rq,
155	struct cq_desc *cq_desc, u16 completed_index,
156	int desc_return, void (*buf_service)(struct vnic_rq *rq,
157	struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
158	int skipped, void *opaque), void *opaque)
159{
160	struct vnic_rq_buf *buf;
161	int skipped;
162
163	buf = rq->to_clean;
164	while (1) {
165
166		skipped = (buf->index != completed_index);
167
168		(*buf_service)(rq, cq_desc, buf, skipped, opaque);
169
170		if (desc_return == VNIC_RQ_RETURN_DESC)
171			rq->ring.desc_avail++;
172
173		rq->to_clean = buf->next;
174
175		if (!skipped)
176			break;
177
178		buf = rq->to_clean;
179	}
180}
181
182static inline int vnic_rq_fill(struct vnic_rq *rq,
183	int (*buf_fill)(struct vnic_rq *rq))
184{
185	int err;
186
187	while (vnic_rq_desc_avail(rq) > 0) {
188
189		err = (*buf_fill)(rq);
190		if (err)
191			return err;
192	}
193
194	return 0;
195}
196
197void vnic_rq_free(struct vnic_rq *rq);
198int vnic_rq_alloc(struct vnic_dev *vdev, struct vnic_rq *rq, unsigned int index,
199	unsigned int desc_count, unsigned int desc_size);
200void vnic_rq_init(struct vnic_rq *rq, unsigned int cq_index,
201	unsigned int error_interrupt_enable,
202	unsigned int error_interrupt_offset);
203unsigned int vnic_rq_error_status(struct vnic_rq *rq);
204void vnic_rq_enable(struct vnic_rq *rq);
205int vnic_rq_disable(struct vnic_rq *rq);
206void vnic_rq_clean(struct vnic_rq *rq,
207	void (*buf_clean)(struct vnic_rq *rq, struct vnic_rq_buf *buf));
208
209#endif /* _VNIC_RQ_H_ */