/drivers/net/chelsio/regs.h

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  1. /*****************************************************************************
  2. * *
  3. * File: regs.h *
  4. * $Revision: 1.8 $ *
  5. * $Date: 2005/06/21 18:29:48 $ *
  6. * Description: *
  7. * part of the Chelsio 10Gb Ethernet Driver. *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License, version 2, as *
  11. * published by the Free Software Foundation. *
  12. * *
  13. * You should have received a copy of the GNU General Public License along *
  14. * with this program; if not, write to the Free Software Foundation, Inc., *
  15. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  16. * *
  17. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
  18. * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
  19. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
  20. * *
  21. * http://www.chelsio.com *
  22. * *
  23. * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
  24. * All rights reserved. *
  25. * *
  26. * Maintainers: maintainers@chelsio.com *
  27. * *
  28. * Authors: Dimitrios Michailidis <dm@chelsio.com> *
  29. * Tina Yang <tainay@chelsio.com> *
  30. * Felix Marti <felix@chelsio.com> *
  31. * Scott Bardone <sbardone@chelsio.com> *
  32. * Kurt Ottaway <kottaway@chelsio.com> *
  33. * Frank DiMambro <frank@chelsio.com> *
  34. * *
  35. * History: *
  36. * *
  37. ****************************************************************************/
  38. #ifndef _CXGB_REGS_H_
  39. #define _CXGB_REGS_H_
  40. /* SGE registers */
  41. #define A_SG_CONTROL 0x0
  42. #define S_CMDQ0_ENABLE 0
  43. #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)
  44. #define F_CMDQ0_ENABLE V_CMDQ0_ENABLE(1U)
  45. #define S_CMDQ1_ENABLE 1
  46. #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)
  47. #define F_CMDQ1_ENABLE V_CMDQ1_ENABLE(1U)
  48. #define S_FL0_ENABLE 2
  49. #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)
  50. #define F_FL0_ENABLE V_FL0_ENABLE(1U)
  51. #define S_FL1_ENABLE 3
  52. #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)
  53. #define F_FL1_ENABLE V_FL1_ENABLE(1U)
  54. #define S_CPL_ENABLE 4
  55. #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)
  56. #define F_CPL_ENABLE V_CPL_ENABLE(1U)
  57. #define S_RESPONSE_QUEUE_ENABLE 5
  58. #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)
  59. #define F_RESPONSE_QUEUE_ENABLE V_RESPONSE_QUEUE_ENABLE(1U)
  60. #define S_CMDQ_PRIORITY 6
  61. #define M_CMDQ_PRIORITY 0x3
  62. #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)
  63. #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)
  64. #define S_DISABLE_CMDQ0_GTS 8
  65. #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS)
  66. #define F_DISABLE_CMDQ0_GTS V_DISABLE_CMDQ0_GTS(1U)
  67. #define S_DISABLE_CMDQ1_GTS 9
  68. #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)
  69. #define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U)
  70. #define S_DISABLE_FL0_GTS 10
  71. #define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS)
  72. #define F_DISABLE_FL0_GTS V_DISABLE_FL0_GTS(1U)
  73. #define S_DISABLE_FL1_GTS 11
  74. #define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS)
  75. #define F_DISABLE_FL1_GTS V_DISABLE_FL1_GTS(1U)
  76. #define S_ENABLE_BIG_ENDIAN 12
  77. #define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)
  78. #define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U)
  79. #define S_FL_SELECTION_CRITERIA 13
  80. #define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA)
  81. #define F_FL_SELECTION_CRITERIA V_FL_SELECTION_CRITERIA(1U)
  82. #define S_ISCSI_COALESCE 14
  83. #define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)
  84. #define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U)
  85. #define S_RX_PKT_OFFSET 15
  86. #define M_RX_PKT_OFFSET 0x7
  87. #define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)
  88. #define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET)
  89. #define S_VLAN_XTRACT 18
  90. #define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)
  91. #define F_VLAN_XTRACT V_VLAN_XTRACT(1U)
  92. #define A_SG_DOORBELL 0x4
  93. #define A_SG_CMD0BASELWR 0x8
  94. #define A_SG_CMD0BASEUPR 0xc
  95. #define A_SG_CMD1BASELWR 0x10
  96. #define A_SG_CMD1BASEUPR 0x14
  97. #define A_SG_FL0BASELWR 0x18
  98. #define A_SG_FL0BASEUPR 0x1c
  99. #define A_SG_FL1BASELWR 0x20
  100. #define A_SG_FL1BASEUPR 0x24
  101. #define A_SG_CMD0SIZE 0x28
  102. #define S_CMDQ0_SIZE 0
  103. #define M_CMDQ0_SIZE 0x1ffff
  104. #define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE)
  105. #define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE)
  106. #define A_SG_FL0SIZE 0x2c
  107. #define S_FL0_SIZE 0
  108. #define M_FL0_SIZE 0x1ffff
  109. #define V_FL0_SIZE(x) ((x) << S_FL0_SIZE)
  110. #define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE)
  111. #define A_SG_RSPSIZE 0x30
  112. #define S_RESPQ_SIZE 0
  113. #define M_RESPQ_SIZE 0x1ffff
  114. #define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE)
  115. #define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE)
  116. #define A_SG_RSPBASELWR 0x34
  117. #define A_SG_RSPBASEUPR 0x38
  118. #define A_SG_FLTHRESHOLD 0x3c
  119. #define S_FL_THRESHOLD 0
  120. #define M_FL_THRESHOLD 0xffff
  121. #define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD)
  122. #define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD)
  123. #define A_SG_RSPQUEUECREDIT 0x40
  124. #define S_RESPQ_CREDIT 0
  125. #define M_RESPQ_CREDIT 0x1ffff
  126. #define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT)
  127. #define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT)
  128. #define A_SG_SLEEPING 0x48
  129. #define S_SLEEPING 0
  130. #define M_SLEEPING 0xffff
  131. #define V_SLEEPING(x) ((x) << S_SLEEPING)
  132. #define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING)
  133. #define A_SG_INTRTIMER 0x4c
  134. #define S_INTERRUPT_TIMER_COUNT 0
  135. #define M_INTERRUPT_TIMER_COUNT 0xffffff
  136. #define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT)
  137. #define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT)
  138. #define A_SG_CMD0PTR 0x50
  139. #define S_CMDQ0_POINTER 0
  140. #define M_CMDQ0_POINTER 0xffff
  141. #define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER)
  142. #define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER)
  143. #define S_CURRENT_GENERATION_BIT 16
  144. #define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT)
  145. #define F_CURRENT_GENERATION_BIT V_CURRENT_GENERATION_BIT(1U)
  146. #define A_SG_CMD1PTR 0x54
  147. #define S_CMDQ1_POINTER 0
  148. #define M_CMDQ1_POINTER 0xffff
  149. #define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER)
  150. #define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER)
  151. #define A_SG_FL0PTR 0x58
  152. #define S_FL0_POINTER 0
  153. #define M_FL0_POINTER 0xffff
  154. #define V_FL0_POINTER(x) ((x) << S_FL0_POINTER)
  155. #define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER)
  156. #define A_SG_FL1PTR 0x5c
  157. #define S_FL1_POINTER 0
  158. #define M_FL1_POINTER 0xffff
  159. #define V_FL1_POINTER(x) ((x) << S_FL1_POINTER)
  160. #define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER)
  161. #define A_SG_VERSION 0x6c
  162. #define S_DAY 0
  163. #define M_DAY 0x1f
  164. #define V_DAY(x) ((x) << S_DAY)
  165. #define G_DAY(x) (((x) >> S_DAY) & M_DAY)
  166. #define S_MONTH 5
  167. #define M_MONTH 0xf
  168. #define V_MONTH(x) ((x) << S_MONTH)
  169. #define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH)
  170. #define A_SG_CMD1SIZE 0xb0
  171. #define S_CMDQ1_SIZE 0
  172. #define M_CMDQ1_SIZE 0x1ffff
  173. #define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE)
  174. #define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE)
  175. #define A_SG_FL1SIZE 0xb4
  176. #define S_FL1_SIZE 0
  177. #define M_FL1_SIZE 0x1ffff
  178. #define V_FL1_SIZE(x) ((x) << S_FL1_SIZE)
  179. #define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE)
  180. #define A_SG_INT_ENABLE 0xb8
  181. #define S_RESPQ_EXHAUSTED 0
  182. #define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED)
  183. #define F_RESPQ_EXHAUSTED V_RESPQ_EXHAUSTED(1U)
  184. #define S_RESPQ_OVERFLOW 1
  185. #define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW)
  186. #define F_RESPQ_OVERFLOW V_RESPQ_OVERFLOW(1U)
  187. #define S_FL_EXHAUSTED 2
  188. #define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED)
  189. #define F_FL_EXHAUSTED V_FL_EXHAUSTED(1U)
  190. #define S_PACKET_TOO_BIG 3
  191. #define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG)
  192. #define F_PACKET_TOO_BIG V_PACKET_TOO_BIG(1U)
  193. #define S_PACKET_MISMATCH 4
  194. #define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH)
  195. #define F_PACKET_MISMATCH V_PACKET_MISMATCH(1U)
  196. #define A_SG_INT_CAUSE 0xbc
  197. #define A_SG_RESPACCUTIMER 0xc0
  198. /* MC3 registers */
  199. #define A_MC3_CFG 0x100
  200. #define S_CLK_ENABLE 0
  201. #define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE)
  202. #define F_CLK_ENABLE V_CLK_ENABLE(1U)
  203. #define S_READY 1
  204. #define V_READY(x) ((x) << S_READY)
  205. #define F_READY V_READY(1U)
  206. #define S_READ_TO_WRITE_DELAY 2
  207. #define M_READ_TO_WRITE_DELAY 0x7
  208. #define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY)
  209. #define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY)
  210. #define S_WRITE_TO_READ_DELAY 5
  211. #define M_WRITE_TO_READ_DELAY 0x7
  212. #define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY)
  213. #define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY)
  214. #define S_MC3_BANK_CYCLE 8
  215. #define M_MC3_BANK_CYCLE 0xf
  216. #define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE)
  217. #define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE)
  218. #define S_REFRESH_CYCLE 12
  219. #define M_REFRESH_CYCLE 0xf
  220. #define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE)
  221. #define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE)
  222. #define S_PRECHARGE_CYCLE 16
  223. #define M_PRECHARGE_CYCLE 0x3
  224. #define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE)
  225. #define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE)
  226. #define S_ACTIVE_TO_READ_WRITE_DELAY 18
  227. #define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY)
  228. #define F_ACTIVE_TO_READ_WRITE_DELAY V_ACTIVE_TO_READ_WRITE_DELAY(1U)
  229. #define S_ACTIVE_TO_PRECHARGE_DELAY 19
  230. #define M_ACTIVE_TO_PRECHARGE_DELAY 0x7
  231. #define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY)
  232. #define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY)
  233. #define S_WRITE_RECOVERY_DELAY 22
  234. #define M_WRITE_RECOVERY_DELAY 0x3
  235. #define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY)
  236. #define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY)
  237. #define S_DENSITY 24
  238. #define M_DENSITY 0x3
  239. #define V_DENSITY(x) ((x) << S_DENSITY)
  240. #define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY)
  241. #define S_ORGANIZATION 26
  242. #define V_ORGANIZATION(x) ((x) << S_ORGANIZATION)
  243. #define F_ORGANIZATION V_ORGANIZATION(1U)
  244. #define S_BANKS 27
  245. #define V_BANKS(x) ((x) << S_BANKS)
  246. #define F_BANKS V_BANKS(1U)
  247. #define S_UNREGISTERED 28
  248. #define V_UNREGISTERED(x) ((x) << S_UNREGISTERED)
  249. #define F_UNREGISTERED V_UNREGISTERED(1U)
  250. #define S_MC3_WIDTH 29
  251. #define M_MC3_WIDTH 0x3
  252. #define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH)
  253. #define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH)
  254. #define S_MC3_SLOW 31
  255. #define V_MC3_SLOW(x) ((x) << S_MC3_SLOW)
  256. #define F_MC3_SLOW V_MC3_SLOW(1U)
  257. #define A_MC3_MODE 0x104
  258. #define S_MC3_MODE 0
  259. #define M_MC3_MODE 0x3fff
  260. #define V_MC3_MODE(x) ((x) << S_MC3_MODE)
  261. #define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE)
  262. #define S_BUSY 31
  263. #define V_BUSY(x) ((x) << S_BUSY)
  264. #define F_BUSY V_BUSY(1U)
  265. #define A_MC3_EXT_MODE 0x108
  266. #define S_MC3_EXTENDED_MODE 0
  267. #define M_MC3_EXTENDED_MODE 0x3fff
  268. #define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE)
  269. #define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE)
  270. #define A_MC3_PRECHARG 0x10c
  271. #define A_MC3_REFRESH 0x110
  272. #define S_REFRESH_ENABLE 0
  273. #define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE)
  274. #define F_REFRESH_ENABLE V_REFRESH_ENABLE(1U)
  275. #define S_REFRESH_DIVISOR 1
  276. #define M_REFRESH_DIVISOR 0x3fff
  277. #define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR)
  278. #define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR)
  279. #define A_MC3_STROBE 0x114
  280. #define S_MASTER_DLL_RESET 0
  281. #define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET)
  282. #define F_MASTER_DLL_RESET V_MASTER_DLL_RESET(1U)
  283. #define S_MASTER_DLL_TAP_COUNT 1
  284. #define M_MASTER_DLL_TAP_COUNT 0xff
  285. #define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT)
  286. #define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT)
  287. #define S_MASTER_DLL_LOCKED 9
  288. #define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED)
  289. #define F_MASTER_DLL_LOCKED V_MASTER_DLL_LOCKED(1U)
  290. #define S_MASTER_DLL_MAX_TAP_COUNT 10
  291. #define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT)
  292. #define F_MASTER_DLL_MAX_TAP_COUNT V_MASTER_DLL_MAX_TAP_COUNT(1U)
  293. #define S_MASTER_DLL_TAP_COUNT_OFFSET 11
  294. #define M_MASTER_DLL_TAP_COUNT_OFFSET 0x3f
  295. #define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET)
  296. #define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET)
  297. #define S_SLAVE_DLL_RESET 11
  298. #define V_SLAVE_DLL_RESET(x) ((x) << S_SLAVE_DLL_RESET)
  299. #define F_SLAVE_DLL_RESET V_SLAVE_DLL_RESET(1U)
  300. #define S_SLAVE_DLL_DELTA 12
  301. #define M_SLAVE_DLL_DELTA 0xf
  302. #define V_SLAVE_DLL_DELTA(x) ((x) << S_SLAVE_DLL_DELTA)
  303. #define G_SLAVE_DLL_DELTA(x) (((x) >> S_SLAVE_DLL_DELTA) & M_SLAVE_DLL_DELTA)
  304. #define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 17
  305. #define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 0x3f
  306. #define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
  307. #define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
  308. #define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE 23
  309. #define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE)
  310. #define F_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(1U)
  311. #define S_SLAVE_DELAY_LINE_TAP_COUNT 24
  312. #define M_SLAVE_DELAY_LINE_TAP_COUNT 0x3f
  313. #define V_SLAVE_DELAY_LINE_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_TAP_COUNT)
  314. #define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT)
  315. #define A_MC3_ECC_CNTL 0x118
  316. #define S_ECC_GENERATION_ENABLE 0
  317. #define V_ECC_GENERATION_ENABLE(x) ((x) << S_ECC_GENERATION_ENABLE)
  318. #define F_ECC_GENERATION_ENABLE V_ECC_GENERATION_ENABLE(1U)
  319. #define S_ECC_CHECK_ENABLE 1
  320. #define V_ECC_CHECK_ENABLE(x) ((x) << S_ECC_CHECK_ENABLE)
  321. #define F_ECC_CHECK_ENABLE V_ECC_CHECK_ENABLE(1U)
  322. #define S_CORRECTABLE_ERROR_COUNT 2
  323. #define M_CORRECTABLE_ERROR_COUNT 0xff
  324. #define V_CORRECTABLE_ERROR_COUNT(x) ((x) << S_CORRECTABLE_ERROR_COUNT)
  325. #define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT)
  326. #define S_UNCORRECTABLE_ERROR_COUNT 10
  327. #define M_UNCORRECTABLE_ERROR_COUNT 0xff
  328. #define V_UNCORRECTABLE_ERROR_COUNT(x) ((x) << S_UNCORRECTABLE_ERROR_COUNT)
  329. #define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT)
  330. #define A_MC3_CE_ADDR 0x11c
  331. #define S_MC3_CE_ADDR 4
  332. #define M_MC3_CE_ADDR 0xfffffff
  333. #define V_MC3_CE_ADDR(x) ((x) << S_MC3_CE_ADDR)
  334. #define G_MC3_CE_ADDR(x) (((x) >> S_MC3_CE_ADDR) & M_MC3_CE_ADDR)
  335. #define A_MC3_CE_DATA0 0x120
  336. #define A_MC3_CE_DATA1 0x124
  337. #define A_MC3_CE_DATA2 0x128
  338. #define A_MC3_CE_DATA3 0x12c
  339. #define A_MC3_CE_DATA4 0x130
  340. #define A_MC3_UE_ADDR 0x134
  341. #define S_MC3_UE_ADDR 4
  342. #define M_MC3_UE_ADDR 0xfffffff
  343. #define V_MC3_UE_ADDR(x) ((x) << S_MC3_UE_ADDR)
  344. #define G_MC3_UE_ADDR(x) (((x) >> S_MC3_UE_ADDR) & M_MC3_UE_ADDR)
  345. #define A_MC3_UE_DATA0 0x138
  346. #define A_MC3_UE_DATA1 0x13c
  347. #define A_MC3_UE_DATA2 0x140
  348. #define A_MC3_UE_DATA3 0x144
  349. #define A_MC3_UE_DATA4 0x148
  350. #define A_MC3_BD_ADDR 0x14c
  351. #define A_MC3_BD_DATA0 0x150
  352. #define A_MC3_BD_DATA1 0x154
  353. #define A_MC3_BD_DATA2 0x158
  354. #define A_MC3_BD_DATA3 0x15c
  355. #define A_MC3_BD_DATA4 0x160
  356. #define A_MC3_BD_OP 0x164
  357. #define S_BACK_DOOR_OPERATION 0
  358. #define V_BACK_DOOR_OPERATION(x) ((x) << S_BACK_DOOR_OPERATION)
  359. #define F_BACK_DOOR_OPERATION V_BACK_DOOR_OPERATION(1U)
  360. #define A_MC3_BIST_ADDR_BEG 0x168
  361. #define A_MC3_BIST_ADDR_END 0x16c
  362. #define A_MC3_BIST_DATA 0x170
  363. #define A_MC3_BIST_OP 0x174
  364. #define S_OP 0
  365. #define V_OP(x) ((x) << S_OP)
  366. #define F_OP V_OP(1U)
  367. #define S_DATA_PATTERN 1
  368. #define M_DATA_PATTERN 0x3
  369. #define V_DATA_PATTERN(x) ((x) << S_DATA_PATTERN)
  370. #define G_DATA_PATTERN(x) (((x) >> S_DATA_PATTERN) & M_DATA_PATTERN)
  371. #define S_CONTINUOUS 3
  372. #define V_CONTINUOUS(x) ((x) << S_CONTINUOUS)
  373. #define F_CONTINUOUS V_CONTINUOUS(1U)
  374. #define A_MC3_INT_ENABLE 0x178
  375. #define S_MC3_CORR_ERR 0
  376. #define V_MC3_CORR_ERR(x) ((x) << S_MC3_CORR_ERR)
  377. #define F_MC3_CORR_ERR V_MC3_CORR_ERR(1U)
  378. #define S_MC3_UNCORR_ERR 1
  379. #define V_MC3_UNCORR_ERR(x) ((x) << S_MC3_UNCORR_ERR)
  380. #define F_MC3_UNCORR_ERR V_MC3_UNCORR_ERR(1U)
  381. #define S_MC3_PARITY_ERR 2
  382. #define M_MC3_PARITY_ERR 0xff
  383. #define V_MC3_PARITY_ERR(x) ((x) << S_MC3_PARITY_ERR)
  384. #define G_MC3_PARITY_ERR(x) (((x) >> S_MC3_PARITY_ERR) & M_MC3_PARITY_ERR)
  385. #define S_MC3_ADDR_ERR 10
  386. #define V_MC3_ADDR_ERR(x) ((x) << S_MC3_ADDR_ERR)
  387. #define F_MC3_ADDR_ERR V_MC3_ADDR_ERR(1U)
  388. #define A_MC3_INT_CAUSE 0x17c
  389. /* MC4 registers */
  390. #define A_MC4_CFG 0x180
  391. #define S_POWER_UP 0
  392. #define V_POWER_UP(x) ((x) << S_POWER_UP)
  393. #define F_POWER_UP V_POWER_UP(1U)
  394. #define S_MC4_BANK_CYCLE 8
  395. #define M_MC4_BANK_CYCLE 0x7
  396. #define V_MC4_BANK_CYCLE(x) ((x) << S_MC4_BANK_CYCLE)
  397. #define G_MC4_BANK_CYCLE(x) (((x) >> S_MC4_BANK_CYCLE) & M_MC4_BANK_CYCLE)
  398. #define S_MC4_NARROW 24
  399. #define V_MC4_NARROW(x) ((x) << S_MC4_NARROW)
  400. #define F_MC4_NARROW V_MC4_NARROW(1U)
  401. #define S_MC4_SLOW 25
  402. #define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)
  403. #define F_MC4_SLOW V_MC4_SLOW(1U)
  404. #define S_MC4A_WIDTH 24
  405. #define M_MC4A_WIDTH 0x3
  406. #define V_MC4A_WIDTH(x) ((x) << S_MC4A_WIDTH)
  407. #define G_MC4A_WIDTH(x) (((x) >> S_MC4A_WIDTH) & M_MC4A_WIDTH)
  408. #define S_MC4A_SLOW 26
  409. #define V_MC4A_SLOW(x) ((x) << S_MC4A_SLOW)
  410. #define F_MC4A_SLOW V_MC4A_SLOW(1U)
  411. #define A_MC4_MODE 0x184
  412. #define S_MC4_MODE 0
  413. #define M_MC4_MODE 0x7fff
  414. #define V_MC4_MODE(x) ((x) << S_MC4_MODE)
  415. #define G_MC4_MODE(x) (((x) >> S_MC4_MODE) & M_MC4_MODE)
  416. #define A_MC4_EXT_MODE 0x188
  417. #define S_MC4_EXTENDED_MODE 0
  418. #define M_MC4_EXTENDED_MODE 0x7fff
  419. #define V_MC4_EXTENDED_MODE(x) ((x) << S_MC4_EXTENDED_MODE)
  420. #define G_MC4_EXTENDED_MODE(x) (((x) >> S_MC4_EXTENDED_MODE) & M_MC4_EXTENDED_MODE)
  421. #define A_MC4_REFRESH 0x190
  422. #define A_MC4_STROBE 0x194
  423. #define A_MC4_ECC_CNTL 0x198
  424. #define A_MC4_CE_ADDR 0x19c
  425. #define S_MC4_CE_ADDR 4
  426. #define M_MC4_CE_ADDR 0xffffff
  427. #define V_MC4_CE_ADDR(x) ((x) << S_MC4_CE_ADDR)
  428. #define G_MC4_CE_ADDR(x) (((x) >> S_MC4_CE_ADDR) & M_MC4_CE_ADDR)
  429. #define A_MC4_CE_DATA0 0x1a0
  430. #define A_MC4_CE_DATA1 0x1a4
  431. #define A_MC4_CE_DATA2 0x1a8
  432. #define A_MC4_CE_DATA3 0x1ac
  433. #define A_MC4_CE_DATA4 0x1b0
  434. #define A_MC4_UE_ADDR 0x1b4
  435. #define S_MC4_UE_ADDR 4
  436. #define M_MC4_UE_ADDR 0xffffff
  437. #define V_MC4_UE_ADDR(x) ((x) << S_MC4_UE_ADDR)
  438. #define G_MC4_UE_ADDR(x) (((x) >> S_MC4_UE_ADDR) & M_MC4_UE_ADDR)
  439. #define A_MC4_UE_DATA0 0x1b8
  440. #define A_MC4_UE_DATA1 0x1bc
  441. #define A_MC4_UE_DATA2 0x1c0
  442. #define A_MC4_UE_DATA3 0x1c4
  443. #define A_MC4_UE_DATA4 0x1c8
  444. #define A_MC4_BD_ADDR 0x1cc
  445. #define S_MC4_BACK_DOOR_ADDR 0
  446. #define M_MC4_BACK_DOOR_ADDR 0xfffffff
  447. #define V_MC4_BACK_DOOR_ADDR(x) ((x) << S_MC4_BACK_DOOR_ADDR)
  448. #define G_MC4_BACK_DOOR_ADDR(x) (((x) >> S_MC4_BACK_DOOR_ADDR) & M_MC4_BACK_DOOR_ADDR)
  449. #define A_MC4_BD_DATA0 0x1d0
  450. #define A_MC4_BD_DATA1 0x1d4
  451. #define A_MC4_BD_DATA2 0x1d8
  452. #define A_MC4_BD_DATA3 0x1dc
  453. #define A_MC4_BD_DATA4 0x1e0
  454. #define A_MC4_BD_OP 0x1e4
  455. #define S_OPERATION 0
  456. #define V_OPERATION(x) ((x) << S_OPERATION)
  457. #define F_OPERATION V_OPERATION(1U)
  458. #define A_MC4_BIST_ADDR_BEG 0x1e8
  459. #define A_MC4_BIST_ADDR_END 0x1ec
  460. #define A_MC4_BIST_DATA 0x1f0
  461. #define A_MC4_BIST_OP 0x1f4
  462. #define A_MC4_INT_ENABLE 0x1f8
  463. #define S_MC4_CORR_ERR 0
  464. #define V_MC4_CORR_ERR(x) ((x) << S_MC4_CORR_ERR)
  465. #define F_MC4_CORR_ERR V_MC4_CORR_ERR(1U)
  466. #define S_MC4_UNCORR_ERR 1
  467. #define V_MC4_UNCORR_ERR(x) ((x) << S_MC4_UNCORR_ERR)
  468. #define F_MC4_UNCORR_ERR V_MC4_UNCORR_ERR(1U)
  469. #define S_MC4_ADDR_ERR 2
  470. #define V_MC4_ADDR_ERR(x) ((x) << S_MC4_ADDR_ERR)
  471. #define F_MC4_ADDR_ERR V_MC4_ADDR_ERR(1U)
  472. #define A_MC4_INT_CAUSE 0x1fc
  473. /* TPI registers */
  474. #define A_TPI_ADDR 0x280
  475. #define S_TPI_ADDRESS 0
  476. #define M_TPI_ADDRESS 0xffffff
  477. #define V_TPI_ADDRESS(x) ((x) << S_TPI_ADDRESS)
  478. #define G_TPI_ADDRESS(x) (((x) >> S_TPI_ADDRESS) & M_TPI_ADDRESS)
  479. #define A_TPI_WR_DATA 0x284
  480. #define A_TPI_RD_DATA 0x288
  481. #define A_TPI_CSR 0x28c
  482. #define S_TPIWR 0
  483. #define V_TPIWR(x) ((x) << S_TPIWR)
  484. #define F_TPIWR V_TPIWR(1U)
  485. #define S_TPIRDY 1
  486. #define V_TPIRDY(x) ((x) << S_TPIRDY)
  487. #define F_TPIRDY V_TPIRDY(1U)
  488. #define S_INT_DIR 31
  489. #define V_INT_DIR(x) ((x) << S_INT_DIR)
  490. #define F_INT_DIR V_INT_DIR(1U)
  491. #define A_TPI_PAR 0x29c
  492. #define S_TPIPAR 0
  493. #define M_TPIPAR 0x7f
  494. #define V_TPIPAR(x) ((x) << S_TPIPAR)
  495. #define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)
  496. /* TP registers */
  497. #define A_TP_IN_CONFIG 0x300
  498. #define S_TP_IN_CSPI_TUNNEL 0
  499. #define V_TP_IN_CSPI_TUNNEL(x) ((x) << S_TP_IN_CSPI_TUNNEL)
  500. #define F_TP_IN_CSPI_TUNNEL V_TP_IN_CSPI_TUNNEL(1U)
  501. #define S_TP_IN_CSPI_ETHERNET 1
  502. #define V_TP_IN_CSPI_ETHERNET(x) ((x) << S_TP_IN_CSPI_ETHERNET)
  503. #define F_TP_IN_CSPI_ETHERNET V_TP_IN_CSPI_ETHERNET(1U)
  504. #define S_TP_IN_CSPI_CPL 3
  505. #define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)
  506. #define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U)
  507. #define S_TP_IN_CSPI_POS 4
  508. #define V_TP_IN_CSPI_POS(x) ((x) << S_TP_IN_CSPI_POS)
  509. #define F_TP_IN_CSPI_POS V_TP_IN_CSPI_POS(1U)
  510. #define S_TP_IN_CSPI_CHECK_IP_CSUM 5
  511. #define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)
  512. #define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U)
  513. #define S_TP_IN_CSPI_CHECK_TCP_CSUM 6
  514. #define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)
  515. #define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)
  516. #define S_TP_IN_ESPI_TUNNEL 7
  517. #define V_TP_IN_ESPI_TUNNEL(x) ((x) << S_TP_IN_ESPI_TUNNEL)
  518. #define F_TP_IN_ESPI_TUNNEL V_TP_IN_ESPI_TUNNEL(1U)
  519. #define S_TP_IN_ESPI_ETHERNET 8
  520. #define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)
  521. #define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U)
  522. #define S_TP_IN_ESPI_CPL 10
  523. #define V_TP_IN_ESPI_CPL(x) ((x) << S_TP_IN_ESPI_CPL)
  524. #define F_TP_IN_ESPI_CPL V_TP_IN_ESPI_CPL(1U)
  525. #define S_TP_IN_ESPI_POS 11
  526. #define V_TP_IN_ESPI_POS(x) ((x) << S_TP_IN_ESPI_POS)
  527. #define F_TP_IN_ESPI_POS V_TP_IN_ESPI_POS(1U)
  528. #define S_TP_IN_ESPI_CHECK_IP_CSUM 12
  529. #define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)
  530. #define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U)
  531. #define S_TP_IN_ESPI_CHECK_TCP_CSUM 13
  532. #define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM)
  533. #define F_TP_IN_ESPI_CHECK_TCP_CSUM V_TP_IN_ESPI_CHECK_TCP_CSUM(1U)
  534. #define S_OFFLOAD_DISABLE 14
  535. #define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE)
  536. #define F_OFFLOAD_DISABLE V_OFFLOAD_DISABLE(1U)
  537. #define A_TP_OUT_CONFIG 0x304
  538. #define S_TP_OUT_C_ETH 0
  539. #define V_TP_OUT_C_ETH(x) ((x) << S_TP_OUT_C_ETH)
  540. #define F_TP_OUT_C_ETH V_TP_OUT_C_ETH(1U)
  541. #define S_TP_OUT_CSPI_CPL 2
  542. #define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)
  543. #define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U)
  544. #define S_TP_OUT_CSPI_POS 3
  545. #define V_TP_OUT_CSPI_POS(x) ((x) << S_TP_OUT_CSPI_POS)
  546. #define F_TP_OUT_CSPI_POS V_TP_OUT_CSPI_POS(1U)
  547. #define S_TP_OUT_CSPI_GENERATE_IP_CSUM 4
  548. #define V_TP_OUT_CSPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_IP_CSUM)
  549. #define F_TP_OUT_CSPI_GENERATE_IP_CSUM V_TP_OUT_CSPI_GENERATE_IP_CSUM(1U)
  550. #define S_TP_OUT_CSPI_GENERATE_TCP_CSUM 5
  551. #define V_TP_OUT_CSPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_TCP_CSUM)
  552. #define F_TP_OUT_CSPI_GENERATE_TCP_CSUM V_TP_OUT_CSPI_GENERATE_TCP_CSUM(1U)
  553. #define S_TP_OUT_ESPI_ETHERNET 6
  554. #define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)
  555. #define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U)
  556. #define S_TP_OUT_ESPI_TAG_ETHERNET 7
  557. #define V_TP_OUT_ESPI_TAG_ETHERNET(x) ((x) << S_TP_OUT_ESPI_TAG_ETHERNET)
  558. #define F_TP_OUT_ESPI_TAG_ETHERNET V_TP_OUT_ESPI_TAG_ETHERNET(1U)
  559. #define S_TP_OUT_ESPI_CPL 8
  560. #define V_TP_OUT_ESPI_CPL(x) ((x) << S_TP_OUT_ESPI_CPL)
  561. #define F_TP_OUT_ESPI_CPL V_TP_OUT_ESPI_CPL(1U)
  562. #define S_TP_OUT_ESPI_POS 9
  563. #define V_TP_OUT_ESPI_POS(x) ((x) << S_TP_OUT_ESPI_POS)
  564. #define F_TP_OUT_ESPI_POS V_TP_OUT_ESPI_POS(1U)
  565. #define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10
  566. #define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)
  567. #define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)
  568. #define S_TP_OUT_ESPI_GENERATE_TCP_CSUM 11
  569. #define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM)
  570. #define F_TP_OUT_ESPI_GENERATE_TCP_CSUM V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U)
  571. #define A_TP_GLOBAL_CONFIG 0x308
  572. #define S_IP_TTL 0
  573. #define M_IP_TTL 0xff
  574. #define V_IP_TTL(x) ((x) << S_IP_TTL)
  575. #define G_IP_TTL(x) (((x) >> S_IP_TTL) & M_IP_TTL)
  576. #define S_TCAM_SERVER_REGION_USAGE 8
  577. #define M_TCAM_SERVER_REGION_USAGE 0x3
  578. #define V_TCAM_SERVER_REGION_USAGE(x) ((x) << S_TCAM_SERVER_REGION_USAGE)
  579. #define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE)
  580. #define S_QOS_MAPPING 10
  581. #define V_QOS_MAPPING(x) ((x) << S_QOS_MAPPING)
  582. #define F_QOS_MAPPING V_QOS_MAPPING(1U)
  583. #define S_TCP_CSUM 11
  584. #define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)
  585. #define F_TCP_CSUM V_TCP_CSUM(1U)
  586. #define S_UDP_CSUM 12
  587. #define V_UDP_CSUM(x) ((x) << S_UDP_CSUM)
  588. #define F_UDP_CSUM V_UDP_CSUM(1U)
  589. #define S_IP_CSUM 13
  590. #define V_IP_CSUM(x) ((x) << S_IP_CSUM)
  591. #define F_IP_CSUM V_IP_CSUM(1U)
  592. #define S_IP_ID_SPLIT 14
  593. #define V_IP_ID_SPLIT(x) ((x) << S_IP_ID_SPLIT)
  594. #define F_IP_ID_SPLIT V_IP_ID_SPLIT(1U)
  595. #define S_PATH_MTU 15
  596. #define V_PATH_MTU(x) ((x) << S_PATH_MTU)
  597. #define F_PATH_MTU V_PATH_MTU(1U)
  598. #define S_5TUPLE_LOOKUP 17
  599. #define M_5TUPLE_LOOKUP 0x3
  600. #define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)
  601. #define G_5TUPLE_LOOKUP(x) (((x) >> S_5TUPLE_LOOKUP) & M_5TUPLE_LOOKUP)
  602. #define S_IP_FRAGMENT_DROP 19
  603. #define V_IP_FRAGMENT_DROP(x) ((x) << S_IP_FRAGMENT_DROP)
  604. #define F_IP_FRAGMENT_DROP V_IP_FRAGMENT_DROP(1U)
  605. #define S_PING_DROP 20
  606. #define V_PING_DROP(x) ((x) << S_PING_DROP)
  607. #define F_PING_DROP V_PING_DROP(1U)
  608. #define S_PROTECT_MODE 21
  609. #define V_PROTECT_MODE(x) ((x) << S_PROTECT_MODE)
  610. #define F_PROTECT_MODE V_PROTECT_MODE(1U)
  611. #define S_SYN_COOKIE_ALGORITHM 22
  612. #define V_SYN_COOKIE_ALGORITHM(x) ((x) << S_SYN_COOKIE_ALGORITHM)
  613. #define F_SYN_COOKIE_ALGORITHM V_SYN_COOKIE_ALGORITHM(1U)
  614. #define S_ATTACK_FILTER 23
  615. #define V_ATTACK_FILTER(x) ((x) << S_ATTACK_FILTER)
  616. #define F_ATTACK_FILTER V_ATTACK_FILTER(1U)
  617. #define S_INTERFACE_TYPE 24
  618. #define V_INTERFACE_TYPE(x) ((x) << S_INTERFACE_TYPE)
  619. #define F_INTERFACE_TYPE V_INTERFACE_TYPE(1U)
  620. #define S_DISABLE_RX_FLOW_CONTROL 25
  621. #define V_DISABLE_RX_FLOW_CONTROL(x) ((x) << S_DISABLE_RX_FLOW_CONTROL)
  622. #define F_DISABLE_RX_FLOW_CONTROL V_DISABLE_RX_FLOW_CONTROL(1U)
  623. #define S_SYN_COOKIE_PARAMETER 26
  624. #define M_SYN_COOKIE_PARAMETER 0x3f
  625. #define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)
  626. #define G_SYN_COOKIE_PARAMETER(x) (((x) >> S_SYN_COOKIE_PARAMETER) & M_SYN_COOKIE_PARAMETER)
  627. #define A_TP_GLOBAL_RX_CREDITS 0x30c
  628. #define A_TP_CM_SIZE 0x310
  629. #define A_TP_CM_MM_BASE 0x314
  630. #define S_CM_MEMMGR_BASE 0
  631. #define M_CM_MEMMGR_BASE 0xfffffff
  632. #define V_CM_MEMMGR_BASE(x) ((x) << S_CM_MEMMGR_BASE)
  633. #define G_CM_MEMMGR_BASE(x) (((x) >> S_CM_MEMMGR_BASE) & M_CM_MEMMGR_BASE)
  634. #define A_TP_CM_TIMER_BASE 0x318
  635. #define S_CM_TIMER_BASE 0
  636. #define M_CM_TIMER_BASE 0xfffffff
  637. #define V_CM_TIMER_BASE(x) ((x) << S_CM_TIMER_BASE)
  638. #define G_CM_TIMER_BASE(x) (((x) >> S_CM_TIMER_BASE) & M_CM_TIMER_BASE)
  639. #define A_TP_PM_SIZE 0x31c
  640. #define A_TP_PM_TX_BASE 0x320
  641. #define A_TP_PM_DEFRAG_BASE 0x324
  642. #define A_TP_PM_RX_BASE 0x328
  643. #define A_TP_PM_RX_PG_SIZE 0x32c
  644. #define A_TP_PM_RX_MAX_PGS 0x330
  645. #define A_TP_PM_TX_PG_SIZE 0x334
  646. #define A_TP_PM_TX_MAX_PGS 0x338
  647. #define A_TP_TCP_OPTIONS 0x340
  648. #define S_TIMESTAMP 0
  649. #define M_TIMESTAMP 0x3
  650. #define V_TIMESTAMP(x) ((x) << S_TIMESTAMP)
  651. #define G_TIMESTAMP(x) (((x) >> S_TIMESTAMP) & M_TIMESTAMP)
  652. #define S_WINDOW_SCALE 2
  653. #define M_WINDOW_SCALE 0x3
  654. #define V_WINDOW_SCALE(x) ((x) << S_WINDOW_SCALE)
  655. #define G_WINDOW_SCALE(x) (((x) >> S_WINDOW_SCALE) & M_WINDOW_SCALE)
  656. #define S_SACK 4
  657. #define M_SACK 0x3
  658. #define V_SACK(x) ((x) << S_SACK)
  659. #define G_SACK(x) (((x) >> S_SACK) & M_SACK)
  660. #define S_ECN 6
  661. #define M_ECN 0x3
  662. #define V_ECN(x) ((x) << S_ECN)
  663. #define G_ECN(x) (((x) >> S_ECN) & M_ECN)
  664. #define S_SACK_ALGORITHM 8
  665. #define M_SACK_ALGORITHM 0x3
  666. #define V_SACK_ALGORITHM(x) ((x) << S_SACK_ALGORITHM)
  667. #define G_SACK_ALGORITHM(x) (((x) >> S_SACK_ALGORITHM) & M_SACK_ALGORITHM)
  668. #define S_MSS 10
  669. #define V_MSS(x) ((x) << S_MSS)
  670. #define F_MSS V_MSS(1U)
  671. #define S_DEFAULT_PEER_MSS 16
  672. #define M_DEFAULT_PEER_MSS 0xffff
  673. #define V_DEFAULT_PEER_MSS(x) ((x) << S_DEFAULT_PEER_MSS)
  674. #define G_DEFAULT_PEER_MSS(x) (((x) >> S_DEFAULT_PEER_MSS) & M_DEFAULT_PEER_MSS)
  675. #define A_TP_DACK_CONFIG 0x344
  676. #define S_DACK_MODE 0
  677. #define V_DACK_MODE(x) ((x) << S_DACK_MODE)
  678. #define F_DACK_MODE V_DACK_MODE(1U)
  679. #define S_DACK_AUTO_MGMT 1
  680. #define V_DACK_AUTO_MGMT(x) ((x) << S_DACK_AUTO_MGMT)
  681. #define F_DACK_AUTO_MGMT V_DACK_AUTO_MGMT(1U)
  682. #define S_DACK_AUTO_CAREFUL 2
  683. #define V_DACK_AUTO_CAREFUL(x) ((x) << S_DACK_AUTO_CAREFUL)
  684. #define F_DACK_AUTO_CAREFUL V_DACK_AUTO_CAREFUL(1U)
  685. #define S_DACK_MSS_SELECTOR 3
  686. #define M_DACK_MSS_SELECTOR 0x3
  687. #define V_DACK_MSS_SELECTOR(x) ((x) << S_DACK_MSS_SELECTOR)
  688. #define G_DACK_MSS_SELECTOR(x) (((x) >> S_DACK_MSS_SELECTOR) & M_DACK_MSS_SELECTOR)
  689. #define S_DACK_BYTE_THRESHOLD 5
  690. #define M_DACK_BYTE_THRESHOLD 0xfffff
  691. #define V_DACK_BYTE_THRESHOLD(x) ((x) << S_DACK_BYTE_THRESHOLD)
  692. #define G_DACK_BYTE_THRESHOLD(x) (((x) >> S_DACK_BYTE_THRESHOLD) & M_DACK_BYTE_THRESHOLD)
  693. #define A_TP_PC_CONFIG 0x348
  694. #define S_TP_ACCESS_LATENCY 0
  695. #define M_TP_ACCESS_LATENCY 0xf
  696. #define V_TP_ACCESS_LATENCY(x) ((x) << S_TP_ACCESS_LATENCY)
  697. #define G_TP_ACCESS_LATENCY(x) (((x) >> S_TP_ACCESS_LATENCY) & M_TP_ACCESS_LATENCY)
  698. #define S_HELD_FIN_DISABLE 4
  699. #define V_HELD_FIN_DISABLE(x) ((x) << S_HELD_FIN_DISABLE)
  700. #define F_HELD_FIN_DISABLE V_HELD_FIN_DISABLE(1U)
  701. #define S_DDP_FC_ENABLE 5
  702. #define V_DDP_FC_ENABLE(x) ((x) << S_DDP_FC_ENABLE)
  703. #define F_DDP_FC_ENABLE V_DDP_FC_ENABLE(1U)
  704. #define S_RDMA_ERR_ENABLE 6
  705. #define V_RDMA_ERR_ENABLE(x) ((x) << S_RDMA_ERR_ENABLE)
  706. #define F_RDMA_ERR_ENABLE V_RDMA_ERR_ENABLE(1U)
  707. #define S_FAST_PDU_DELIVERY 7
  708. #define V_FAST_PDU_DELIVERY(x) ((x) << S_FAST_PDU_DELIVERY)
  709. #define F_FAST_PDU_DELIVERY V_FAST_PDU_DELIVERY(1U)
  710. #define S_CLEAR_FIN 8
  711. #define V_CLEAR_FIN(x) ((x) << S_CLEAR_FIN)
  712. #define F_CLEAR_FIN V_CLEAR_FIN(1U)
  713. #define S_DIS_TX_FILL_WIN_PUSH 12
  714. #define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH)
  715. #define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U)
  716. #define S_TP_PC_REV 30
  717. #define M_TP_PC_REV 0x3
  718. #define V_TP_PC_REV(x) ((x) << S_TP_PC_REV)
  719. #define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)
  720. #define A_TP_BACKOFF0 0x350
  721. #define S_ELEMENT0 0
  722. #define M_ELEMENT0 0xff
  723. #define V_ELEMENT0(x) ((x) << S_ELEMENT0)
  724. #define G_ELEMENT0(x) (((x) >> S_ELEMENT0) & M_ELEMENT0)
  725. #define S_ELEMENT1 8
  726. #define M_ELEMENT1 0xff
  727. #define V_ELEMENT1(x) ((x) << S_ELEMENT1)
  728. #define G_ELEMENT1(x) (((x) >> S_ELEMENT1) & M_ELEMENT1)
  729. #define S_ELEMENT2 16
  730. #define M_ELEMENT2 0xff
  731. #define V_ELEMENT2(x) ((x) << S_ELEMENT2)
  732. #define G_ELEMENT2(x) (((x) >> S_ELEMENT2) & M_ELEMENT2)
  733. #define S_ELEMENT3 24
  734. #define M_ELEMENT3 0xff
  735. #define V_ELEMENT3(x) ((x) << S_ELEMENT3)
  736. #define G_ELEMENT3(x) (((x) >> S_ELEMENT3) & M_ELEMENT3)
  737. #define A_TP_BACKOFF1 0x354
  738. #define A_TP_BACKOFF2 0x358
  739. #define A_TP_BACKOFF3 0x35c
  740. #define A_TP_PARA_REG0 0x360
  741. #define S_VAR_MULT 0
  742. #define M_VAR_MULT 0xf
  743. #define V_VAR_MULT(x) ((x) << S_VAR_MULT)
  744. #define G_VAR_MULT(x) (((x) >> S_VAR_MULT) & M_VAR_MULT)
  745. #define S_VAR_GAIN 4
  746. #define M_VAR_GAIN 0xf
  747. #define V_VAR_GAIN(x) ((x) << S_VAR_GAIN)
  748. #define G_VAR_GAIN(x) (((x) >> S_VAR_GAIN) & M_VAR_GAIN)
  749. #define S_SRTT_GAIN 8
  750. #define M_SRTT_GAIN 0xf
  751. #define V_SRTT_GAIN(x) ((x) << S_SRTT_GAIN)
  752. #define G_SRTT_GAIN(x) (((x) >> S_SRTT_GAIN) & M_SRTT_GAIN)
  753. #define S_RTTVAR_INIT 12
  754. #define M_RTTVAR_INIT 0xf
  755. #define V_RTTVAR_INIT(x) ((x) << S_RTTVAR_INIT)
  756. #define G_RTTVAR_INIT(x) (((x) >> S_RTTVAR_INIT) & M_RTTVAR_INIT)
  757. #define S_DUP_THRESH 20
  758. #define M_DUP_THRESH 0xf
  759. #define V_DUP_THRESH(x) ((x) << S_DUP_THRESH)
  760. #define G_DUP_THRESH(x) (((x) >> S_DUP_THRESH) & M_DUP_THRESH)
  761. #define S_INIT_CONG_WIN 24
  762. #define M_INIT_CONG_WIN 0x7
  763. #define V_INIT_CONG_WIN(x) ((x) << S_INIT_CONG_WIN)
  764. #define G_INIT_CONG_WIN(x) (((x) >> S_INIT_CONG_WIN) & M_INIT_CONG_WIN)
  765. #define A_TP_PARA_REG1 0x364
  766. #define S_INITIAL_SLOW_START_THRESHOLD 0
  767. #define M_INITIAL_SLOW_START_THRESHOLD 0xffff
  768. #define V_INITIAL_SLOW_START_THRESHOLD(x) ((x) << S_INITIAL_SLOW_START_THRESHOLD)
  769. #define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD)
  770. #define S_RECEIVE_BUFFER_SIZE 16
  771. #define M_RECEIVE_BUFFER_SIZE 0xffff
  772. #define V_RECEIVE_BUFFER_SIZE(x) ((x) << S_RECEIVE_BUFFER_SIZE)
  773. #define G_RECEIVE_BUFFER_SIZE(x) (((x) >> S_RECEIVE_BUFFER_SIZE) & M_RECEIVE_BUFFER_SIZE)
  774. #define A_TP_PARA_REG2 0x368
  775. #define S_RX_COALESCE_SIZE 0
  776. #define M_RX_COALESCE_SIZE 0xffff
  777. #define V_RX_COALESCE_SIZE(x) ((x) << S_RX_COALESCE_SIZE)
  778. #define G_RX_COALESCE_SIZE(x) (((x) >> S_RX_COALESCE_SIZE) & M_RX_COALESCE_SIZE)
  779. #define S_MAX_RX_SIZE 16
  780. #define M_MAX_RX_SIZE 0xffff
  781. #define V_MAX_RX_SIZE(x) ((x) << S_MAX_RX_SIZE)
  782. #define G_MAX_RX_SIZE(x) (((x) >> S_MAX_RX_SIZE) & M_MAX_RX_SIZE)
  783. #define A_TP_PARA_REG3 0x36c
  784. #define S_RX_COALESCING_PSH_DELIVER 0
  785. #define V_RX_COALESCING_PSH_DELIVER(x) ((x) << S_RX_COALESCING_PSH_DELIVER)
  786. #define F_RX_COALESCING_PSH_DELIVER V_RX_COALESCING_PSH_DELIVER(1U)
  787. #define S_RX_COALESCING_ENABLE 1
  788. #define V_RX_COALESCING_ENABLE(x) ((x) << S_RX_COALESCING_ENABLE)
  789. #define F_RX_COALESCING_ENABLE V_RX_COALESCING_ENABLE(1U)
  790. #define S_TAHOE_ENABLE 2
  791. #define V_TAHOE_ENABLE(x) ((x) << S_TAHOE_ENABLE)
  792. #define F_TAHOE_ENABLE V_TAHOE_ENABLE(1U)
  793. #define S_MAX_REORDER_FRAGMENTS 12
  794. #define M_MAX_REORDER_FRAGMENTS 0x7
  795. #define V_MAX_REORDER_FRAGMENTS(x) ((x) << S_MAX_REORDER_FRAGMENTS)
  796. #define G_MAX_REORDER_FRAGMENTS(x) (((x) >> S_MAX_REORDER_FRAGMENTS) & M_MAX_REORDER_FRAGMENTS)
  797. #define A_TP_TIMER_RESOLUTION 0x390
  798. #define S_DELAYED_ACK_TIMER_RESOLUTION 0
  799. #define M_DELAYED_ACK_TIMER_RESOLUTION 0x3f
  800. #define V_DELAYED_ACK_TIMER_RESOLUTION(x) ((x) << S_DELAYED_ACK_TIMER_RESOLUTION)
  801. #define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION)
  802. #define S_GENERIC_TIMER_RESOLUTION 16
  803. #define M_GENERIC_TIMER_RESOLUTION 0x3f
  804. #define V_GENERIC_TIMER_RESOLUTION(x) ((x) << S_GENERIC_TIMER_RESOLUTION)
  805. #define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION)
  806. #define A_TP_2MSL 0x394
  807. #define S_2MSL 0
  808. #define M_2MSL 0x3fffffff
  809. #define V_2MSL(x) ((x) << S_2MSL)
  810. #define G_2MSL(x) (((x) >> S_2MSL) & M_2MSL)
  811. #define A_TP_RXT_MIN 0x398
  812. #define S_RETRANSMIT_TIMER_MIN 0
  813. #define M_RETRANSMIT_TIMER_MIN 0xffff
  814. #define V_RETRANSMIT_TIMER_MIN(x) ((x) << S_RETRANSMIT_TIMER_MIN)
  815. #define G_RETRANSMIT_TIMER_MIN(x) (((x) >> S_RETRANSMIT_TIMER_MIN) & M_RETRANSMIT_TIMER_MIN)
  816. #define A_TP_RXT_MAX 0x39c
  817. #define S_RETRANSMIT_TIMER_MAX 0
  818. #define M_RETRANSMIT_TIMER_MAX 0x3fffffff
  819. #define V_RETRANSMIT_TIMER_MAX(x) ((x) << S_RETRANSMIT_TIMER_MAX)
  820. #define G_RETRANSMIT_TIMER_MAX(x) (((x) >> S_RETRANSMIT_TIMER_MAX) & M_RETRANSMIT_TIMER_MAX)
  821. #define A_TP_PERS_MIN 0x3a0
  822. #define S_PERSIST_TIMER_MIN 0
  823. #define M_PERSIST_TIMER_MIN 0xffff
  824. #define V_PERSIST_TIMER_MIN(x) ((x) << S_PERSIST_TIMER_MIN)
  825. #define G_PERSIST_TIMER_MIN(x) (((x) >> S_PERSIST_TIMER_MIN) & M_PERSIST_TIMER_MIN)
  826. #define A_TP_PERS_MAX 0x3a4
  827. #define S_PERSIST_TIMER_MAX 0
  828. #define M_PERSIST_TIMER_MAX 0x3fffffff
  829. #define V_PERSIST_TIMER_MAX(x) ((x) << S_PERSIST_TIMER_MAX)
  830. #define G_PERSIST_TIMER_MAX(x) (((x) >> S_PERSIST_TIMER_MAX) & M_PERSIST_TIMER_MAX)
  831. #define A_TP_KEEP_IDLE 0x3ac
  832. #define S_KEEP_ALIVE_IDLE_TIME 0
  833. #define M_KEEP_ALIVE_IDLE_TIME 0x3fffffff
  834. #define V_KEEP_ALIVE_IDLE_TIME(x) ((x) << S_KEEP_ALIVE_IDLE_TIME)
  835. #define G_KEEP_ALIVE_IDLE_TIME(x) (((x) >> S_KEEP_ALIVE_IDLE_TIME) & M_KEEP_ALIVE_IDLE_TIME)
  836. #define A_TP_KEEP_INTVL 0x3b0
  837. #define S_KEEP_ALIVE_INTERVAL_TIME 0
  838. #define M_KEEP_ALIVE_INTERVAL_TIME 0x3fffffff
  839. #define V_KEEP_ALIVE_INTERVAL_TIME(x) ((x) << S_KEEP_ALIVE_INTERVAL_TIME)
  840. #define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME)
  841. #define A_TP_INIT_SRTT 0x3b4
  842. #define S_INITIAL_SRTT 0
  843. #define M_INITIAL_SRTT 0xffff
  844. #define V_INITIAL_SRTT(x) ((x) << S_INITIAL_SRTT)
  845. #define G_INITIAL_SRTT(x) (((x) >> S_INITIAL_SRTT) & M_INITIAL_SRTT)
  846. #define A_TP_DACK_TIME 0x3b8
  847. #define S_DELAYED_ACK_TIME 0
  848. #define M_DELAYED_ACK_TIME 0x7ff
  849. #define V_DELAYED_ACK_TIME(x) ((x) << S_DELAYED_ACK_TIME)
  850. #define G_DELAYED_ACK_TIME(x) (((x) >> S_DELAYED_ACK_TIME) & M_DELAYED_ACK_TIME)
  851. #define A_TP_FINWAIT2_TIME 0x3bc
  852. #define S_FINWAIT2_TIME 0
  853. #define M_FINWAIT2_TIME 0x3fffffff
  854. #define V_FINWAIT2_TIME(x) ((x) << S_FINWAIT2_TIME)
  855. #define G_FINWAIT2_TIME(x) (((x) >> S_FINWAIT2_TIME) & M_FINWAIT2_TIME)
  856. #define A_TP_FAST_FINWAIT2_TIME 0x3c0
  857. #define S_FAST_FINWAIT2_TIME 0
  858. #define M_FAST_FINWAIT2_TIME 0x3fffffff
  859. #define V_FAST_FINWAIT2_TIME(x) ((x) << S_FAST_FINWAIT2_TIME)
  860. #define G_FAST_FINWAIT2_TIME(x) (((x) >> S_FAST_FINWAIT2_TIME) & M_FAST_FINWAIT2_TIME)
  861. #define A_TP_SHIFT_CNT 0x3c4
  862. #define S_KEEPALIVE_MAX 0
  863. #define M_KEEPALIVE_MAX 0xff
  864. #define V_KEEPALIVE_MAX(x) ((x) << S_KEEPALIVE_MAX)
  865. #define G_KEEPALIVE_MAX(x) (((x) >> S_KEEPALIVE_MAX) & M_KEEPALIVE_MAX)
  866. #define S_WINDOWPROBE_MAX 8
  867. #define M_WINDOWPROBE_MAX 0xff
  868. #define V_WINDOWPROBE_MAX(x) ((x) << S_WINDOWPROBE_MAX)
  869. #define G_WINDOWPROBE_MAX(x) (((x) >> S_WINDOWPROBE_MAX) & M_WINDOWPROBE_MAX)
  870. #define S_RETRANSMISSION_MAX 16
  871. #define M_RETRANSMISSION_MAX 0xff
  872. #define V_RETRANSMISSION_MAX(x) ((x) << S_RETRANSMISSION_MAX)
  873. #define G_RETRANSMISSION_MAX(x) (((x) >> S_RETRANSMISSION_MAX) & M_RETRANSMISSION_MAX)
  874. #define S_SYN_MAX 24
  875. #define M_SYN_MAX 0xff
  876. #define V_SYN_MAX(x) ((x) << S_SYN_MAX)
  877. #define G_SYN_MAX(x) (((x) >> S_SYN_MAX) & M_SYN_MAX)
  878. #define A_TP_QOS_REG0 0x3e0
  879. #define S_L3_VALUE 0
  880. #define M_L3_VALUE 0x3f
  881. #define V_L3_VALUE(x) ((x) << S_L3_VALUE)
  882. #define G_L3_VALUE(x) (((x) >> S_L3_VALUE) & M_L3_VALUE)
  883. #define A_TP_QOS_REG1 0x3e4
  884. #define A_TP_QOS_REG2 0x3e8
  885. #define A_TP_QOS_REG3 0x3ec
  886. #define A_TP_QOS_REG4 0x3f0
  887. #define A_TP_QOS_REG5 0x3f4
  888. #define A_TP_QOS_REG6 0x3f8
  889. #define A_TP_QOS_REG7 0x3fc
  890. #define A_TP_MTU_REG0 0x404
  891. #define A_TP_MTU_REG1 0x408
  892. #define A_TP_MTU_REG2 0x40c
  893. #define A_TP_MTU_REG3 0x410
  894. #define A_TP_MTU_REG4 0x414
  895. #define A_TP_MTU_REG5 0x418
  896. #define A_TP_MTU_REG6 0x41c
  897. #define A_TP_MTU_REG7 0x420
  898. #define A_TP_RESET 0x44c
  899. #define S_TP_RESET 0
  900. #define V_TP_RESET(x) ((x) << S_TP_RESET)
  901. #define F_TP_RESET V_TP_RESET(1U)
  902. #define S_CM_MEMMGR_INIT 1
  903. #define V_CM_MEMMGR_INIT(x) ((x) << S_CM_MEMMGR_INIT)
  904. #define F_CM_MEMMGR_INIT V_CM_MEMMGR_INIT(1U)
  905. #define A_TP_MIB_INDEX 0x450
  906. #define A_TP_MIB_DATA 0x454
  907. #define A_TP_SYNC_TIME_HI 0x458
  908. #define A_TP_SYNC_TIME_LO 0x45c
  909. #define A_TP_CM_MM_RX_FLST_BASE 0x460
  910. #define S_CM_MEMMGR_RX_FREE_LIST_BASE 0
  911. #define M_CM_MEMMGR_RX_FREE_LIST_BASE 0xfffffff
  912. #define V_CM_MEMMGR_RX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_RX_FREE_LIST_BASE)
  913. #define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE)
  914. #define A_TP_CM_MM_TX_FLST_BASE 0x464
  915. #define S_CM_MEMMGR_TX_FREE_LIST_BASE 0
  916. #define M_CM_MEMMGR_TX_FREE_LIST_BASE 0xfffffff
  917. #define V_CM_MEMMGR_TX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_TX_FREE_LIST_BASE)
  918. #define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE)
  919. #define A_TP_CM_MM_P_FLST_BASE 0x468
  920. #define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0
  921. #define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0xfffffff
  922. #define V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
  923. #define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
  924. #define A_TP_CM_MM_MAX_P 0x46c
  925. #define S_CM_MEMMGR_MAX_PSTRUCT 0
  926. #define M_CM_MEMMGR_MAX_PSTRUCT 0xfffffff
  927. #define V_CM_MEMMGR_MAX_PSTRUCT(x) ((x) << S_CM_MEMMGR_MAX_PSTRUCT)
  928. #define G_CM_MEMMGR_MAX_PSTRUCT(x) (((x) >> S_CM_MEMMGR_MAX_PSTRUCT) & M_CM_MEMMGR_MAX_PSTRUCT)
  929. #define A_TP_INT_ENABLE 0x470
  930. #define S_TX_FREE_LIST_EMPTY 0
  931. #define V_TX_FREE_LIST_EMPTY(x) ((x) << S_TX_FREE_LIST_EMPTY)
  932. #define F_TX_FREE_LIST_EMPTY V_TX_FREE_LIST_EMPTY(1U)
  933. #define S_RX_FREE_LIST_EMPTY 1
  934. #define V_RX_FREE_LIST_EMPTY(x) ((x) << S_RX_FREE_LIST_EMPTY)
  935. #define F_RX_FREE_LIST_EMPTY V_RX_FREE_LIST_EMPTY(1U)
  936. #define A_TP_INT_CAUSE 0x474
  937. #define A_TP_TIMER_SEPARATOR 0x4a4
  938. #define S_DISABLE_PAST_TIMER_INSERTION 0
  939. #define V_DISABLE_PAST_TIMER_INSERTION(x) ((x) << S_DISABLE_PAST_TIMER_INSERTION)
  940. #define F_DISABLE_PAST_TIMER_INSERTION V_DISABLE_PAST_TIMER_INSERTION(1U)
  941. #define S_MODULATION_TIMER_SEPARATOR 1
  942. #define M_MODULATION_TIMER_SEPARATOR 0x7fff
  943. #define V_MODULATION_TIMER_SEPARATOR(x) ((x) << S_MODULATION_TIMER_SEPARATOR)
  944. #define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR)
  945. #define S_GLOBAL_TIMER_SEPARATOR 16
  946. #define M_GLOBAL_TIMER_SEPARATOR 0xffff
  947. #define V_GLOBAL_TIMER_SEPARATOR(x) ((x) << S_GLOBAL_TIMER_SEPARATOR)
  948. #define G_GLOBAL_TIMER_SEPARATOR(x) (((x) >> S_GLOBAL_TIMER_SEPARATOR) & M_GLOBAL_TIMER_SEPARATOR)
  949. #define A_TP_CM_FC_MODE 0x4b0
  950. #define A_TP_PC_CONGESTION_CNTL 0x4b4
  951. #define A_TP_TX_DROP_CONFIG 0x4b8
  952. #define S_ENABLE_TX_DROP 31
  953. #define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP)
  954. #define F_ENABLE_TX_DROP V_ENABLE_TX_DROP(1U)
  955. #define S_ENABLE_TX_ERROR 30
  956. #define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR)
  957. #define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U)
  958. #define S_DROP_TICKS_CNT 4
  959. #define M_DROP_TICKS_CNT 0x3ffffff
  960. #define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)
  961. #define G_DROP_TICKS_CNT(x) (((x) >> S_DROP_TICKS_CNT) & M_DROP_TICKS_CNT)
  962. #define S_NUM_PKTS_DROPPED 0
  963. #define M_NUM_PKTS_DROPPED 0xf
  964. #define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)
  965. #define G_NUM_PKTS_DROPPED(x) (((x) >> S_NUM_PKTS_DROPPED) & M_NUM_PKTS_DROPPED)
  966. #define A_TP_TX_DROP_COUNT 0x4bc
  967. /* RAT registers */
  968. #define A_RAT_ROUTE_CONTROL 0x580
  969. #define S_USE_ROUTE_TABLE 0
  970. #define V_USE_ROUTE_TABLE(x) ((x) << S_USE_ROUTE_TABLE)
  971. #define F_USE_ROUTE_TABLE V_USE_ROUTE_TABLE(1U)
  972. #define S_ENABLE_CSPI 1
  973. #define V_ENABLE_CSPI(x) ((x) << S_ENABLE_CSPI)
  974. #define F_ENABLE_CSPI V_ENABLE_CSPI(1U)
  975. #define S_ENABLE_PCIX 2
  976. #define V_ENABLE_PCIX(x) ((x) << S_ENABLE_PCIX)
  977. #define F_ENABLE_PCIX V_ENABLE_PCIX(1U)
  978. #define A_RAT_ROUTE_TABLE_INDEX 0x584
  979. #define S_ROUTE_TABLE_INDEX 0
  980. #define M_ROUTE_TABLE_INDEX 0xf
  981. #define V_ROUTE_TABLE_INDEX(x) ((x) << S_ROUTE_TABLE_INDEX)
  982. #define G_ROUTE_TABLE_INDEX(x) (((x) >> S_ROUTE_TABLE_INDEX) & M_ROUTE_TABLE_INDEX)
  983. #define A_RAT_ROUTE_TABLE_DATA 0x588
  984. #define A_RAT_NO_ROUTE 0x58c
  985. #define S_CPL_OPCODE 0
  986. #define M_CPL_OPCODE 0xff
  987. #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
  988. #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & M_CPL_OPCODE)
  989. #define A_RAT_INTR_ENABLE 0x590
  990. #define S_ZEROROUTEERROR 0
  991. #define V_ZEROROUTEERROR(x) ((x) << S_ZEROROUTEERROR)
  992. #define F_ZEROROUTEERROR V_ZEROROUTEERROR(1U)
  993. #define S_CSPIFRAMINGERROR 1
  994. #define V_CSPIFRAMINGERROR(x) ((x) << S_CSPIFRAMINGERROR)
  995. #define F_CSPIFRAMINGERROR V_CSPIFRAMINGERROR(1U)
  996. #define S_SGEFRAMINGERROR 2
  997. #define V_SGEFRAMINGERROR(x) ((x) << S_SGEFRAMINGERROR)
  998. #define F_SGEFRAMINGERROR V_SGEFRAMINGERROR(1U)
  999. #define S_TPFRAMINGERROR 3
  1000. #define V_TPFRAMINGERROR(x) ((x) << S_TPFRAMINGERROR)
  1001. #define F_TPFRAMINGERROR V_TPFRAMINGERROR(1U)
  1002. #define A_RAT_INTR_CAUSE 0x594
  1003. /* CSPI registers */
  1004. #define A_CSPI_RX_AE_WM 0x810
  1005. #define A_CSPI_RX_AF_WM 0x814
  1006. #define A_CSPI_CALENDAR_LEN 0x818
  1007. #define S_CALENDARLENGTH 0
  1008. #define M_CALENDARLENGTH 0xffff
  1009. #define V_CALENDARLENGTH(x) ((x) << S_CALENDARLENGTH)
  1010. #define G_CALENDARLENGTH(x) (((x) >> S_CALENDARLENGTH) & M_CALENDARLENGTH)
  1011. #define A_CSPI_FIFO_STATUS_ENABLE 0x820
  1012. #define S_FIFOSTATUSENABLE 0
  1013. #define V_FIFOSTATUSENABLE(x) ((x) << S_FIFOSTATUSENABLE)
  1014. #define F_FIFOSTATUSENABLE V_FIFOSTATUSENABLE(1U)
  1015. #define A_CSPI_MAXBURST1_MAXBURST2 0x828
  1016. #define S_MAXBURST1 0
  1017. #define M_MAXBURST1 0xffff
  1018. #define V_MAXBURST1(x) ((x) << S_MAXBURST1)
  1019. #define G_MAXBURST1(x) (((x) >> S_MAXBURST1) & M_MAXBURST1)
  1020. #define S_MAXBURST2 16
  1021. #define M_MAXBURST2 0xffff
  1022. #define V_MAXBURST2(x) ((x) << S_MAXBURST2)
  1023. #define G_MAXBURST2(x) (((x) >> S_MAXBURST2) & M_MAXBURST2)
  1024. #define A_CSPI_TRAIN 0x82c
  1025. #define S_CSPI_TRAIN_ALPHA 0
  1026. #define M_CSPI_TRAIN_ALPHA 0xffff
  1027. #define V_CSPI_TRAIN_ALPHA(x) ((x) << S_CSPI_TRAIN_ALPHA)
  1028. #define G_CSPI_TRAIN_ALPHA(x) (((x) >> S_CSPI_TRAIN_ALPHA) & M_CSPI_TRAIN_ALPHA)
  1029. #define S_CSPI_TRAIN_DATA_MAXT 16
  1030. #define M_CSPI_TRAIN_DATA_MAXT 0xffff
  1031. #define V_CSPI_TRAIN_DATA_MAXT(x) ((x) << S_CSPI_TRAIN_DATA_MAXT)
  1032. #define G_CSPI_TRAIN_DATA_MAXT(x) (((x) >> S_CSPI_TRAIN_DATA_MAXT) & M_CSPI_TRAIN_DATA_MAXT)
  1033. #define A_CSPI_INTR_STATUS 0x848
  1034. #define S_DIP4ERR 0
  1035. #define V_DIP4ERR(x) ((x) << S_DIP4ERR)
  1036. #define F_DIP4ERR V_DIP4ERR(1U)
  1037. #define S_RXDROP 1
  1038. #define V_RXDROP(x) ((x) << S_RXDROP)
  1039. #define F_RXDROP V_RXDROP(1U)
  1040. #define S_TXDROP 2
  1041. #define V_TXDROP(x) ((x) << S_TXDROP)
  1042. #define F_TXDROP V_TXDROP(1U)
  1043. #define S_RXOVERFLOW 3
  1044. #define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW)
  1045. #define F_RXOVERFLOW V_RXOVERFLOW(1U)
  1046. #define S_RAMPARITYERR 4
  1047. #define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)
  1048. #define F_RAMPARITYERR V_RAMPARITYERR(1U)
  1049. #define A_CSPI_INTR_ENABLE 0x84c
  1050. /* ESPI registers */
  1051. #define A_ESPI_SCH_TOKEN0 0x880
  1052. #define S_SCHTOKEN0 0
  1053. #define M_SCHTOKEN0 0xffff
  1054. #define V_SCHTOKEN0(x) ((x) << S_SCHTOKEN0)
  1055. #define G_SCHTOKEN0(x) (((x) >> S_SCHTOKEN0) & M_SCHTOKEN0)
  1056. #define A_ESPI_SCH_TOKEN1 0x884
  1057. #define S_SCHTOKEN1 0
  1058. #define M_SCHTOKEN1 0xffff
  1059. #define V_SCHTOKEN1(x) ((x) << S_SCHTOKEN1)
  1060. #define G_SCHTOKEN1(x) (((x) >> S_SCHTOKEN1) & M_SCHTOKEN1)
  1061. #define A_ESPI_SCH_TOKEN2 0x888
  1062. #define S_SCHTOKEN2 0
  1063. #define M_SCHTOKEN2 0xffff
  1064. #define V_SCHTOKEN2(x) ((x) << S_SCHTOKEN2)
  1065. #define G_SCHTOKEN2(x) (((x) >> S_SCHTOKEN2) & M_SCHTOKEN2)
  1066. #define A_ESPI_SCH_TOKEN3 0x88c
  1067. #define S_SCHTOKEN3 0
  1068. #define M_SCHTOKEN3 0xffff
  1069. #define V_SCHTOKEN3(x) ((x) << S_SCHTOKEN3)
  1070. #define G_SCHTOKEN3(x) (((x) >> S_SCHTOKEN3) & M_SCHTOKEN3)
  1071. #define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
  1072. #define S_ALMOSTEMPTY 0
  1073. #define M_ALMOSTEMPTY 0xffff
  1074. #define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
  1075. #define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
  1076. #define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
  1077. #define S_ALMOSTFULL 0
  1078. #define M_ALMOSTFULL 0xffff
  1079. #define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
  1080. #define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
  1081. #define A_ESPI_CALENDAR_LENGTH 0x898
  1082. #define A_PORT_CONFIG 0x89c
  1083. #define S_RX_NPORTS 0
  1084. #define M_RX_NPORTS 0xff
  1085. #define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)
  1086. #define G_RX_NPORTS(x) (((x) >> S_RX_NPORTS) & M_RX_NPORTS)
  1087. #define S_TX_NPORTS 8
  1088. #define M_TX_NPORTS 0xff
  1089. #define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)
  1090. #define G_TX_NPORTS(x) (((x) >> S_TX_NPORTS) & M_TX_NPORTS)
  1091. #define A_ESPI_FIFO_STATUS_ENABLE 0x8a0
  1092. #define S_RXSTATUSENABLE 0
  1093. #define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)
  1094. #define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U)
  1095. #define S_TXDROPENABLE 1
  1096. #define V_TXDROPENABLE(x) ((x) << S_TXDROPENABLE)
  1097. #define F_TXDROPENABLE V_TXDROPENABLE(1U)
  1098. #define S_RXENDIANMODE 2
  1099. #define V_RXENDIANMODE(x) ((x) << S_RXENDIANMODE)
  1100. #define F_RXENDIANMODE V_RXENDI