/drivers/net/chelsio/regs.h
C Header | 2168 lines | 1601 code | 518 blank | 49 comment | 0 complexity | c4f2d68e17dbbc62535cec8cc6b61bfa MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
Large files files are truncated, but you can click here to view the full file
1/*****************************************************************************
2 * *
3 * File: regs.h *
4 * $Revision: 1.8 $ *
5 * $Date: 2005/06/21 18:29:48 $ *
6 * Description: *
7 * part of the Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
38
39#ifndef _CXGB_REGS_H_
40#define _CXGB_REGS_H_
41
42/* SGE registers */
43#define A_SG_CONTROL 0x0
44
45#define S_CMDQ0_ENABLE 0
46#define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)
47#define F_CMDQ0_ENABLE V_CMDQ0_ENABLE(1U)
48
49#define S_CMDQ1_ENABLE 1
50#define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)
51#define F_CMDQ1_ENABLE V_CMDQ1_ENABLE(1U)
52
53#define S_FL0_ENABLE 2
54#define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)
55#define F_FL0_ENABLE V_FL0_ENABLE(1U)
56
57#define S_FL1_ENABLE 3
58#define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)
59#define F_FL1_ENABLE V_FL1_ENABLE(1U)
60
61#define S_CPL_ENABLE 4
62#define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)
63#define F_CPL_ENABLE V_CPL_ENABLE(1U)
64
65#define S_RESPONSE_QUEUE_ENABLE 5
66#define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)
67#define F_RESPONSE_QUEUE_ENABLE V_RESPONSE_QUEUE_ENABLE(1U)
68
69#define S_CMDQ_PRIORITY 6
70#define M_CMDQ_PRIORITY 0x3
71#define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)
72#define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)
73
74#define S_DISABLE_CMDQ0_GTS 8
75#define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS)
76#define F_DISABLE_CMDQ0_GTS V_DISABLE_CMDQ0_GTS(1U)
77
78#define S_DISABLE_CMDQ1_GTS 9
79#define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)
80#define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U)
81
82#define S_DISABLE_FL0_GTS 10
83#define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS)
84#define F_DISABLE_FL0_GTS V_DISABLE_FL0_GTS(1U)
85
86#define S_DISABLE_FL1_GTS 11
87#define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS)
88#define F_DISABLE_FL1_GTS V_DISABLE_FL1_GTS(1U)
89
90#define S_ENABLE_BIG_ENDIAN 12
91#define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)
92#define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U)
93
94#define S_FL_SELECTION_CRITERIA 13
95#define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA)
96#define F_FL_SELECTION_CRITERIA V_FL_SELECTION_CRITERIA(1U)
97
98#define S_ISCSI_COALESCE 14
99#define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)
100#define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U)
101
102#define S_RX_PKT_OFFSET 15
103#define M_RX_PKT_OFFSET 0x7
104#define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)
105#define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET)
106
107#define S_VLAN_XTRACT 18
108#define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)
109#define F_VLAN_XTRACT V_VLAN_XTRACT(1U)
110
111#define A_SG_DOORBELL 0x4
112#define A_SG_CMD0BASELWR 0x8
113#define A_SG_CMD0BASEUPR 0xc
114#define A_SG_CMD1BASELWR 0x10
115#define A_SG_CMD1BASEUPR 0x14
116#define A_SG_FL0BASELWR 0x18
117#define A_SG_FL0BASEUPR 0x1c
118#define A_SG_FL1BASELWR 0x20
119#define A_SG_FL1BASEUPR 0x24
120#define A_SG_CMD0SIZE 0x28
121
122#define S_CMDQ0_SIZE 0
123#define M_CMDQ0_SIZE 0x1ffff
124#define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE)
125#define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE)
126
127#define A_SG_FL0SIZE 0x2c
128
129#define S_FL0_SIZE 0
130#define M_FL0_SIZE 0x1ffff
131#define V_FL0_SIZE(x) ((x) << S_FL0_SIZE)
132#define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE)
133
134#define A_SG_RSPSIZE 0x30
135
136#define S_RESPQ_SIZE 0
137#define M_RESPQ_SIZE 0x1ffff
138#define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE)
139#define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE)
140
141#define A_SG_RSPBASELWR 0x34
142#define A_SG_RSPBASEUPR 0x38
143#define A_SG_FLTHRESHOLD 0x3c
144
145#define S_FL_THRESHOLD 0
146#define M_FL_THRESHOLD 0xffff
147#define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD)
148#define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD)
149
150#define A_SG_RSPQUEUECREDIT 0x40
151
152#define S_RESPQ_CREDIT 0
153#define M_RESPQ_CREDIT 0x1ffff
154#define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT)
155#define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT)
156
157#define A_SG_SLEEPING 0x48
158
159#define S_SLEEPING 0
160#define M_SLEEPING 0xffff
161#define V_SLEEPING(x) ((x) << S_SLEEPING)
162#define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING)
163
164#define A_SG_INTRTIMER 0x4c
165
166#define S_INTERRUPT_TIMER_COUNT 0
167#define M_INTERRUPT_TIMER_COUNT 0xffffff
168#define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT)
169#define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT)
170
171#define A_SG_CMD0PTR 0x50
172
173#define S_CMDQ0_POINTER 0
174#define M_CMDQ0_POINTER 0xffff
175#define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER)
176#define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER)
177
178#define S_CURRENT_GENERATION_BIT 16
179#define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT)
180#define F_CURRENT_GENERATION_BIT V_CURRENT_GENERATION_BIT(1U)
181
182#define A_SG_CMD1PTR 0x54
183
184#define S_CMDQ1_POINTER 0
185#define M_CMDQ1_POINTER 0xffff
186#define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER)
187#define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER)
188
189#define A_SG_FL0PTR 0x58
190
191#define S_FL0_POINTER 0
192#define M_FL0_POINTER 0xffff
193#define V_FL0_POINTER(x) ((x) << S_FL0_POINTER)
194#define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER)
195
196#define A_SG_FL1PTR 0x5c
197
198#define S_FL1_POINTER 0
199#define M_FL1_POINTER 0xffff
200#define V_FL1_POINTER(x) ((x) << S_FL1_POINTER)
201#define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER)
202
203#define A_SG_VERSION 0x6c
204
205#define S_DAY 0
206#define M_DAY 0x1f
207#define V_DAY(x) ((x) << S_DAY)
208#define G_DAY(x) (((x) >> S_DAY) & M_DAY)
209
210#define S_MONTH 5
211#define M_MONTH 0xf
212#define V_MONTH(x) ((x) << S_MONTH)
213#define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH)
214
215#define A_SG_CMD1SIZE 0xb0
216
217#define S_CMDQ1_SIZE 0
218#define M_CMDQ1_SIZE 0x1ffff
219#define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE)
220#define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE)
221
222#define A_SG_FL1SIZE 0xb4
223
224#define S_FL1_SIZE 0
225#define M_FL1_SIZE 0x1ffff
226#define V_FL1_SIZE(x) ((x) << S_FL1_SIZE)
227#define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE)
228
229#define A_SG_INT_ENABLE 0xb8
230
231#define S_RESPQ_EXHAUSTED 0
232#define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED)
233#define F_RESPQ_EXHAUSTED V_RESPQ_EXHAUSTED(1U)
234
235#define S_RESPQ_OVERFLOW 1
236#define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW)
237#define F_RESPQ_OVERFLOW V_RESPQ_OVERFLOW(1U)
238
239#define S_FL_EXHAUSTED 2
240#define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED)
241#define F_FL_EXHAUSTED V_FL_EXHAUSTED(1U)
242
243#define S_PACKET_TOO_BIG 3
244#define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG)
245#define F_PACKET_TOO_BIG V_PACKET_TOO_BIG(1U)
246
247#define S_PACKET_MISMATCH 4
248#define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH)
249#define F_PACKET_MISMATCH V_PACKET_MISMATCH(1U)
250
251#define A_SG_INT_CAUSE 0xbc
252#define A_SG_RESPACCUTIMER 0xc0
253
254/* MC3 registers */
255#define A_MC3_CFG 0x100
256
257#define S_CLK_ENABLE 0
258#define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE)
259#define F_CLK_ENABLE V_CLK_ENABLE(1U)
260
261#define S_READY 1
262#define V_READY(x) ((x) << S_READY)
263#define F_READY V_READY(1U)
264
265#define S_READ_TO_WRITE_DELAY 2
266#define M_READ_TO_WRITE_DELAY 0x7
267#define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY)
268#define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY)
269
270#define S_WRITE_TO_READ_DELAY 5
271#define M_WRITE_TO_READ_DELAY 0x7
272#define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY)
273#define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY)
274
275#define S_MC3_BANK_CYCLE 8
276#define M_MC3_BANK_CYCLE 0xf
277#define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE)
278#define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE)
279
280#define S_REFRESH_CYCLE 12
281#define M_REFRESH_CYCLE 0xf
282#define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE)
283#define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE)
284
285#define S_PRECHARGE_CYCLE 16
286#define M_PRECHARGE_CYCLE 0x3
287#define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE)
288#define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE)
289
290#define S_ACTIVE_TO_READ_WRITE_DELAY 18
291#define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY)
292#define F_ACTIVE_TO_READ_WRITE_DELAY V_ACTIVE_TO_READ_WRITE_DELAY(1U)
293
294#define S_ACTIVE_TO_PRECHARGE_DELAY 19
295#define M_ACTIVE_TO_PRECHARGE_DELAY 0x7
296#define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY)
297#define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY)
298
299#define S_WRITE_RECOVERY_DELAY 22
300#define M_WRITE_RECOVERY_DELAY 0x3
301#define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY)
302#define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY)
303
304#define S_DENSITY 24
305#define M_DENSITY 0x3
306#define V_DENSITY(x) ((x) << S_DENSITY)
307#define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY)
308
309#define S_ORGANIZATION 26
310#define V_ORGANIZATION(x) ((x) << S_ORGANIZATION)
311#define F_ORGANIZATION V_ORGANIZATION(1U)
312
313#define S_BANKS 27
314#define V_BANKS(x) ((x) << S_BANKS)
315#define F_BANKS V_BANKS(1U)
316
317#define S_UNREGISTERED 28
318#define V_UNREGISTERED(x) ((x) << S_UNREGISTERED)
319#define F_UNREGISTERED V_UNREGISTERED(1U)
320
321#define S_MC3_WIDTH 29
322#define M_MC3_WIDTH 0x3
323#define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH)
324#define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH)
325
326#define S_MC3_SLOW 31
327#define V_MC3_SLOW(x) ((x) << S_MC3_SLOW)
328#define F_MC3_SLOW V_MC3_SLOW(1U)
329
330#define A_MC3_MODE 0x104
331
332#define S_MC3_MODE 0
333#define M_MC3_MODE 0x3fff
334#define V_MC3_MODE(x) ((x) << S_MC3_MODE)
335#define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE)
336
337#define S_BUSY 31
338#define V_BUSY(x) ((x) << S_BUSY)
339#define F_BUSY V_BUSY(1U)
340
341#define A_MC3_EXT_MODE 0x108
342
343#define S_MC3_EXTENDED_MODE 0
344#define M_MC3_EXTENDED_MODE 0x3fff
345#define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE)
346#define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE)
347
348#define A_MC3_PRECHARG 0x10c
349#define A_MC3_REFRESH 0x110
350
351#define S_REFRESH_ENABLE 0
352#define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE)
353#define F_REFRESH_ENABLE V_REFRESH_ENABLE(1U)
354
355#define S_REFRESH_DIVISOR 1
356#define M_REFRESH_DIVISOR 0x3fff
357#define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR)
358#define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR)
359
360#define A_MC3_STROBE 0x114
361
362#define S_MASTER_DLL_RESET 0
363#define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET)
364#define F_MASTER_DLL_RESET V_MASTER_DLL_RESET(1U)
365
366#define S_MASTER_DLL_TAP_COUNT 1
367#define M_MASTER_DLL_TAP_COUNT 0xff
368#define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT)
369#define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT)
370
371#define S_MASTER_DLL_LOCKED 9
372#define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED)
373#define F_MASTER_DLL_LOCKED V_MASTER_DLL_LOCKED(1U)
374
375#define S_MASTER_DLL_MAX_TAP_COUNT 10
376#define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT)
377#define F_MASTER_DLL_MAX_TAP_COUNT V_MASTER_DLL_MAX_TAP_COUNT(1U)
378
379#define S_MASTER_DLL_TAP_COUNT_OFFSET 11
380#define M_MASTER_DLL_TAP_COUNT_OFFSET 0x3f
381#define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET)
382#define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET)
383
384#define S_SLAVE_DLL_RESET 11
385#define V_SLAVE_DLL_RESET(x) ((x) << S_SLAVE_DLL_RESET)
386#define F_SLAVE_DLL_RESET V_SLAVE_DLL_RESET(1U)
387
388#define S_SLAVE_DLL_DELTA 12
389#define M_SLAVE_DLL_DELTA 0xf
390#define V_SLAVE_DLL_DELTA(x) ((x) << S_SLAVE_DLL_DELTA)
391#define G_SLAVE_DLL_DELTA(x) (((x) >> S_SLAVE_DLL_DELTA) & M_SLAVE_DLL_DELTA)
392
393#define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 17
394#define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 0x3f
395#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
396#define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
397
398#define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE 23
399#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE)
400#define F_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(1U)
401
402#define S_SLAVE_DELAY_LINE_TAP_COUNT 24
403#define M_SLAVE_DELAY_LINE_TAP_COUNT 0x3f
404#define V_SLAVE_DELAY_LINE_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_TAP_COUNT)
405#define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT)
406
407#define A_MC3_ECC_CNTL 0x118
408
409#define S_ECC_GENERATION_ENABLE 0
410#define V_ECC_GENERATION_ENABLE(x) ((x) << S_ECC_GENERATION_ENABLE)
411#define F_ECC_GENERATION_ENABLE V_ECC_GENERATION_ENABLE(1U)
412
413#define S_ECC_CHECK_ENABLE 1
414#define V_ECC_CHECK_ENABLE(x) ((x) << S_ECC_CHECK_ENABLE)
415#define F_ECC_CHECK_ENABLE V_ECC_CHECK_ENABLE(1U)
416
417#define S_CORRECTABLE_ERROR_COUNT 2
418#define M_CORRECTABLE_ERROR_COUNT 0xff
419#define V_CORRECTABLE_ERROR_COUNT(x) ((x) << S_CORRECTABLE_ERROR_COUNT)
420#define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT)
421
422#define S_UNCORRECTABLE_ERROR_COUNT 10
423#define M_UNCORRECTABLE_ERROR_COUNT 0xff
424#define V_UNCORRECTABLE_ERROR_COUNT(x) ((x) << S_UNCORRECTABLE_ERROR_COUNT)
425#define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT)
426
427#define A_MC3_CE_ADDR 0x11c
428
429#define S_MC3_CE_ADDR 4
430#define M_MC3_CE_ADDR 0xfffffff
431#define V_MC3_CE_ADDR(x) ((x) << S_MC3_CE_ADDR)
432#define G_MC3_CE_ADDR(x) (((x) >> S_MC3_CE_ADDR) & M_MC3_CE_ADDR)
433
434#define A_MC3_CE_DATA0 0x120
435#define A_MC3_CE_DATA1 0x124
436#define A_MC3_CE_DATA2 0x128
437#define A_MC3_CE_DATA3 0x12c
438#define A_MC3_CE_DATA4 0x130
439#define A_MC3_UE_ADDR 0x134
440
441#define S_MC3_UE_ADDR 4
442#define M_MC3_UE_ADDR 0xfffffff
443#define V_MC3_UE_ADDR(x) ((x) << S_MC3_UE_ADDR)
444#define G_MC3_UE_ADDR(x) (((x) >> S_MC3_UE_ADDR) & M_MC3_UE_ADDR)
445
446#define A_MC3_UE_DATA0 0x138
447#define A_MC3_UE_DATA1 0x13c
448#define A_MC3_UE_DATA2 0x140
449#define A_MC3_UE_DATA3 0x144
450#define A_MC3_UE_DATA4 0x148
451#define A_MC3_BD_ADDR 0x14c
452#define A_MC3_BD_DATA0 0x150
453#define A_MC3_BD_DATA1 0x154
454#define A_MC3_BD_DATA2 0x158
455#define A_MC3_BD_DATA3 0x15c
456#define A_MC3_BD_DATA4 0x160
457#define A_MC3_BD_OP 0x164
458
459#define S_BACK_DOOR_OPERATION 0
460#define V_BACK_DOOR_OPERATION(x) ((x) << S_BACK_DOOR_OPERATION)
461#define F_BACK_DOOR_OPERATION V_BACK_DOOR_OPERATION(1U)
462
463#define A_MC3_BIST_ADDR_BEG 0x168
464#define A_MC3_BIST_ADDR_END 0x16c
465#define A_MC3_BIST_DATA 0x170
466#define A_MC3_BIST_OP 0x174
467
468#define S_OP 0
469#define V_OP(x) ((x) << S_OP)
470#define F_OP V_OP(1U)
471
472#define S_DATA_PATTERN 1
473#define M_DATA_PATTERN 0x3
474#define V_DATA_PATTERN(x) ((x) << S_DATA_PATTERN)
475#define G_DATA_PATTERN(x) (((x) >> S_DATA_PATTERN) & M_DATA_PATTERN)
476
477#define S_CONTINUOUS 3
478#define V_CONTINUOUS(x) ((x) << S_CONTINUOUS)
479#define F_CONTINUOUS V_CONTINUOUS(1U)
480
481#define A_MC3_INT_ENABLE 0x178
482
483#define S_MC3_CORR_ERR 0
484#define V_MC3_CORR_ERR(x) ((x) << S_MC3_CORR_ERR)
485#define F_MC3_CORR_ERR V_MC3_CORR_ERR(1U)
486
487#define S_MC3_UNCORR_ERR 1
488#define V_MC3_UNCORR_ERR(x) ((x) << S_MC3_UNCORR_ERR)
489#define F_MC3_UNCORR_ERR V_MC3_UNCORR_ERR(1U)
490
491#define S_MC3_PARITY_ERR 2
492#define M_MC3_PARITY_ERR 0xff
493#define V_MC3_PARITY_ERR(x) ((x) << S_MC3_PARITY_ERR)
494#define G_MC3_PARITY_ERR(x) (((x) >> S_MC3_PARITY_ERR) & M_MC3_PARITY_ERR)
495
496#define S_MC3_ADDR_ERR 10
497#define V_MC3_ADDR_ERR(x) ((x) << S_MC3_ADDR_ERR)
498#define F_MC3_ADDR_ERR V_MC3_ADDR_ERR(1U)
499
500#define A_MC3_INT_CAUSE 0x17c
501
502/* MC4 registers */
503#define A_MC4_CFG 0x180
504
505#define S_POWER_UP 0
506#define V_POWER_UP(x) ((x) << S_POWER_UP)
507#define F_POWER_UP V_POWER_UP(1U)
508
509#define S_MC4_BANK_CYCLE 8
510#define M_MC4_BANK_CYCLE 0x7
511#define V_MC4_BANK_CYCLE(x) ((x) << S_MC4_BANK_CYCLE)
512#define G_MC4_BANK_CYCLE(x) (((x) >> S_MC4_BANK_CYCLE) & M_MC4_BANK_CYCLE)
513
514#define S_MC4_NARROW 24
515#define V_MC4_NARROW(x) ((x) << S_MC4_NARROW)
516#define F_MC4_NARROW V_MC4_NARROW(1U)
517
518#define S_MC4_SLOW 25
519#define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)
520#define F_MC4_SLOW V_MC4_SLOW(1U)
521
522#define S_MC4A_WIDTH 24
523#define M_MC4A_WIDTH 0x3
524#define V_MC4A_WIDTH(x) ((x) << S_MC4A_WIDTH)
525#define G_MC4A_WIDTH(x) (((x) >> S_MC4A_WIDTH) & M_MC4A_WIDTH)
526
527#define S_MC4A_SLOW 26
528#define V_MC4A_SLOW(x) ((x) << S_MC4A_SLOW)
529#define F_MC4A_SLOW V_MC4A_SLOW(1U)
530
531#define A_MC4_MODE 0x184
532
533#define S_MC4_MODE 0
534#define M_MC4_MODE 0x7fff
535#define V_MC4_MODE(x) ((x) << S_MC4_MODE)
536#define G_MC4_MODE(x) (((x) >> S_MC4_MODE) & M_MC4_MODE)
537
538#define A_MC4_EXT_MODE 0x188
539
540#define S_MC4_EXTENDED_MODE 0
541#define M_MC4_EXTENDED_MODE 0x7fff
542#define V_MC4_EXTENDED_MODE(x) ((x) << S_MC4_EXTENDED_MODE)
543#define G_MC4_EXTENDED_MODE(x) (((x) >> S_MC4_EXTENDED_MODE) & M_MC4_EXTENDED_MODE)
544
545#define A_MC4_REFRESH 0x190
546#define A_MC4_STROBE 0x194
547#define A_MC4_ECC_CNTL 0x198
548#define A_MC4_CE_ADDR 0x19c
549
550#define S_MC4_CE_ADDR 4
551#define M_MC4_CE_ADDR 0xffffff
552#define V_MC4_CE_ADDR(x) ((x) << S_MC4_CE_ADDR)
553#define G_MC4_CE_ADDR(x) (((x) >> S_MC4_CE_ADDR) & M_MC4_CE_ADDR)
554
555#define A_MC4_CE_DATA0 0x1a0
556#define A_MC4_CE_DATA1 0x1a4
557#define A_MC4_CE_DATA2 0x1a8
558#define A_MC4_CE_DATA3 0x1ac
559#define A_MC4_CE_DATA4 0x1b0
560#define A_MC4_UE_ADDR 0x1b4
561
562#define S_MC4_UE_ADDR 4
563#define M_MC4_UE_ADDR 0xffffff
564#define V_MC4_UE_ADDR(x) ((x) << S_MC4_UE_ADDR)
565#define G_MC4_UE_ADDR(x) (((x) >> S_MC4_UE_ADDR) & M_MC4_UE_ADDR)
566
567#define A_MC4_UE_DATA0 0x1b8
568#define A_MC4_UE_DATA1 0x1bc
569#define A_MC4_UE_DATA2 0x1c0
570#define A_MC4_UE_DATA3 0x1c4
571#define A_MC4_UE_DATA4 0x1c8
572#define A_MC4_BD_ADDR 0x1cc
573
574#define S_MC4_BACK_DOOR_ADDR 0
575#define M_MC4_BACK_DOOR_ADDR 0xfffffff
576#define V_MC4_BACK_DOOR_ADDR(x) ((x) << S_MC4_BACK_DOOR_ADDR)
577#define G_MC4_BACK_DOOR_ADDR(x) (((x) >> S_MC4_BACK_DOOR_ADDR) & M_MC4_BACK_DOOR_ADDR)
578
579#define A_MC4_BD_DATA0 0x1d0
580#define A_MC4_BD_DATA1 0x1d4
581#define A_MC4_BD_DATA2 0x1d8
582#define A_MC4_BD_DATA3 0x1dc
583#define A_MC4_BD_DATA4 0x1e0
584#define A_MC4_BD_OP 0x1e4
585
586#define S_OPERATION 0
587#define V_OPERATION(x) ((x) << S_OPERATION)
588#define F_OPERATION V_OPERATION(1U)
589
590#define A_MC4_BIST_ADDR_BEG 0x1e8
591#define A_MC4_BIST_ADDR_END 0x1ec
592#define A_MC4_BIST_DATA 0x1f0
593#define A_MC4_BIST_OP 0x1f4
594#define A_MC4_INT_ENABLE 0x1f8
595
596#define S_MC4_CORR_ERR 0
597#define V_MC4_CORR_ERR(x) ((x) << S_MC4_CORR_ERR)
598#define F_MC4_CORR_ERR V_MC4_CORR_ERR(1U)
599
600#define S_MC4_UNCORR_ERR 1
601#define V_MC4_UNCORR_ERR(x) ((x) << S_MC4_UNCORR_ERR)
602#define F_MC4_UNCORR_ERR V_MC4_UNCORR_ERR(1U)
603
604#define S_MC4_ADDR_ERR 2
605#define V_MC4_ADDR_ERR(x) ((x) << S_MC4_ADDR_ERR)
606#define F_MC4_ADDR_ERR V_MC4_ADDR_ERR(1U)
607
608#define A_MC4_INT_CAUSE 0x1fc
609
610/* TPI registers */
611#define A_TPI_ADDR 0x280
612
613#define S_TPI_ADDRESS 0
614#define M_TPI_ADDRESS 0xffffff
615#define V_TPI_ADDRESS(x) ((x) << S_TPI_ADDRESS)
616#define G_TPI_ADDRESS(x) (((x) >> S_TPI_ADDRESS) & M_TPI_ADDRESS)
617
618#define A_TPI_WR_DATA 0x284
619#define A_TPI_RD_DATA 0x288
620#define A_TPI_CSR 0x28c
621
622#define S_TPIWR 0
623#define V_TPIWR(x) ((x) << S_TPIWR)
624#define F_TPIWR V_TPIWR(1U)
625
626#define S_TPIRDY 1
627#define V_TPIRDY(x) ((x) << S_TPIRDY)
628#define F_TPIRDY V_TPIRDY(1U)
629
630#define S_INT_DIR 31
631#define V_INT_DIR(x) ((x) << S_INT_DIR)
632#define F_INT_DIR V_INT_DIR(1U)
633
634#define A_TPI_PAR 0x29c
635
636#define S_TPIPAR 0
637#define M_TPIPAR 0x7f
638#define V_TPIPAR(x) ((x) << S_TPIPAR)
639#define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)
640
641
642/* TP registers */
643#define A_TP_IN_CONFIG 0x300
644
645#define S_TP_IN_CSPI_TUNNEL 0
646#define V_TP_IN_CSPI_TUNNEL(x) ((x) << S_TP_IN_CSPI_TUNNEL)
647#define F_TP_IN_CSPI_TUNNEL V_TP_IN_CSPI_TUNNEL(1U)
648
649#define S_TP_IN_CSPI_ETHERNET 1
650#define V_TP_IN_CSPI_ETHERNET(x) ((x) << S_TP_IN_CSPI_ETHERNET)
651#define F_TP_IN_CSPI_ETHERNET V_TP_IN_CSPI_ETHERNET(1U)
652
653#define S_TP_IN_CSPI_CPL 3
654#define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)
655#define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U)
656
657#define S_TP_IN_CSPI_POS 4
658#define V_TP_IN_CSPI_POS(x) ((x) << S_TP_IN_CSPI_POS)
659#define F_TP_IN_CSPI_POS V_TP_IN_CSPI_POS(1U)
660
661#define S_TP_IN_CSPI_CHECK_IP_CSUM 5
662#define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)
663#define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U)
664
665#define S_TP_IN_CSPI_CHECK_TCP_CSUM 6
666#define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)
667#define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)
668
669#define S_TP_IN_ESPI_TUNNEL 7
670#define V_TP_IN_ESPI_TUNNEL(x) ((x) << S_TP_IN_ESPI_TUNNEL)
671#define F_TP_IN_ESPI_TUNNEL V_TP_IN_ESPI_TUNNEL(1U)
672
673#define S_TP_IN_ESPI_ETHERNET 8
674#define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)
675#define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U)
676
677#define S_TP_IN_ESPI_CPL 10
678#define V_TP_IN_ESPI_CPL(x) ((x) << S_TP_IN_ESPI_CPL)
679#define F_TP_IN_ESPI_CPL V_TP_IN_ESPI_CPL(1U)
680
681#define S_TP_IN_ESPI_POS 11
682#define V_TP_IN_ESPI_POS(x) ((x) << S_TP_IN_ESPI_POS)
683#define F_TP_IN_ESPI_POS V_TP_IN_ESPI_POS(1U)
684
685#define S_TP_IN_ESPI_CHECK_IP_CSUM 12
686#define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)
687#define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U)
688
689#define S_TP_IN_ESPI_CHECK_TCP_CSUM 13
690#define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM)
691#define F_TP_IN_ESPI_CHECK_TCP_CSUM V_TP_IN_ESPI_CHECK_TCP_CSUM(1U)
692
693#define S_OFFLOAD_DISABLE 14
694#define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE)
695#define F_OFFLOAD_DISABLE V_OFFLOAD_DISABLE(1U)
696
697#define A_TP_OUT_CONFIG 0x304
698
699#define S_TP_OUT_C_ETH 0
700#define V_TP_OUT_C_ETH(x) ((x) << S_TP_OUT_C_ETH)
701#define F_TP_OUT_C_ETH V_TP_OUT_C_ETH(1U)
702
703#define S_TP_OUT_CSPI_CPL 2
704#define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)
705#define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U)
706
707#define S_TP_OUT_CSPI_POS 3
708#define V_TP_OUT_CSPI_POS(x) ((x) << S_TP_OUT_CSPI_POS)
709#define F_TP_OUT_CSPI_POS V_TP_OUT_CSPI_POS(1U)
710
711#define S_TP_OUT_CSPI_GENERATE_IP_CSUM 4
712#define V_TP_OUT_CSPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_IP_CSUM)
713#define F_TP_OUT_CSPI_GENERATE_IP_CSUM V_TP_OUT_CSPI_GENERATE_IP_CSUM(1U)
714
715#define S_TP_OUT_CSPI_GENERATE_TCP_CSUM 5
716#define V_TP_OUT_CSPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_TCP_CSUM)
717#define F_TP_OUT_CSPI_GENERATE_TCP_CSUM V_TP_OUT_CSPI_GENERATE_TCP_CSUM(1U)
718
719#define S_TP_OUT_ESPI_ETHERNET 6
720#define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)
721#define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U)
722
723#define S_TP_OUT_ESPI_TAG_ETHERNET 7
724#define V_TP_OUT_ESPI_TAG_ETHERNET(x) ((x) << S_TP_OUT_ESPI_TAG_ETHERNET)
725#define F_TP_OUT_ESPI_TAG_ETHERNET V_TP_OUT_ESPI_TAG_ETHERNET(1U)
726
727#define S_TP_OUT_ESPI_CPL 8
728#define V_TP_OUT_ESPI_CPL(x) ((x) << S_TP_OUT_ESPI_CPL)
729#define F_TP_OUT_ESPI_CPL V_TP_OUT_ESPI_CPL(1U)
730
731#define S_TP_OUT_ESPI_POS 9
732#define V_TP_OUT_ESPI_POS(x) ((x) << S_TP_OUT_ESPI_POS)
733#define F_TP_OUT_ESPI_POS V_TP_OUT_ESPI_POS(1U)
734
735#define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10
736#define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)
737#define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)
738
739#define S_TP_OUT_ESPI_GENERATE_TCP_CSUM 11
740#define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM)
741#define F_TP_OUT_ESPI_GENERATE_TCP_CSUM V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U)
742
743#define A_TP_GLOBAL_CONFIG 0x308
744
745#define S_IP_TTL 0
746#define M_IP_TTL 0xff
747#define V_IP_TTL(x) ((x) << S_IP_TTL)
748#define G_IP_TTL(x) (((x) >> S_IP_TTL) & M_IP_TTL)
749
750#define S_TCAM_SERVER_REGION_USAGE 8
751#define M_TCAM_SERVER_REGION_USAGE 0x3
752#define V_TCAM_SERVER_REGION_USAGE(x) ((x) << S_TCAM_SERVER_REGION_USAGE)
753#define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE)
754
755#define S_QOS_MAPPING 10
756#define V_QOS_MAPPING(x) ((x) << S_QOS_MAPPING)
757#define F_QOS_MAPPING V_QOS_MAPPING(1U)
758
759#define S_TCP_CSUM 11
760#define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)
761#define F_TCP_CSUM V_TCP_CSUM(1U)
762
763#define S_UDP_CSUM 12
764#define V_UDP_CSUM(x) ((x) << S_UDP_CSUM)
765#define F_UDP_CSUM V_UDP_CSUM(1U)
766
767#define S_IP_CSUM 13
768#define V_IP_CSUM(x) ((x) << S_IP_CSUM)
769#define F_IP_CSUM V_IP_CSUM(1U)
770
771#define S_IP_ID_SPLIT 14
772#define V_IP_ID_SPLIT(x) ((x) << S_IP_ID_SPLIT)
773#define F_IP_ID_SPLIT V_IP_ID_SPLIT(1U)
774
775#define S_PATH_MTU 15
776#define V_PATH_MTU(x) ((x) << S_PATH_MTU)
777#define F_PATH_MTU V_PATH_MTU(1U)
778
779#define S_5TUPLE_LOOKUP 17
780#define M_5TUPLE_LOOKUP 0x3
781#define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)
782#define G_5TUPLE_LOOKUP(x) (((x) >> S_5TUPLE_LOOKUP) & M_5TUPLE_LOOKUP)
783
784#define S_IP_FRAGMENT_DROP 19
785#define V_IP_FRAGMENT_DROP(x) ((x) << S_IP_FRAGMENT_DROP)
786#define F_IP_FRAGMENT_DROP V_IP_FRAGMENT_DROP(1U)
787
788#define S_PING_DROP 20
789#define V_PING_DROP(x) ((x) << S_PING_DROP)
790#define F_PING_DROP V_PING_DROP(1U)
791
792#define S_PROTECT_MODE 21
793#define V_PROTECT_MODE(x) ((x) << S_PROTECT_MODE)
794#define F_PROTECT_MODE V_PROTECT_MODE(1U)
795
796#define S_SYN_COOKIE_ALGORITHM 22
797#define V_SYN_COOKIE_ALGORITHM(x) ((x) << S_SYN_COOKIE_ALGORITHM)
798#define F_SYN_COOKIE_ALGORITHM V_SYN_COOKIE_ALGORITHM(1U)
799
800#define S_ATTACK_FILTER 23
801#define V_ATTACK_FILTER(x) ((x) << S_ATTACK_FILTER)
802#define F_ATTACK_FILTER V_ATTACK_FILTER(1U)
803
804#define S_INTERFACE_TYPE 24
805#define V_INTERFACE_TYPE(x) ((x) << S_INTERFACE_TYPE)
806#define F_INTERFACE_TYPE V_INTERFACE_TYPE(1U)
807
808#define S_DISABLE_RX_FLOW_CONTROL 25
809#define V_DISABLE_RX_FLOW_CONTROL(x) ((x) << S_DISABLE_RX_FLOW_CONTROL)
810#define F_DISABLE_RX_FLOW_CONTROL V_DISABLE_RX_FLOW_CONTROL(1U)
811
812#define S_SYN_COOKIE_PARAMETER 26
813#define M_SYN_COOKIE_PARAMETER 0x3f
814#define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)
815#define G_SYN_COOKIE_PARAMETER(x) (((x) >> S_SYN_COOKIE_PARAMETER) & M_SYN_COOKIE_PARAMETER)
816
817#define A_TP_GLOBAL_RX_CREDITS 0x30c
818#define A_TP_CM_SIZE 0x310
819#define A_TP_CM_MM_BASE 0x314
820
821#define S_CM_MEMMGR_BASE 0
822#define M_CM_MEMMGR_BASE 0xfffffff
823#define V_CM_MEMMGR_BASE(x) ((x) << S_CM_MEMMGR_BASE)
824#define G_CM_MEMMGR_BASE(x) (((x) >> S_CM_MEMMGR_BASE) & M_CM_MEMMGR_BASE)
825
826#define A_TP_CM_TIMER_BASE 0x318
827
828#define S_CM_TIMER_BASE 0
829#define M_CM_TIMER_BASE 0xfffffff
830#define V_CM_TIMER_BASE(x) ((x) << S_CM_TIMER_BASE)
831#define G_CM_TIMER_BASE(x) (((x) >> S_CM_TIMER_BASE) & M_CM_TIMER_BASE)
832
833#define A_TP_PM_SIZE 0x31c
834#define A_TP_PM_TX_BASE 0x320
835#define A_TP_PM_DEFRAG_BASE 0x324
836#define A_TP_PM_RX_BASE 0x328
837#define A_TP_PM_RX_PG_SIZE 0x32c
838#define A_TP_PM_RX_MAX_PGS 0x330
839#define A_TP_PM_TX_PG_SIZE 0x334
840#define A_TP_PM_TX_MAX_PGS 0x338
841#define A_TP_TCP_OPTIONS 0x340
842
843#define S_TIMESTAMP 0
844#define M_TIMESTAMP 0x3
845#define V_TIMESTAMP(x) ((x) << S_TIMESTAMP)
846#define G_TIMESTAMP(x) (((x) >> S_TIMESTAMP) & M_TIMESTAMP)
847
848#define S_WINDOW_SCALE 2
849#define M_WINDOW_SCALE 0x3
850#define V_WINDOW_SCALE(x) ((x) << S_WINDOW_SCALE)
851#define G_WINDOW_SCALE(x) (((x) >> S_WINDOW_SCALE) & M_WINDOW_SCALE)
852
853#define S_SACK 4
854#define M_SACK 0x3
855#define V_SACK(x) ((x) << S_SACK)
856#define G_SACK(x) (((x) >> S_SACK) & M_SACK)
857
858#define S_ECN 6
859#define M_ECN 0x3
860#define V_ECN(x) ((x) << S_ECN)
861#define G_ECN(x) (((x) >> S_ECN) & M_ECN)
862
863#define S_SACK_ALGORITHM 8
864#define M_SACK_ALGORITHM 0x3
865#define V_SACK_ALGORITHM(x) ((x) << S_SACK_ALGORITHM)
866#define G_SACK_ALGORITHM(x) (((x) >> S_SACK_ALGORITHM) & M_SACK_ALGORITHM)
867
868#define S_MSS 10
869#define V_MSS(x) ((x) << S_MSS)
870#define F_MSS V_MSS(1U)
871
872#define S_DEFAULT_PEER_MSS 16
873#define M_DEFAULT_PEER_MSS 0xffff
874#define V_DEFAULT_PEER_MSS(x) ((x) << S_DEFAULT_PEER_MSS)
875#define G_DEFAULT_PEER_MSS(x) (((x) >> S_DEFAULT_PEER_MSS) & M_DEFAULT_PEER_MSS)
876
877#define A_TP_DACK_CONFIG 0x344
878
879#define S_DACK_MODE 0
880#define V_DACK_MODE(x) ((x) << S_DACK_MODE)
881#define F_DACK_MODE V_DACK_MODE(1U)
882
883#define S_DACK_AUTO_MGMT 1
884#define V_DACK_AUTO_MGMT(x) ((x) << S_DACK_AUTO_MGMT)
885#define F_DACK_AUTO_MGMT V_DACK_AUTO_MGMT(1U)
886
887#define S_DACK_AUTO_CAREFUL 2
888#define V_DACK_AUTO_CAREFUL(x) ((x) << S_DACK_AUTO_CAREFUL)
889#define F_DACK_AUTO_CAREFUL V_DACK_AUTO_CAREFUL(1U)
890
891#define S_DACK_MSS_SELECTOR 3
892#define M_DACK_MSS_SELECTOR 0x3
893#define V_DACK_MSS_SELECTOR(x) ((x) << S_DACK_MSS_SELECTOR)
894#define G_DACK_MSS_SELECTOR(x) (((x) >> S_DACK_MSS_SELECTOR) & M_DACK_MSS_SELECTOR)
895
896#define S_DACK_BYTE_THRESHOLD 5
897#define M_DACK_BYTE_THRESHOLD 0xfffff
898#define V_DACK_BYTE_THRESHOLD(x) ((x) << S_DACK_BYTE_THRESHOLD)
899#define G_DACK_BYTE_THRESHOLD(x) (((x) >> S_DACK_BYTE_THRESHOLD) & M_DACK_BYTE_THRESHOLD)
900
901#define A_TP_PC_CONFIG 0x348
902
903#define S_TP_ACCESS_LATENCY 0
904#define M_TP_ACCESS_LATENCY 0xf
905#define V_TP_ACCESS_LATENCY(x) ((x) << S_TP_ACCESS_LATENCY)
906#define G_TP_ACCESS_LATENCY(x) (((x) >> S_TP_ACCESS_LATENCY) & M_TP_ACCESS_LATENCY)
907
908#define S_HELD_FIN_DISABLE 4
909#define V_HELD_FIN_DISABLE(x) ((x) << S_HELD_FIN_DISABLE)
910#define F_HELD_FIN_DISABLE V_HELD_FIN_DISABLE(1U)
911
912#define S_DDP_FC_ENABLE 5
913#define V_DDP_FC_ENABLE(x) ((x) << S_DDP_FC_ENABLE)
914#define F_DDP_FC_ENABLE V_DDP_FC_ENABLE(1U)
915
916#define S_RDMA_ERR_ENABLE 6
917#define V_RDMA_ERR_ENABLE(x) ((x) << S_RDMA_ERR_ENABLE)
918#define F_RDMA_ERR_ENABLE V_RDMA_ERR_ENABLE(1U)
919
920#define S_FAST_PDU_DELIVERY 7
921#define V_FAST_PDU_DELIVERY(x) ((x) << S_FAST_PDU_DELIVERY)
922#define F_FAST_PDU_DELIVERY V_FAST_PDU_DELIVERY(1U)
923
924#define S_CLEAR_FIN 8
925#define V_CLEAR_FIN(x) ((x) << S_CLEAR_FIN)
926#define F_CLEAR_FIN V_CLEAR_FIN(1U)
927
928#define S_DIS_TX_FILL_WIN_PUSH 12
929#define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH)
930#define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U)
931
932#define S_TP_PC_REV 30
933#define M_TP_PC_REV 0x3
934#define V_TP_PC_REV(x) ((x) << S_TP_PC_REV)
935#define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)
936
937#define A_TP_BACKOFF0 0x350
938
939#define S_ELEMENT0 0
940#define M_ELEMENT0 0xff
941#define V_ELEMENT0(x) ((x) << S_ELEMENT0)
942#define G_ELEMENT0(x) (((x) >> S_ELEMENT0) & M_ELEMENT0)
943
944#define S_ELEMENT1 8
945#define M_ELEMENT1 0xff
946#define V_ELEMENT1(x) ((x) << S_ELEMENT1)
947#define G_ELEMENT1(x) (((x) >> S_ELEMENT1) & M_ELEMENT1)
948
949#define S_ELEMENT2 16
950#define M_ELEMENT2 0xff
951#define V_ELEMENT2(x) ((x) << S_ELEMENT2)
952#define G_ELEMENT2(x) (((x) >> S_ELEMENT2) & M_ELEMENT2)
953
954#define S_ELEMENT3 24
955#define M_ELEMENT3 0xff
956#define V_ELEMENT3(x) ((x) << S_ELEMENT3)
957#define G_ELEMENT3(x) (((x) >> S_ELEMENT3) & M_ELEMENT3)
958
959#define A_TP_BACKOFF1 0x354
960#define A_TP_BACKOFF2 0x358
961#define A_TP_BACKOFF3 0x35c
962#define A_TP_PARA_REG0 0x360
963
964#define S_VAR_MULT 0
965#define M_VAR_MULT 0xf
966#define V_VAR_MULT(x) ((x) << S_VAR_MULT)
967#define G_VAR_MULT(x) (((x) >> S_VAR_MULT) & M_VAR_MULT)
968
969#define S_VAR_GAIN 4
970#define M_VAR_GAIN 0xf
971#define V_VAR_GAIN(x) ((x) << S_VAR_GAIN)
972#define G_VAR_GAIN(x) (((x) >> S_VAR_GAIN) & M_VAR_GAIN)
973
974#define S_SRTT_GAIN 8
975#define M_SRTT_GAIN 0xf
976#define V_SRTT_GAIN(x) ((x) << S_SRTT_GAIN)
977#define G_SRTT_GAIN(x) (((x) >> S_SRTT_GAIN) & M_SRTT_GAIN)
978
979#define S_RTTVAR_INIT 12
980#define M_RTTVAR_INIT 0xf
981#define V_RTTVAR_INIT(x) ((x) << S_RTTVAR_INIT)
982#define G_RTTVAR_INIT(x) (((x) >> S_RTTVAR_INIT) & M_RTTVAR_INIT)
983
984#define S_DUP_THRESH 20
985#define M_DUP_THRESH 0xf
986#define V_DUP_THRESH(x) ((x) << S_DUP_THRESH)
987#define G_DUP_THRESH(x) (((x) >> S_DUP_THRESH) & M_DUP_THRESH)
988
989#define S_INIT_CONG_WIN 24
990#define M_INIT_CONG_WIN 0x7
991#define V_INIT_CONG_WIN(x) ((x) << S_INIT_CONG_WIN)
992#define G_INIT_CONG_WIN(x) (((x) >> S_INIT_CONG_WIN) & M_INIT_CONG_WIN)
993
994#define A_TP_PARA_REG1 0x364
995
996#define S_INITIAL_SLOW_START_THRESHOLD 0
997#define M_INITIAL_SLOW_START_THRESHOLD 0xffff
998#define V_INITIAL_SLOW_START_THRESHOLD(x) ((x) << S_INITIAL_SLOW_START_THRESHOLD)
999#define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD)
1000
1001#define S_RECEIVE_BUFFER_SIZE 16
1002#define M_RECEIVE_BUFFER_SIZE 0xffff
1003#define V_RECEIVE_BUFFER_SIZE(x) ((x) << S_RECEIVE_BUFFER_SIZE)
1004#define G_RECEIVE_BUFFER_SIZE(x) (((x) >> S_RECEIVE_BUFFER_SIZE) & M_RECEIVE_BUFFER_SIZE)
1005
1006#define A_TP_PARA_REG2 0x368
1007
1008#define S_RX_COALESCE_SIZE 0
1009#define M_RX_COALESCE_SIZE 0xffff
1010#define V_RX_COALESCE_SIZE(x) ((x) << S_RX_COALESCE_SIZE)
1011#define G_RX_COALESCE_SIZE(x) (((x) >> S_RX_COALESCE_SIZE) & M_RX_COALESCE_SIZE)
1012
1013#define S_MAX_RX_SIZE 16
1014#define M_MAX_RX_SIZE 0xffff
1015#define V_MAX_RX_SIZE(x) ((x) << S_MAX_RX_SIZE)
1016#define G_MAX_RX_SIZE(x) (((x) >> S_MAX_RX_SIZE) & M_MAX_RX_SIZE)
1017
1018#define A_TP_PARA_REG3 0x36c
1019
1020#define S_RX_COALESCING_PSH_DELIVER 0
1021#define V_RX_COALESCING_PSH_DELIVER(x) ((x) << S_RX_COALESCING_PSH_DELIVER)
1022#define F_RX_COALESCING_PSH_DELIVER V_RX_COALESCING_PSH_DELIVER(1U)
1023
1024#define S_RX_COALESCING_ENABLE 1
1025#define V_RX_COALESCING_ENABLE(x) ((x) << S_RX_COALESCING_ENABLE)
1026#define F_RX_COALESCING_ENABLE V_RX_COALESCING_ENABLE(1U)
1027
1028#define S_TAHOE_ENABLE 2
1029#define V_TAHOE_ENABLE(x) ((x) << S_TAHOE_ENABLE)
1030#define F_TAHOE_ENABLE V_TAHOE_ENABLE(1U)
1031
1032#define S_MAX_REORDER_FRAGMENTS 12
1033#define M_MAX_REORDER_FRAGMENTS 0x7
1034#define V_MAX_REORDER_FRAGMENTS(x) ((x) << S_MAX_REORDER_FRAGMENTS)
1035#define G_MAX_REORDER_FRAGMENTS(x) (((x) >> S_MAX_REORDER_FRAGMENTS) & M_MAX_REORDER_FRAGMENTS)
1036
1037#define A_TP_TIMER_RESOLUTION 0x390
1038
1039#define S_DELAYED_ACK_TIMER_RESOLUTION 0
1040#define M_DELAYED_ACK_TIMER_RESOLUTION 0x3f
1041#define V_DELAYED_ACK_TIMER_RESOLUTION(x) ((x) << S_DELAYED_ACK_TIMER_RESOLUTION)
1042#define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION)
1043
1044#define S_GENERIC_TIMER_RESOLUTION 16
1045#define M_GENERIC_TIMER_RESOLUTION 0x3f
1046#define V_GENERIC_TIMER_RESOLUTION(x) ((x) << S_GENERIC_TIMER_RESOLUTION)
1047#define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION)
1048
1049#define A_TP_2MSL 0x394
1050
1051#define S_2MSL 0
1052#define M_2MSL 0x3fffffff
1053#define V_2MSL(x) ((x) << S_2MSL)
1054#define G_2MSL(x) (((x) >> S_2MSL) & M_2MSL)
1055
1056#define A_TP_RXT_MIN 0x398
1057
1058#define S_RETRANSMIT_TIMER_MIN 0
1059#define M_RETRANSMIT_TIMER_MIN 0xffff
1060#define V_RETRANSMIT_TIMER_MIN(x) ((x) << S_RETRANSMIT_TIMER_MIN)
1061#define G_RETRANSMIT_TIMER_MIN(x) (((x) >> S_RETRANSMIT_TIMER_MIN) & M_RETRANSMIT_TIMER_MIN)
1062
1063#define A_TP_RXT_MAX 0x39c
1064
1065#define S_RETRANSMIT_TIMER_MAX 0
1066#define M_RETRANSMIT_TIMER_MAX 0x3fffffff
1067#define V_RETRANSMIT_TIMER_MAX(x) ((x) << S_RETRANSMIT_TIMER_MAX)
1068#define G_RETRANSMIT_TIMER_MAX(x) (((x) >> S_RETRANSMIT_TIMER_MAX) & M_RETRANSMIT_TIMER_MAX)
1069
1070#define A_TP_PERS_MIN 0x3a0
1071
1072#define S_PERSIST_TIMER_MIN 0
1073#define M_PERSIST_TIMER_MIN 0xffff
1074#define V_PERSIST_TIMER_MIN(x) ((x) << S_PERSIST_TIMER_MIN)
1075#define G_PERSIST_TIMER_MIN(x) (((x) >> S_PERSIST_TIMER_MIN) & M_PERSIST_TIMER_MIN)
1076
1077#define A_TP_PERS_MAX 0x3a4
1078
1079#define S_PERSIST_TIMER_MAX 0
1080#define M_PERSIST_TIMER_MAX 0x3fffffff
1081#define V_PERSIST_TIMER_MAX(x) ((x) << S_PERSIST_TIMER_MAX)
1082#define G_PERSIST_TIMER_MAX(x) (((x) >> S_PERSIST_TIMER_MAX) & M_PERSIST_TIMER_MAX)
1083
1084#define A_TP_KEEP_IDLE 0x3ac
1085
1086#define S_KEEP_ALIVE_IDLE_TIME 0
1087#define M_KEEP_ALIVE_IDLE_TIME 0x3fffffff
1088#define V_KEEP_ALIVE_IDLE_TIME(x) ((x) << S_KEEP_ALIVE_IDLE_TIME)
1089#define G_KEEP_ALIVE_IDLE_TIME(x) (((x) >> S_KEEP_ALIVE_IDLE_TIME) & M_KEEP_ALIVE_IDLE_TIME)
1090
1091#define A_TP_KEEP_INTVL 0x3b0
1092
1093#define S_KEEP_ALIVE_INTERVAL_TIME 0
1094#define M_KEEP_ALIVE_INTERVAL_TIME 0x3fffffff
1095#define V_KEEP_ALIVE_INTERVAL_TIME(x) ((x) << S_KEEP_ALIVE_INTERVAL_TIME)
1096#define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME)
1097
1098#define A_TP_INIT_SRTT 0x3b4
1099
1100#define S_INITIAL_SRTT 0
1101#define M_INITIAL_SRTT 0xffff
1102#define V_INITIAL_SRTT(x) ((x) << S_INITIAL_SRTT)
1103#define G_INITIAL_SRTT(x) (((x) >> S_INITIAL_SRTT) & M_INITIAL_SRTT)
1104
1105#define A_TP_DACK_TIME 0x3b8
1106
1107#define S_DELAYED_ACK_TIME 0
1108#define M_DELAYED_ACK_TIME 0x7ff
1109#define V_DELAYED_ACK_TIME(x) ((x) << S_DELAYED_ACK_TIME)
1110#define G_DELAYED_ACK_TIME(x) (((x) >> S_DELAYED_ACK_TIME) & M_DELAYED_ACK_TIME)
1111
1112#define A_TP_FINWAIT2_TIME 0x3bc
1113
1114#define S_FINWAIT2_TIME 0
1115#define M_FINWAIT2_TIME 0x3fffffff
1116#define V_FINWAIT2_TIME(x) ((x) << S_FINWAIT2_TIME)
1117#define G_FINWAIT2_TIME(x) (((x) >> S_FINWAIT2_TIME) & M_FINWAIT2_TIME)
1118
1119#define A_TP_FAST_FINWAIT2_TIME 0x3c0
1120
1121#define S_FAST_FINWAIT2_TIME 0
1122#define M_FAST_FINWAIT2_TIME 0x3fffffff
1123#define V_FAST_FINWAIT2_TIME(x) ((x) << S_FAST_FINWAIT2_TIME)
1124#define G_FAST_FINWAIT2_TIME(x) (((x) >> S_FAST_FINWAIT2_TIME) & M_FAST_FINWAIT2_TIME)
1125
1126#define A_TP_SHIFT_CNT 0x3c4
1127
1128#define S_KEEPALIVE_MAX 0
1129#define M_KEEPALIVE_MAX 0xff
1130#define V_KEEPALIVE_MAX(x) ((x) << S_KEEPALIVE_MAX)
1131#define G_KEEPALIVE_MAX(x) (((x) >> S_KEEPALIVE_MAX) & M_KEEPALIVE_MAX)
1132
1133#define S_WINDOWPROBE_MAX 8
1134#define M_WINDOWPROBE_MAX 0xff
1135#define V_WINDOWPROBE_MAX(x) ((x) << S_WINDOWPROBE_MAX)
1136#define G_WINDOWPROBE_MAX(x) (((x) >> S_WINDOWPROBE_MAX) & M_WINDOWPROBE_MAX)
1137
1138#define S_RETRANSMISSION_MAX 16
1139#define M_RETRANSMISSION_MAX 0xff
1140#define V_RETRANSMISSION_MAX(x) ((x) << S_RETRANSMISSION_MAX)
1141#define G_RETRANSMISSION_MAX(x) (((x) >> S_RETRANSMISSION_MAX) & M_RETRANSMISSION_MAX)
1142
1143#define S_SYN_MAX 24
1144#define M_SYN_MAX 0xff
1145#define V_SYN_MAX(x) ((x) << S_SYN_MAX)
1146#define G_SYN_MAX(x) (((x) >> S_SYN_MAX) & M_SYN_MAX)
1147
1148#define A_TP_QOS_REG0 0x3e0
1149
1150#define S_L3_VALUE 0
1151#define M_L3_VALUE 0x3f
1152#define V_L3_VALUE(x) ((x) << S_L3_VALUE)
1153#define G_L3_VALUE(x) (((x) >> S_L3_VALUE) & M_L3_VALUE)
1154
1155#define A_TP_QOS_REG1 0x3e4
1156#define A_TP_QOS_REG2 0x3e8
1157#define A_TP_QOS_REG3 0x3ec
1158#define A_TP_QOS_REG4 0x3f0
1159#define A_TP_QOS_REG5 0x3f4
1160#define A_TP_QOS_REG6 0x3f8
1161#define A_TP_QOS_REG7 0x3fc
1162#define A_TP_MTU_REG0 0x404
1163#define A_TP_MTU_REG1 0x408
1164#define A_TP_MTU_REG2 0x40c
1165#define A_TP_MTU_REG3 0x410
1166#define A_TP_MTU_REG4 0x414
1167#define A_TP_MTU_REG5 0x418
1168#define A_TP_MTU_REG6 0x41c
1169#define A_TP_MTU_REG7 0x420
1170#define A_TP_RESET 0x44c
1171
1172#define S_TP_RESET 0
1173#define V_TP_RESET(x) ((x) << S_TP_RESET)
1174#define F_TP_RESET V_TP_RESET(1U)
1175
1176#define S_CM_MEMMGR_INIT 1
1177#define V_CM_MEMMGR_INIT(x) ((x) << S_CM_MEMMGR_INIT)
1178#define F_CM_MEMMGR_INIT V_CM_MEMMGR_INIT(1U)
1179
1180#define A_TP_MIB_INDEX 0x450
1181#define A_TP_MIB_DATA 0x454
1182#define A_TP_SYNC_TIME_HI 0x458
1183#define A_TP_SYNC_TIME_LO 0x45c
1184#define A_TP_CM_MM_RX_FLST_BASE 0x460
1185
1186#define S_CM_MEMMGR_RX_FREE_LIST_BASE 0
1187#define M_CM_MEMMGR_RX_FREE_LIST_BASE 0xfffffff
1188#define V_CM_MEMMGR_RX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_RX_FREE_LIST_BASE)
1189#define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE)
1190
1191#define A_TP_CM_MM_TX_FLST_BASE 0x464
1192
1193#define S_CM_MEMMGR_TX_FREE_LIST_BASE 0
1194#define M_CM_MEMMGR_TX_FREE_LIST_BASE 0xfffffff
1195#define V_CM_MEMMGR_TX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_TX_FREE_LIST_BASE)
1196#define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE)
1197
1198#define A_TP_CM_MM_P_FLST_BASE 0x468
1199
1200#define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0
1201#define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0xfffffff
1202#define V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1203#define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1204
1205#define A_TP_CM_MM_MAX_P 0x46c
1206
1207#define S_CM_MEMMGR_MAX_PSTRUCT 0
1208#define M_CM_MEMMGR_MAX_PSTRUCT 0xfffffff
1209#define V_CM_MEMMGR_MAX_PSTRUCT(x) ((x) << S_CM_MEMMGR_MAX_PSTRUCT)
1210#define G_CM_MEMMGR_MAX_PSTRUCT(x) (((x) >> S_CM_MEMMGR_MAX_PSTRUCT) & M_CM_MEMMGR_MAX_PSTRUCT)
1211
1212#define A_TP_INT_ENABLE 0x470
1213
1214#define S_TX_FREE_LIST_EMPTY 0
1215#define V_TX_FREE_LIST_EMPTY(x) ((x) << S_TX_FREE_LIST_EMPTY)
1216#define F_TX_FREE_LIST_EMPTY V_TX_FREE_LIST_EMPTY(1U)
1217
1218#define S_RX_FREE_LIST_EMPTY 1
1219#define V_RX_FREE_LIST_EMPTY(x) ((x) << S_RX_FREE_LIST_EMPTY)
1220#define F_RX_FREE_LIST_EMPTY V_RX_FREE_LIST_EMPTY(1U)
1221
1222#define A_TP_INT_CAUSE 0x474
1223#define A_TP_TIMER_SEPARATOR 0x4a4
1224
1225#define S_DISABLE_PAST_TIMER_INSERTION 0
1226#define V_DISABLE_PAST_TIMER_INSERTION(x) ((x) << S_DISABLE_PAST_TIMER_INSERTION)
1227#define F_DISABLE_PAST_TIMER_INSERTION V_DISABLE_PAST_TIMER_INSERTION(1U)
1228
1229#define S_MODULATION_TIMER_SEPARATOR 1
1230#define M_MODULATION_TIMER_SEPARATOR 0x7fff
1231#define V_MODULATION_TIMER_SEPARATOR(x) ((x) << S_MODULATION_TIMER_SEPARATOR)
1232#define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR)
1233
1234#define S_GLOBAL_TIMER_SEPARATOR 16
1235#define M_GLOBAL_TIMER_SEPARATOR 0xffff
1236#define V_GLOBAL_TIMER_SEPARATOR(x) ((x) << S_GLOBAL_TIMER_SEPARATOR)
1237#define G_GLOBAL_TIMER_SEPARATOR(x) (((x) >> S_GLOBAL_TIMER_SEPARATOR) & M_GLOBAL_TIMER_SEPARATOR)
1238
1239#define A_TP_CM_FC_MODE 0x4b0
1240#define A_TP_PC_CONGESTION_CNTL 0x4b4
1241#define A_TP_TX_DROP_CONFIG 0x4b8
1242
1243#define S_ENABLE_TX_DROP 31
1244#define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP)
1245#define F_ENABLE_TX_DROP V_ENABLE_TX_DROP(1U)
1246
1247#define S_ENABLE_TX_ERROR 30
1248#define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR)
1249#define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U)
1250
1251#define S_DROP_TICKS_CNT 4
1252#define M_DROP_TICKS_CNT 0x3ffffff
1253#define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)
1254#define G_DROP_TICKS_CNT(x) (((x) >> S_DROP_TICKS_CNT) & M_DROP_TICKS_CNT)
1255
1256#define S_NUM_PKTS_DROPPED 0
1257#define M_NUM_PKTS_DROPPED 0xf
1258#define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)
1259#define G_NUM_PKTS_DROPPED(x) (((x) >> S_NUM_PKTS_DROPPED) & M_NUM_PKTS_DROPPED)
1260
1261#define A_TP_TX_DROP_COUNT 0x4bc
1262
1263/* RAT registers */
1264#define A_RAT_ROUTE_CONTROL 0x580
1265
1266#define S_USE_ROUTE_TABLE 0
1267#define V_USE_ROUTE_TABLE(x) ((x) << S_USE_ROUTE_TABLE)
1268#define F_USE_ROUTE_TABLE V_USE_ROUTE_TABLE(1U)
1269
1270#define S_ENABLE_CSPI 1
1271#define V_ENABLE_CSPI(x) ((x) << S_ENABLE_CSPI)
1272#define F_ENABLE_CSPI V_ENABLE_CSPI(1U)
1273
1274#define S_ENABLE_PCIX 2
1275#define V_ENABLE_PCIX(x) ((x) << S_ENABLE_PCIX)
1276#define F_ENABLE_PCIX V_ENABLE_PCIX(1U)
1277
1278#define A_RAT_ROUTE_TABLE_INDEX 0x584
1279
1280#define S_ROUTE_TABLE_INDEX 0
1281#define M_ROUTE_TABLE_INDEX 0xf
1282#define V_ROUTE_TABLE_INDEX(x) ((x) << S_ROUTE_TABLE_INDEX)
1283#define G_ROUTE_TABLE_INDEX(x) (((x) >> S_ROUTE_TABLE_INDEX) & M_ROUTE_TABLE_INDEX)
1284
1285#define A_RAT_ROUTE_TABLE_DATA 0x588
1286#define A_RAT_NO_ROUTE 0x58c
1287
1288#define S_CPL_OPCODE 0
1289#define M_CPL_OPCODE 0xff
1290#define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
1291#define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & M_CPL_OPCODE)
1292
1293#define A_RAT_INTR_ENABLE 0x590
1294
1295#define S_ZEROROUTEERROR 0
1296#define V_ZEROROUTEERROR(x) ((x) << S_ZEROROUTEERROR)
1297#define F_ZEROROUTEERROR V_ZEROROUTEERROR(1U)
1298
1299#define S_CSPIFRAMINGERROR 1
1300#define V_CSPIFRAMINGERROR(x) ((x) << S_CSPIFRAMINGERROR)
1301#define F_CSPIFRAMINGERROR V_CSPIFRAMINGERROR(1U)
1302
1303#define S_SGEFRAMINGERROR 2
1304#define V_SGEFRAMINGERROR(x) ((x) << S_SGEFRAMINGERROR)
1305#define F_SGEFRAMINGERROR V_SGEFRAMINGERROR(1U)
1306
1307#define S_TPFRAMINGERROR 3
1308#define V_TPFRAMINGERROR(x) ((x) << S_TPFRAMINGERROR)
1309#define F_TPFRAMINGERROR V_TPFRAMINGERROR(1U)
1310
1311#define A_RAT_INTR_CAUSE 0x594
1312
1313/* CSPI registers */
1314#define A_CSPI_RX_AE_WM 0x810
1315#define A_CSPI_RX_AF_WM 0x814
1316#define A_CSPI_CALENDAR_LEN 0x818
1317
1318#define S_CALENDARLENGTH 0
1319#define M_CALENDARLENGTH 0xffff
1320#define V_CALENDARLENGTH(x) ((x) << S_CALENDARLENGTH)
1321#define G_CALENDARLENGTH(x) (((x) >> S_CALENDARLENGTH) & M_CALENDARLENGTH)
1322
1323#define A_CSPI_FIFO_STATUS_ENABLE 0x820
1324
1325#define S_FIFOSTATUSENABLE 0
1326#define V_FIFOSTATUSENABLE(x) ((x) << S_FIFOSTATUSENABLE)
1327#define F_FIFOSTATUSENABLE V_FIFOSTATUSENABLE(1U)
1328
1329#define A_CSPI_MAXBURST1_MAXBURST2 0x828
1330
1331#define S_MAXBURST1 0
1332#define M_MAXBURST1 0xffff
1333#define V_MAXBURST1(x) ((x) << S_MAXBURST1)
1334#define G_MAXBURST1(x) (((x) >> S_MAXBURST1) & M_MAXBURST1)
1335
1336#define S_MAXBURST2 16
1337#define M_MAXBURST2 0xffff
1338#define V_MAXBURST2(x) ((x) << S_MAXBURST2)
1339#define G_MAXBURST2(x) (((x) >> S_MAXBURST2) & M_MAXBURST2)
1340
1341#define A_CSPI_TRAIN 0x82c
1342
1343#define S_CSPI_TRAIN_ALPHA 0
1344#define M_CSPI_TRAIN_ALPHA 0xffff
1345#define V_CSPI_TRAIN_ALPHA(x) ((x) << S_CSPI_TRAIN_ALPHA)
1346#define G_CSPI_TRAIN_ALPHA(x) (((x) >> S_CSPI_TRAIN_ALPHA) & M_CSPI_TRAIN_ALPHA)
1347
1348#define S_CSPI_TRAIN_DATA_MAXT 16
1349#define M_CSPI_TRAIN_DATA_MAXT 0xffff
1350#define V_CSPI_TRAIN_DATA_MAXT(x) ((x) << S_CSPI_TRAIN_DATA_MAXT)
1351#define G_CSPI_TRAIN_DATA_MAXT(x) (((x) >> S_CSPI_TRAIN_DATA_MAXT) & M_CSPI_TRAIN_DATA_MAXT)
1352
1353#define A_CSPI_INTR_STATUS 0x848
1354
1355#define S_DIP4ERR 0
1356#define V_DIP4ERR(x) ((x) << S_DIP4ERR)
1357#define F_DIP4ERR V_DIP4ERR(1U)
1358
1359#define S_RXDROP 1
1360#define V_RXDROP(x) ((x) << S_RXDROP)
1361#define F_RXDROP V_RXDROP(1U)
1362
1363#define S_TXDROP 2
1364#define V_TXDROP(x) ((x) << S_TXDROP)
1365#define F_TXDROP V_TXDROP(1U)
1366
1367#define S_RXOVERFLOW 3
1368#define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW)
1369#define F_RXOVERFLOW V_RXOVERFLOW(1U)
1370
1371#define S_RAMPARITYERR 4
1372#define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)
1373#define F_RAMPARITYERR V_RAMPARITYERR(1U)
1374
1375#define A_CSPI_INTR_ENABLE 0x84c
1376
1377/* ESPI registers */
1378#define A_ESPI_SCH_TOKEN0 0x880
1379
1380#define S_SCHTOKEN0 0
1381#define M_SCHTOKEN0 0xffff
1382#define V_SCHTOKEN0(x) ((x) << S_SCHTOKEN0)
1383#define G_SCHTOKEN0(x) (((x) >> S_SCHTOKEN0) & M_SCHTOKEN0)
1384
1385#define A_ESPI_SCH_TOKEN1 0x884
1386
1387#define S_SCHTOKEN1 0
1388#define M_SCHTOKEN1 0xffff
1389#define V_SCHTOKEN1(x) ((x) << S_SCHTOKEN1)
1390#define G_SCHTOKEN1(x) (((x) >> S_SCHTOKEN1) & M_SCHTOKEN1)
1391
1392#define A_ESPI_SCH_TOKEN2 0x888
1393
1394#define S_SCHTOKEN2 0
1395#define M_SCHTOKEN2 0xffff
1396#define V_SCHTOKEN2(x) ((x) << S_SCHTOKEN2)
1397#define G_SCHTOKEN2(x) (((x) >> S_SCHTOKEN2) & M_SCHTOKEN2)
1398
1399#define A_ESPI_SCH_TOKEN3 0x88c
1400
1401#define S_SCHTOKEN3 0
1402#define M_SCHTOKEN3 0xffff
1403#define V_SCHTOKEN3(x) ((x) << S_SCHTOKEN3)
1404#define G_SCHTOKEN3(x) (((x) >> S_SCHTOKEN3) & M_SCHTOKEN3)
1405
1406#define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
1407
1408#define S_ALMOSTEMPTY 0
1409#define M_ALMOSTEMPTY 0xffff
1410#define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
1411#define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
1412
1413#define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
1414
1415#define S_ALMOSTFULL 0
1416#define M_ALMOSTFULL 0xffff
1417#define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
1418#define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
1419
1420#define A_ESPI_CALENDAR_LENGTH 0x898
1421#define A_PORT_CONFIG 0x89c
1422
1423#define S_RX_NPORTS 0
1424#define M_RX_NPORTS 0xff
1425#define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)
1426#define G_RX_NPORTS(x) (((x) >> S_RX_NPORTS) & M_RX_NPORTS)
1427
1428#define S_TX_NPORTS 8
1429#define M_TX_NPORTS 0xff
1430#define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)
1431#define G_TX_NPORTS(x) (((x) >> S_TX_NPORTS) & M_TX_NPORTS)
1432
1433#define A_ESPI_FIFO_STATUS_ENABLE 0x8a0
1434
1435#define S_RXSTATUSENABLE 0
1436#define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)
1437#define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U)
1438
1439#define S_TXDROPENABLE 1
1440#define V_TXDROPENABLE(x) ((x) << S_TXDROPENABLE)
1441#define F_TXDROPENABLE V_TXDROPENABLE(1U)
1442
1443#define S_RXENDIANMODE 2
1444#define V_RXENDIANMODE(x) ((x) << S_RXENDIANMODE)
1445#define F_RXENDIANMODE V_RXENDI…Large files files are truncated, but you can click here to view the full file