/drivers/net/bnx2x/bnx2x_init_ops.h
C Header | 866 lines | 661 code | 115 blank | 90 comment | 74 complexity | c54dffc6be988cb24984a4a7b568e358 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/* bnx2x_init_ops.h: Broadcom Everest network driver.
2 * Static functions needed during the initialization.
3 * This file is "included" in bnx2x_main.c.
4 *
5 * Copyright (c) 2007-2011 Broadcom Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
11 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
12 * Written by: Vladislav Zolotarov <vladz@broadcom.com>
13 */
14
15#ifndef BNX2X_INIT_OPS_H
16#define BNX2X_INIT_OPS_H
17
18static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len);
19static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
20static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
21 u32 addr, u32 len);
22
23static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
24 u32 len)
25{
26 u32 i;
27
28 for (i = 0; i < len; i++)
29 REG_WR(bp, addr + i*4, data[i]);
30}
31
32static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
33 u32 len)
34{
35 u32 i;
36
37 for (i = 0; i < len; i++)
38 REG_WR_IND(bp, addr + i*4, data[i]);
39}
40
41static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
42{
43 if (bp->dmae_ready)
44 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
45 else
46 bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
47}
48
49static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
50{
51 u32 buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
52 u32 buf_len32 = buf_len/4;
53 u32 i;
54
55 memset(GUNZIP_BUF(bp), (u8)fill, buf_len);
56
57 for (i = 0; i < len; i += buf_len32) {
58 u32 cur_len = min(buf_len32, len - i);
59
60 bnx2x_write_big_buf(bp, addr + i*4, cur_len);
61 }
62}
63
64static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
65 u32 len64)
66{
67 u32 buf_len32 = FW_BUF_SIZE/4;
68 u32 len = len64*2;
69 u64 data64 = 0;
70 u32 i;
71
72 /* 64 bit value is in a blob: first low DWORD, then high DWORD */
73 data64 = HILO_U64((*(data + 1)), (*data));
74
75 len64 = min((u32)(FW_BUF_SIZE/8), len64);
76 for (i = 0; i < len64; i++) {
77 u64 *pdata = ((u64 *)(GUNZIP_BUF(bp))) + i;
78
79 *pdata = data64;
80 }
81
82 for (i = 0; i < len; i += buf_len32) {
83 u32 cur_len = min(buf_len32, len - i);
84
85 bnx2x_write_big_buf(bp, addr + i*4, cur_len);
86 }
87}
88
89/*********************************************************
90 There are different blobs for each PRAM section.
91 In addition, each blob write operation is divided into a few operations
92 in order to decrease the amount of phys. contiguous buffer needed.
93 Thus, when we select a blob the address may be with some offset
94 from the beginning of PRAM section.
95 The same holds for the INT_TABLE sections.
96**********************************************************/
97#define IF_IS_INT_TABLE_ADDR(base, addr) \
98 if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
99
100#define IF_IS_PRAM_ADDR(base, addr) \
101 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
102
103static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr, const u8 *data)
104{
105 IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
106 data = INIT_TSEM_INT_TABLE_DATA(bp);
107 else
108 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
109 data = INIT_CSEM_INT_TABLE_DATA(bp);
110 else
111 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
112 data = INIT_USEM_INT_TABLE_DATA(bp);
113 else
114 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
115 data = INIT_XSEM_INT_TABLE_DATA(bp);
116 else
117 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
118 data = INIT_TSEM_PRAM_DATA(bp);
119 else
120 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
121 data = INIT_CSEM_PRAM_DATA(bp);
122 else
123 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
124 data = INIT_USEM_PRAM_DATA(bp);
125 else
126 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
127 data = INIT_XSEM_PRAM_DATA(bp);
128
129 return data;
130}
131
132static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len)
133{
134 if (bp->dmae_ready)
135 bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
136 else
137 bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
138}
139
140static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
141 u32 len)
142{
143 const u32 *old_data = data;
144
145 data = (const u32 *)bnx2x_sel_blob(bp, addr, (const u8 *)data);
146
147 if (bp->dmae_ready) {
148 if (old_data != data)
149 VIRT_WR_DMAE_LEN(bp, data, addr, len, 1);
150 else
151 VIRT_WR_DMAE_LEN(bp, data, addr, len, 0);
152 } else
153 bnx2x_init_ind_wr(bp, addr, data, len);
154}
155
156static void bnx2x_wr_64(struct bnx2x *bp, u32 reg, u32 val_lo, u32 val_hi)
157{
158 u32 wb_write[2];
159
160 wb_write[0] = val_lo;
161 wb_write[1] = val_hi;
162 REG_WR_DMAE_LEN(bp, reg, wb_write, 2);
163}
164
165static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len, u32 blob_off)
166{
167 const u8 *data = NULL;
168 int rc;
169 u32 i;
170
171 data = bnx2x_sel_blob(bp, addr, data) + blob_off*4;
172
173 rc = bnx2x_gunzip(bp, data, len);
174 if (rc)
175 return;
176
177 /* gunzip_outlen is in dwords */
178 len = GUNZIP_OUTLEN(bp);
179 for (i = 0; i < len; i++)
180 ((u32 *)GUNZIP_BUF(bp))[i] =
181 cpu_to_le32(((u32 *)GUNZIP_BUF(bp))[i]);
182
183 bnx2x_write_big_buf_wb(bp, addr, len);
184}
185
186static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage)
187{
188 u16 op_start =
189 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, STAGE_START)];
190 u16 op_end =
191 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage, STAGE_END)];
192 union init_op *op;
193 int hw_wr;
194 u32 i, op_type, addr, len;
195 const u32 *data, *data_base;
196
197 /* If empty block */
198 if (op_start == op_end)
199 return;
200
201 if (CHIP_REV_IS_FPGA(bp))
202 hw_wr = OP_WR_FPGA;
203 else if (CHIP_REV_IS_EMUL(bp))
204 hw_wr = OP_WR_EMUL;
205 else
206 hw_wr = OP_WR_ASIC;
207
208 data_base = INIT_DATA(bp);
209
210 for (i = op_start; i < op_end; i++) {
211
212 op = (union init_op *)&(INIT_OPS(bp)[i]);
213
214 op_type = op->str_wr.op;
215 addr = op->str_wr.offset;
216 len = op->str_wr.data_len;
217 data = data_base + op->str_wr.data_off;
218
219 /* HW/EMUL specific */
220 if ((op_type > OP_WB) && (op_type == hw_wr))
221 op_type = OP_WR;
222
223 switch (op_type) {
224 case OP_RD:
225 REG_RD(bp, addr);
226 break;
227 case OP_WR:
228 REG_WR(bp, addr, op->write.val);
229 break;
230 case OP_SW:
231 bnx2x_init_str_wr(bp, addr, data, len);
232 break;
233 case OP_WB:
234 bnx2x_init_wr_wb(bp, addr, data, len);
235 break;
236 case OP_SI:
237 bnx2x_init_ind_wr(bp, addr, data, len);
238 break;
239 case OP_ZR:
240 bnx2x_init_fill(bp, addr, 0, op->zero.len);
241 break;
242 case OP_ZP:
243 bnx2x_init_wr_zp(bp, addr, len,
244 op->str_wr.data_off);
245 break;
246 case OP_WR_64:
247 bnx2x_init_wr_64(bp, addr, data, len);
248 break;
249 default:
250 /* happens whenever an op is of a diff HW */
251 break;
252 }
253 }
254}
255
256
257/****************************************************************************
258* PXP Arbiter
259****************************************************************************/
260/*
261 * This code configures the PCI read/write arbiter
262 * which implements a weighted round robin
263 * between the virtual queues in the chip.
264 *
265 * The values were derived for each PCI max payload and max request size.
266 * since max payload and max request size are only known at run time,
267 * this is done as a separate init stage.
268 */
269
270#define NUM_WR_Q 13
271#define NUM_RD_Q 29
272#define MAX_RD_ORD 3
273#define MAX_WR_ORD 2
274
275/* configuration for one arbiter queue */
276struct arb_line {
277 int l;
278 int add;
279 int ubound;
280};
281
282/* derived configuration for each read queue for each max request size */
283static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
284/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
285 { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
286 { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
287 { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
288 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
289 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
290 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
291 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
292 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
293/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
294 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
295 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
296 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
297 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
298 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
299 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
300 { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
301 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
302 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
303/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
304 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
305 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
306 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
307 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
308 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
309 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
310 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
311 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
312 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
313};
314
315/* derived configuration for each write queue for each max request size */
316static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
317/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
318 { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
319 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
320 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
321 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
322 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
323 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
324 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
325 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
326/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
327 { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
328 { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
329 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
330};
331
332/* register addresses for read queues */
333static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
334/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
335 PXP2_REG_RQ_BW_RD_UBOUND0},
336 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
337 PXP2_REG_PSWRQ_BW_UB1},
338 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
339 PXP2_REG_PSWRQ_BW_UB2},
340 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
341 PXP2_REG_PSWRQ_BW_UB3},
342 {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
343 PXP2_REG_RQ_BW_RD_UBOUND4},
344 {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
345 PXP2_REG_RQ_BW_RD_UBOUND5},
346 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
347 PXP2_REG_PSWRQ_BW_UB6},
348 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
349 PXP2_REG_PSWRQ_BW_UB7},
350 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
351 PXP2_REG_PSWRQ_BW_UB8},
352/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
353 PXP2_REG_PSWRQ_BW_UB9},
354 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
355 PXP2_REG_PSWRQ_BW_UB10},
356 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
357 PXP2_REG_PSWRQ_BW_UB11},
358 {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
359 PXP2_REG_RQ_BW_RD_UBOUND12},
360 {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
361 PXP2_REG_RQ_BW_RD_UBOUND13},
362 {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
363 PXP2_REG_RQ_BW_RD_UBOUND14},
364 {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
365 PXP2_REG_RQ_BW_RD_UBOUND15},
366 {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
367 PXP2_REG_RQ_BW_RD_UBOUND16},
368 {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
369 PXP2_REG_RQ_BW_RD_UBOUND17},
370 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
371 PXP2_REG_RQ_BW_RD_UBOUND18},
372/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
373 PXP2_REG_RQ_BW_RD_UBOUND19},
374 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
375 PXP2_REG_RQ_BW_RD_UBOUND20},
376 {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
377 PXP2_REG_RQ_BW_RD_UBOUND22},
378 {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
379 PXP2_REG_RQ_BW_RD_UBOUND23},
380 {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
381 PXP2_REG_RQ_BW_RD_UBOUND24},
382 {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
383 PXP2_REG_RQ_BW_RD_UBOUND25},
384 {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
385 PXP2_REG_RQ_BW_RD_UBOUND26},
386 {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
387 PXP2_REG_RQ_BW_RD_UBOUND27},
388 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
389 PXP2_REG_PSWRQ_BW_UB28}
390};
391
392/* register addresses for write queues */
393static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
394/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
395 PXP2_REG_PSWRQ_BW_UB1},
396 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
397 PXP2_REG_PSWRQ_BW_UB2},
398 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
399 PXP2_REG_PSWRQ_BW_UB3},
400 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
401 PXP2_REG_PSWRQ_BW_UB6},
402 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
403 PXP2_REG_PSWRQ_BW_UB7},
404 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
405 PXP2_REG_PSWRQ_BW_UB8},
406 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
407 PXP2_REG_PSWRQ_BW_UB9},
408 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
409 PXP2_REG_PSWRQ_BW_UB10},
410 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
411 PXP2_REG_PSWRQ_BW_UB11},
412/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
413 PXP2_REG_PSWRQ_BW_UB28},
414 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
415 PXP2_REG_RQ_BW_WR_UBOUND29},
416 {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
417 PXP2_REG_RQ_BW_WR_UBOUND30}
418};
419
420static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order, int w_order)
421{
422 u32 val, i;
423
424 if (r_order > MAX_RD_ORD) {
425 DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
426 r_order, MAX_RD_ORD);
427 r_order = MAX_RD_ORD;
428 }
429 if (w_order > MAX_WR_ORD) {
430 DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n",
431 w_order, MAX_WR_ORD);
432 w_order = MAX_WR_ORD;
433 }
434 if (CHIP_REV_IS_FPGA(bp)) {
435 DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
436 w_order = 0;
437 }
438 DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
439
440 for (i = 0; i < NUM_RD_Q-1; i++) {
441 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
442 REG_WR(bp, read_arb_addr[i].add,
443 read_arb_data[i][r_order].add);
444 REG_WR(bp, read_arb_addr[i].ubound,
445 read_arb_data[i][r_order].ubound);
446 }
447
448 for (i = 0; i < NUM_WR_Q-1; i++) {
449 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
450 (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
451
452 REG_WR(bp, write_arb_addr[i].l,
453 write_arb_data[i][w_order].l);
454
455 REG_WR(bp, write_arb_addr[i].add,
456 write_arb_data[i][w_order].add);
457
458 REG_WR(bp, write_arb_addr[i].ubound,
459 write_arb_data[i][w_order].ubound);
460 } else {
461
462 val = REG_RD(bp, write_arb_addr[i].l);
463 REG_WR(bp, write_arb_addr[i].l,
464 val | (write_arb_data[i][w_order].l << 10));
465
466 val = REG_RD(bp, write_arb_addr[i].add);
467 REG_WR(bp, write_arb_addr[i].add,
468 val | (write_arb_data[i][w_order].add << 10));
469
470 val = REG_RD(bp, write_arb_addr[i].ubound);
471 REG_WR(bp, write_arb_addr[i].ubound,
472 val | (write_arb_data[i][w_order].ubound << 7));
473 }
474 }
475
476 val = write_arb_data[NUM_WR_Q-1][w_order].add;
477 val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
478 val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
479 REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
480
481 val = read_arb_data[NUM_RD_Q-1][r_order].add;
482 val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
483 val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
484 REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
485
486 REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
487 REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
488 REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
489 REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
490
491 if ((CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) && (r_order == MAX_RD_ORD))
492 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
493
494 if (CHIP_IS_E2(bp))
495 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
496 else
497 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
498
499 if (CHIP_IS_E1H(bp) || CHIP_IS_E2(bp)) {
500 /* MPS w_order optimal TH presently TH
501 * 128 0 0 2
502 * 256 1 1 3
503 * >=512 2 2 3
504 */
505 /* DMAE is special */
506 if (CHIP_IS_E2(bp)) {
507 /* E2 can use optimal TH */
508 val = w_order;
509 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, val);
510 } else {
511 val = ((w_order == 0) ? 2 : 3);
512 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2);
513 }
514
515 REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
516 REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
517 REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
518 REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
519 REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
520 REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
521 REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
522 REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
523 REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
524 REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
525 }
526
527 /* Validate number of tags suppoted by device */
528#define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980
529 val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST);
530 val &= 0xFF;
531 if (val <= 0x20)
532 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
533}
534
535/****************************************************************************
536* ILT management
537****************************************************************************/
538/*
539 * This codes hides the low level HW interaction for ILT management and
540 * configuration. The API consists of a shadow ILT table which is set by the
541 * driver and a set of routines to use it to configure the HW.
542 *
543 */
544
545/* ILT HW init operations */
546
547/* ILT memory management operations */
548#define ILT_MEMOP_ALLOC 0
549#define ILT_MEMOP_FREE 1
550
551/* the phys address is shifted right 12 bits and has an added
552 * 1=valid bit added to the 53rd bit
553 * then since this is a wide register(TM)
554 * we split it into two 32 bit writes
555 */
556#define ILT_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
557#define ILT_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
558#define ILT_RANGE(f, l) (((l) << 10) | f)
559
560static int bnx2x_ilt_line_mem_op(struct bnx2x *bp, struct ilt_line *line,
561 u32 size, u8 memop)
562{
563 if (memop == ILT_MEMOP_FREE) {
564 BNX2X_ILT_FREE(line->page, line->page_mapping, line->size);
565 return 0;
566 }
567 BNX2X_ILT_ZALLOC(line->page, &line->page_mapping, size);
568 if (!line->page)
569 return -1;
570 line->size = size;
571 return 0;
572}
573
574
575static int bnx2x_ilt_client_mem_op(struct bnx2x *bp, int cli_num, u8 memop)
576{
577 int i, rc;
578 struct bnx2x_ilt *ilt = BP_ILT(bp);
579 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
580
581 if (!ilt || !ilt->lines)
582 return -1;
583
584 if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
585 return 0;
586
587 for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
588 rc = bnx2x_ilt_line_mem_op(bp, &ilt->lines[i],
589 ilt_cli->page_size, memop);
590 }
591 return rc;
592}
593
594static int bnx2x_ilt_mem_op(struct bnx2x *bp, u8 memop)
595{
596 int rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_CDU, memop);
597 if (!rc)
598 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_QM, memop);
599 if (!rc)
600 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop);
601 if (!rc)
602 rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_TM, memop);
603
604 return rc;
605}
606
607static void bnx2x_ilt_line_wr(struct bnx2x *bp, int abs_idx,
608 dma_addr_t page_mapping)
609{
610 u32 reg;
611
612 if (CHIP_IS_E1(bp))
613 reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
614 else
615 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
616
617 bnx2x_wr_64(bp, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
618}
619
620static void bnx2x_ilt_line_init_op(struct bnx2x *bp, struct bnx2x_ilt *ilt,
621 int idx, u8 initop)
622{
623 dma_addr_t null_mapping;
624 int abs_idx = ilt->start_line + idx;
625
626
627 switch (initop) {
628 case INITOP_INIT:
629 /* set in the init-value array */
630 case INITOP_SET:
631 bnx2x_ilt_line_wr(bp, abs_idx, ilt->lines[idx].page_mapping);
632 break;
633 case INITOP_CLEAR:
634 null_mapping = 0;
635 bnx2x_ilt_line_wr(bp, abs_idx, null_mapping);
636 break;
637 }
638}
639
640static void bnx2x_ilt_boundry_init_op(struct bnx2x *bp,
641 struct ilt_client_info *ilt_cli,
642 u32 ilt_start, u8 initop)
643{
644 u32 start_reg = 0;
645 u32 end_reg = 0;
646
647 /* The boundary is either SET or INIT,
648 CLEAR => SET and for now SET ~~ INIT */
649
650 /* find the appropriate regs */
651 if (CHIP_IS_E1(bp)) {
652 switch (ilt_cli->client_num) {
653 case ILT_CLIENT_CDU:
654 start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
655 break;
656 case ILT_CLIENT_QM:
657 start_reg = PXP2_REG_PSWRQ_QM0_L2P;
658 break;
659 case ILT_CLIENT_SRC:
660 start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
661 break;
662 case ILT_CLIENT_TM:
663 start_reg = PXP2_REG_PSWRQ_TM0_L2P;
664 break;
665 }
666 REG_WR(bp, start_reg + BP_FUNC(bp)*4,
667 ILT_RANGE((ilt_start + ilt_cli->start),
668 (ilt_start + ilt_cli->end)));
669 } else {
670 switch (ilt_cli->client_num) {
671 case ILT_CLIENT_CDU:
672 start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
673 end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
674 break;
675 case ILT_CLIENT_QM:
676 start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
677 end_reg = PXP2_REG_RQ_QM_LAST_ILT;
678 break;
679 case ILT_CLIENT_SRC:
680 start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
681 end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
682 break;
683 case ILT_CLIENT_TM:
684 start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
685 end_reg = PXP2_REG_RQ_TM_LAST_ILT;
686 break;
687 }
688 REG_WR(bp, start_reg, (ilt_start + ilt_cli->start));
689 REG_WR(bp, end_reg, (ilt_start + ilt_cli->end));
690 }
691}
692
693static void bnx2x_ilt_client_init_op_ilt(struct bnx2x *bp,
694 struct bnx2x_ilt *ilt,
695 struct ilt_client_info *ilt_cli,
696 u8 initop)
697{
698 int i;
699
700 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
701 return;
702
703 for (i = ilt_cli->start; i <= ilt_cli->end; i++)
704 bnx2x_ilt_line_init_op(bp, ilt, i, initop);
705
706 /* init/clear the ILT boundries */
707 bnx2x_ilt_boundry_init_op(bp, ilt_cli, ilt->start_line, initop);
708}
709
710static void bnx2x_ilt_client_init_op(struct bnx2x *bp,
711 struct ilt_client_info *ilt_cli, u8 initop)
712{
713 struct bnx2x_ilt *ilt = BP_ILT(bp);
714
715 bnx2x_ilt_client_init_op_ilt(bp, ilt, ilt_cli, initop);
716}
717
718static void bnx2x_ilt_client_id_init_op(struct bnx2x *bp,
719 int cli_num, u8 initop)
720{
721 struct bnx2x_ilt *ilt = BP_ILT(bp);
722 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
723
724 bnx2x_ilt_client_init_op(bp, ilt_cli, initop);
725}
726
727static void bnx2x_ilt_init_op(struct bnx2x *bp, u8 initop)
728{
729 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_CDU, initop);
730 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_QM, initop);
731 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop);
732 bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_TM, initop);
733}
734
735static void bnx2x_ilt_init_client_psz(struct bnx2x *bp, int cli_num,
736 u32 psz_reg, u8 initop)
737{
738 struct bnx2x_ilt *ilt = BP_ILT(bp);
739 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
740
741 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
742 return;
743
744 switch (initop) {
745 case INITOP_INIT:
746 /* set in the init-value array */
747 case INITOP_SET:
748 REG_WR(bp, psz_reg, ILOG2(ilt_cli->page_size >> 12));
749 break;
750 case INITOP_CLEAR:
751 break;
752 }
753}
754
755/*
756 * called during init common stage, ilt clients should be initialized
757 * prioir to calling this function
758 */
759static void bnx2x_ilt_init_page_size(struct bnx2x *bp, u8 initop)
760{
761 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_CDU,
762 PXP2_REG_RQ_CDU_P_SIZE, initop);
763 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_QM,
764 PXP2_REG_RQ_QM_P_SIZE, initop);
765 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_SRC,
766 PXP2_REG_RQ_SRC_P_SIZE, initop);
767 bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_TM,
768 PXP2_REG_RQ_TM_P_SIZE, initop);
769}
770
771/****************************************************************************
772* QM initializations
773****************************************************************************/
774#define QM_QUEUES_PER_FUNC 16 /* E1 has 32, but only 16 are used */
775#define QM_INIT_MIN_CID_COUNT 31
776#define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT)
777
778/* called during init port stage */
779static void bnx2x_qm_init_cid_count(struct bnx2x *bp, int qm_cid_count,
780 u8 initop)
781{
782 int port = BP_PORT(bp);
783
784 if (QM_INIT(qm_cid_count)) {
785 switch (initop) {
786 case INITOP_INIT:
787 /* set in the init-value array */
788 case INITOP_SET:
789 REG_WR(bp, QM_REG_CONNNUM_0 + port*4,
790 qm_cid_count/16 - 1);
791 break;
792 case INITOP_CLEAR:
793 break;
794 }
795 }
796}
797
798static void bnx2x_qm_set_ptr_table(struct bnx2x *bp, int qm_cid_count)
799{
800 int i;
801 u32 wb_data[2];
802
803 wb_data[0] = wb_data[1] = 0;
804
805 for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {
806 REG_WR(bp, QM_REG_BASEADDR + i*4,
807 qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
808 bnx2x_init_ind_wr(bp, QM_REG_PTRTBL + i*8,
809 wb_data, 2);
810
811 if (CHIP_IS_E1H(bp)) {
812 REG_WR(bp, QM_REG_BASEADDR_EXT_A + i*4,
813 qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
814 bnx2x_init_ind_wr(bp, QM_REG_PTRTBL_EXT_A + i*8,
815 wb_data, 2);
816 }
817 }
818}
819
820/* called during init common stage */
821static void bnx2x_qm_init_ptr_table(struct bnx2x *bp, int qm_cid_count,
822 u8 initop)
823{
824 if (!QM_INIT(qm_cid_count))
825 return;
826
827 switch (initop) {
828 case INITOP_INIT:
829 /* set in the init-value array */
830 case INITOP_SET:
831 bnx2x_qm_set_ptr_table(bp, qm_cid_count);
832 break;
833 case INITOP_CLEAR:
834 break;
835 }
836}
837
838/****************************************************************************
839* SRC initializations
840****************************************************************************/
841#ifdef BCM_CNIC
842/* called during init func stage */
843static void bnx2x_src_init_t2(struct bnx2x *bp, struct src_ent *t2,
844 dma_addr_t t2_mapping, int src_cid_count)
845{
846 int i;
847 int port = BP_PORT(bp);
848
849 /* Initialize T2 */
850 for (i = 0; i < src_cid_count-1; i++)
851 t2[i].next = (u64)(t2_mapping + (i+1)*sizeof(struct src_ent));
852
853 /* tell the searcher where the T2 table is */
854 REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
855
856 bnx2x_wr_64(bp, SRC_REG_FIRSTFREE0 + port*16,
857 U64_LO(t2_mapping), U64_HI(t2_mapping));
858
859 bnx2x_wr_64(bp, SRC_REG_LASTFREE0 + port*16,
860 U64_LO((u64)t2_mapping +
861 (src_cid_count-1) * sizeof(struct src_ent)),
862 U64_HI((u64)t2_mapping +
863 (src_cid_count-1) * sizeof(struct src_ent)));
864}
865#endif
866#endif /* BNX2X_INIT_OPS_H */