/drivers/net/bna/bna_txrx.c

https://bitbucket.org/slukk/jb-tsm-kernel-4.2 · C · 4185 lines · 3204 code · 696 blank · 285 comment · 312 complexity · c8af6c0c5ef9c147e562447b9d878faa MD5 · raw file

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  1. /*
  2. * Linux network driver for Brocade Converged Network Adapter.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License (GPL) Version 2 as
  6. * published by the Free Software Foundation
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. */
  13. /*
  14. * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  15. * All rights reserved
  16. * www.brocade.com
  17. */
  18. #include "bna.h"
  19. #include "bfa_sm.h"
  20. #include "bfi.h"
  21. /**
  22. * IB
  23. */
  24. #define bna_ib_find_free_ibidx(_mask, _pos)\
  25. do {\
  26. (_pos) = 0;\
  27. while (((_pos) < (BFI_IBIDX_MAX_SEGSIZE)) &&\
  28. ((1 << (_pos)) & (_mask)))\
  29. (_pos)++;\
  30. } while (0)
  31. #define bna_ib_count_ibidx(_mask, _count)\
  32. do {\
  33. int pos = 0;\
  34. (_count) = 0;\
  35. while (pos < (BFI_IBIDX_MAX_SEGSIZE)) {\
  36. if ((1 << pos) & (_mask))\
  37. (_count) = pos + 1;\
  38. pos++;\
  39. } \
  40. } while (0)
  41. #define bna_ib_select_segpool(_count, _q_idx)\
  42. do {\
  43. int i;\
  44. (_q_idx) = -1;\
  45. for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {\
  46. if ((_count <= ibidx_pool[i].pool_entry_size)) {\
  47. (_q_idx) = i;\
  48. break;\
  49. } \
  50. } \
  51. } while (0)
  52. struct bna_ibidx_pool {
  53. int pool_size;
  54. int pool_entry_size;
  55. };
  56. init_ibidx_pool(ibidx_pool);
  57. static struct bna_intr *
  58. bna_intr_get(struct bna_ib_mod *ib_mod, enum bna_intr_type intr_type,
  59. int vector)
  60. {
  61. struct bna_intr *intr;
  62. struct list_head *qe;
  63. list_for_each(qe, &ib_mod->intr_active_q) {
  64. intr = (struct bna_intr *)qe;
  65. if ((intr->intr_type == intr_type) &&
  66. (intr->vector == vector)) {
  67. intr->ref_count++;
  68. return intr;
  69. }
  70. }
  71. if (list_empty(&ib_mod->intr_free_q))
  72. return NULL;
  73. bfa_q_deq(&ib_mod->intr_free_q, &intr);
  74. bfa_q_qe_init(&intr->qe);
  75. intr->ref_count = 1;
  76. intr->intr_type = intr_type;
  77. intr->vector = vector;
  78. list_add_tail(&intr->qe, &ib_mod->intr_active_q);
  79. return intr;
  80. }
  81. static void
  82. bna_intr_put(struct bna_ib_mod *ib_mod,
  83. struct bna_intr *intr)
  84. {
  85. intr->ref_count--;
  86. if (intr->ref_count == 0) {
  87. intr->ib = NULL;
  88. list_del(&intr->qe);
  89. bfa_q_qe_init(&intr->qe);
  90. list_add_tail(&intr->qe, &ib_mod->intr_free_q);
  91. }
  92. }
  93. void
  94. bna_ib_mod_init(struct bna_ib_mod *ib_mod, struct bna *bna,
  95. struct bna_res_info *res_info)
  96. {
  97. int i;
  98. int j;
  99. int count;
  100. u8 offset;
  101. struct bna_doorbell_qset *qset;
  102. unsigned long off;
  103. ib_mod->bna = bna;
  104. ib_mod->ib = (struct bna_ib *)
  105. res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mdl[0].kva;
  106. ib_mod->intr = (struct bna_intr *)
  107. res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mdl[0].kva;
  108. ib_mod->idx_seg = (struct bna_ibidx_seg *)
  109. res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mdl[0].kva;
  110. INIT_LIST_HEAD(&ib_mod->ib_free_q);
  111. INIT_LIST_HEAD(&ib_mod->intr_free_q);
  112. INIT_LIST_HEAD(&ib_mod->intr_active_q);
  113. for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++)
  114. INIT_LIST_HEAD(&ib_mod->ibidx_seg_pool[i]);
  115. for (i = 0; i < BFI_MAX_IB; i++) {
  116. ib_mod->ib[i].ib_id = i;
  117. ib_mod->ib[i].ib_seg_host_addr_kva =
  118. res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  119. ib_mod->ib[i].ib_seg_host_addr.lsb =
  120. res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  121. ib_mod->ib[i].ib_seg_host_addr.msb =
  122. res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  123. qset = (struct bna_doorbell_qset *)0;
  124. off = (unsigned long)(&qset[i >> 1].ib0[(i & 0x1)
  125. * (0x20 >> 2)]);
  126. ib_mod->ib[i].door_bell.doorbell_addr = off +
  127. BNA_GET_DOORBELL_BASE_ADDR(bna->pcidev.pci_bar_kva);
  128. bfa_q_qe_init(&ib_mod->ib[i].qe);
  129. list_add_tail(&ib_mod->ib[i].qe, &ib_mod->ib_free_q);
  130. bfa_q_qe_init(&ib_mod->intr[i].qe);
  131. list_add_tail(&ib_mod->intr[i].qe, &ib_mod->intr_free_q);
  132. }
  133. count = 0;
  134. offset = 0;
  135. for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {
  136. for (j = 0; j < ibidx_pool[i].pool_size; j++) {
  137. bfa_q_qe_init(&ib_mod->idx_seg[count]);
  138. ib_mod->idx_seg[count].ib_seg_size =
  139. ibidx_pool[i].pool_entry_size;
  140. ib_mod->idx_seg[count].ib_idx_tbl_offset = offset;
  141. list_add_tail(&ib_mod->idx_seg[count].qe,
  142. &ib_mod->ibidx_seg_pool[i]);
  143. count++;
  144. offset += ibidx_pool[i].pool_entry_size;
  145. }
  146. }
  147. }
  148. void
  149. bna_ib_mod_uninit(struct bna_ib_mod *ib_mod)
  150. {
  151. int i;
  152. int j;
  153. struct list_head *qe;
  154. i = 0;
  155. list_for_each(qe, &ib_mod->ib_free_q)
  156. i++;
  157. i = 0;
  158. list_for_each(qe, &ib_mod->intr_free_q)
  159. i++;
  160. for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {
  161. j = 0;
  162. list_for_each(qe, &ib_mod->ibidx_seg_pool[i])
  163. j++;
  164. }
  165. ib_mod->bna = NULL;
  166. }
  167. static struct bna_ib *
  168. bna_ib_get(struct bna_ib_mod *ib_mod,
  169. enum bna_intr_type intr_type,
  170. int vector)
  171. {
  172. struct bna_ib *ib;
  173. struct bna_intr *intr;
  174. if (intr_type == BNA_INTR_T_INTX)
  175. vector = (1 << vector);
  176. intr = bna_intr_get(ib_mod, intr_type, vector);
  177. if (intr == NULL)
  178. return NULL;
  179. if (intr->ib) {
  180. if (intr->ib->ref_count == BFI_IBIDX_MAX_SEGSIZE) {
  181. bna_intr_put(ib_mod, intr);
  182. return NULL;
  183. }
  184. intr->ib->ref_count++;
  185. return intr->ib;
  186. }
  187. if (list_empty(&ib_mod->ib_free_q)) {
  188. bna_intr_put(ib_mod, intr);
  189. return NULL;
  190. }
  191. bfa_q_deq(&ib_mod->ib_free_q, &ib);
  192. bfa_q_qe_init(&ib->qe);
  193. ib->ref_count = 1;
  194. ib->start_count = 0;
  195. ib->idx_mask = 0;
  196. ib->intr = intr;
  197. ib->idx_seg = NULL;
  198. intr->ib = ib;
  199. ib->bna = ib_mod->bna;
  200. return ib;
  201. }
  202. static void
  203. bna_ib_put(struct bna_ib_mod *ib_mod, struct bna_ib *ib)
  204. {
  205. bna_intr_put(ib_mod, ib->intr);
  206. ib->ref_count--;
  207. if (ib->ref_count == 0) {
  208. ib->intr = NULL;
  209. ib->bna = NULL;
  210. list_add_tail(&ib->qe, &ib_mod->ib_free_q);
  211. }
  212. }
  213. /* Returns index offset - starting from 0 */
  214. static int
  215. bna_ib_reserve_idx(struct bna_ib *ib)
  216. {
  217. struct bna_ib_mod *ib_mod = &ib->bna->ib_mod;
  218. struct bna_ibidx_seg *idx_seg;
  219. int idx;
  220. int num_idx;
  221. int q_idx;
  222. /* Find the first free index position */
  223. bna_ib_find_free_ibidx(ib->idx_mask, idx);
  224. if (idx == BFI_IBIDX_MAX_SEGSIZE)
  225. return -1;
  226. /*
  227. * Calculate the total number of indexes held by this IB,
  228. * including the index newly reserved above.
  229. */
  230. bna_ib_count_ibidx((ib->idx_mask | (1 << idx)), num_idx);
  231. /* See if there is a free space in the index segment held by this IB */
  232. if (ib->idx_seg && (num_idx <= ib->idx_seg->ib_seg_size)) {
  233. ib->idx_mask |= (1 << idx);
  234. return idx;
  235. }
  236. if (ib->start_count)
  237. return -1;
  238. /* Allocate a new segment */
  239. bna_ib_select_segpool(num_idx, q_idx);
  240. while (1) {
  241. if (q_idx == BFI_IBIDX_TOTAL_POOLS)
  242. return -1;
  243. if (!list_empty(&ib_mod->ibidx_seg_pool[q_idx]))
  244. break;
  245. q_idx++;
  246. }
  247. bfa_q_deq(&ib_mod->ibidx_seg_pool[q_idx], &idx_seg);
  248. bfa_q_qe_init(&idx_seg->qe);
  249. /* Free the old segment */
  250. if (ib->idx_seg) {
  251. bna_ib_select_segpool(ib->idx_seg->ib_seg_size, q_idx);
  252. list_add_tail(&ib->idx_seg->qe, &ib_mod->ibidx_seg_pool[q_idx]);
  253. }
  254. ib->idx_seg = idx_seg;
  255. ib->idx_mask |= (1 << idx);
  256. return idx;
  257. }
  258. static void
  259. bna_ib_release_idx(struct bna_ib *ib, int idx)
  260. {
  261. struct bna_ib_mod *ib_mod = &ib->bna->ib_mod;
  262. struct bna_ibidx_seg *idx_seg;
  263. int num_idx;
  264. int cur_q_idx;
  265. int new_q_idx;
  266. ib->idx_mask &= ~(1 << idx);
  267. if (ib->start_count)
  268. return;
  269. bna_ib_count_ibidx(ib->idx_mask, num_idx);
  270. /*
  271. * Free the segment, if there are no more indexes in the segment
  272. * held by this IB
  273. */
  274. if (!num_idx) {
  275. bna_ib_select_segpool(ib->idx_seg->ib_seg_size, cur_q_idx);
  276. list_add_tail(&ib->idx_seg->qe,
  277. &ib_mod->ibidx_seg_pool[cur_q_idx]);
  278. ib->idx_seg = NULL;
  279. return;
  280. }
  281. /* See if we can move to a smaller segment */
  282. bna_ib_select_segpool(num_idx, new_q_idx);
  283. bna_ib_select_segpool(ib->idx_seg->ib_seg_size, cur_q_idx);
  284. while (new_q_idx < cur_q_idx) {
  285. if (!list_empty(&ib_mod->ibidx_seg_pool[new_q_idx]))
  286. break;
  287. new_q_idx++;
  288. }
  289. if (new_q_idx < cur_q_idx) {
  290. /* Select the new smaller segment */
  291. bfa_q_deq(&ib_mod->ibidx_seg_pool[new_q_idx], &idx_seg);
  292. bfa_q_qe_init(&idx_seg->qe);
  293. /* Free the old segment */
  294. list_add_tail(&ib->idx_seg->qe,
  295. &ib_mod->ibidx_seg_pool[cur_q_idx]);
  296. ib->idx_seg = idx_seg;
  297. }
  298. }
  299. static int
  300. bna_ib_config(struct bna_ib *ib, struct bna_ib_config *ib_config)
  301. {
  302. if (ib->start_count)
  303. return -1;
  304. ib->ib_config.coalescing_timeo = ib_config->coalescing_timeo;
  305. ib->ib_config.interpkt_timeo = ib_config->interpkt_timeo;
  306. ib->ib_config.interpkt_count = ib_config->interpkt_count;
  307. ib->ib_config.ctrl_flags = ib_config->ctrl_flags;
  308. ib->ib_config.ctrl_flags |= BFI_IB_CF_MASTER_ENABLE;
  309. if (ib->intr->intr_type == BNA_INTR_T_MSIX)
  310. ib->ib_config.ctrl_flags |= BFI_IB_CF_MSIX_MODE;
  311. return 0;
  312. }
  313. static void
  314. bna_ib_start(struct bna_ib *ib)
  315. {
  316. struct bna_ib_blk_mem ib_cfg;
  317. struct bna_ib_blk_mem *ib_mem;
  318. u32 pg_num;
  319. u32 intx_mask;
  320. int i;
  321. void __iomem *base_addr;
  322. unsigned long off;
  323. ib->start_count++;
  324. if (ib->start_count > 1)
  325. return;
  326. ib_cfg.host_addr_lo = (u32)(ib->ib_seg_host_addr.lsb);
  327. ib_cfg.host_addr_hi = (u32)(ib->ib_seg_host_addr.msb);
  328. ib_cfg.clsc_n_ctrl_n_msix = (((u32)
  329. ib->ib_config.coalescing_timeo << 16) |
  330. ((u32)ib->ib_config.ctrl_flags << 8) |
  331. (ib->intr->vector));
  332. ib_cfg.ipkt_n_ent_n_idxof =
  333. ((u32)
  334. (ib->ib_config.interpkt_timeo & 0xf) << 16) |
  335. ((u32)ib->idx_seg->ib_seg_size << 8) |
  336. (ib->idx_seg->ib_idx_tbl_offset);
  337. ib_cfg.ipkt_cnt_cfg_n_unacked = ((u32)
  338. ib->ib_config.interpkt_count << 24);
  339. pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + ib->bna->port_num,
  340. HQM_IB_RAM_BASE_OFFSET);
  341. writel(pg_num, ib->bna->regs.page_addr);
  342. base_addr = BNA_GET_MEM_BASE_ADDR(ib->bna->pcidev.pci_bar_kva,
  343. HQM_IB_RAM_BASE_OFFSET);
  344. ib_mem = (struct bna_ib_blk_mem *)0;
  345. off = (unsigned long)&ib_mem[ib->ib_id].host_addr_lo;
  346. writel(htonl(ib_cfg.host_addr_lo), base_addr + off);
  347. off = (unsigned long)&ib_mem[ib->ib_id].host_addr_hi;
  348. writel(htonl(ib_cfg.host_addr_hi), base_addr + off);
  349. off = (unsigned long)&ib_mem[ib->ib_id].clsc_n_ctrl_n_msix;
  350. writel(ib_cfg.clsc_n_ctrl_n_msix, base_addr + off);
  351. off = (unsigned long)&ib_mem[ib->ib_id].ipkt_n_ent_n_idxof;
  352. writel(ib_cfg.ipkt_n_ent_n_idxof, base_addr + off);
  353. off = (unsigned long)&ib_mem[ib->ib_id].ipkt_cnt_cfg_n_unacked;
  354. writel(ib_cfg.ipkt_cnt_cfg_n_unacked, base_addr + off);
  355. ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
  356. (u32)ib->ib_config.coalescing_timeo, 0);
  357. pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + ib->bna->port_num,
  358. HQM_INDX_TBL_RAM_BASE_OFFSET);
  359. writel(pg_num, ib->bna->regs.page_addr);
  360. base_addr = BNA_GET_MEM_BASE_ADDR(ib->bna->pcidev.pci_bar_kva,
  361. HQM_INDX_TBL_RAM_BASE_OFFSET);
  362. for (i = 0; i < ib->idx_seg->ib_seg_size; i++) {
  363. off = (unsigned long)
  364. ((ib->idx_seg->ib_idx_tbl_offset + i) * BFI_IBIDX_SIZE);
  365. writel(0, base_addr + off);
  366. }
  367. if (ib->intr->intr_type == BNA_INTR_T_INTX) {
  368. bna_intx_disable(ib->bna, intx_mask);
  369. intx_mask &= ~(ib->intr->vector);
  370. bna_intx_enable(ib->bna, intx_mask);
  371. }
  372. }
  373. static void
  374. bna_ib_stop(struct bna_ib *ib)
  375. {
  376. u32 intx_mask;
  377. ib->start_count--;
  378. if (ib->start_count == 0) {
  379. writel(BNA_DOORBELL_IB_INT_DISABLE,
  380. ib->door_bell.doorbell_addr);
  381. if (ib->intr->intr_type == BNA_INTR_T_INTX) {
  382. bna_intx_disable(ib->bna, intx_mask);
  383. intx_mask |= (ib->intr->vector);
  384. bna_intx_enable(ib->bna, intx_mask);
  385. }
  386. }
  387. }
  388. static void
  389. bna_ib_fail(struct bna_ib *ib)
  390. {
  391. ib->start_count = 0;
  392. }
  393. /**
  394. * RXF
  395. */
  396. static void rxf_enable(struct bna_rxf *rxf);
  397. static void rxf_disable(struct bna_rxf *rxf);
  398. static void __rxf_config_set(struct bna_rxf *rxf);
  399. static void __rxf_rit_set(struct bna_rxf *rxf);
  400. static void __bna_rxf_stat_clr(struct bna_rxf *rxf);
  401. static int rxf_process_packet_filter(struct bna_rxf *rxf);
  402. static int rxf_clear_packet_filter(struct bna_rxf *rxf);
  403. static void rxf_reset_packet_filter(struct bna_rxf *rxf);
  404. static void rxf_cb_enabled(void *arg, int status);
  405. static void rxf_cb_disabled(void *arg, int status);
  406. static void bna_rxf_cb_stats_cleared(void *arg, int status);
  407. static void __rxf_enable(struct bna_rxf *rxf);
  408. static void __rxf_disable(struct bna_rxf *rxf);
  409. bfa_fsm_state_decl(bna_rxf, stopped, struct bna_rxf,
  410. enum bna_rxf_event);
  411. bfa_fsm_state_decl(bna_rxf, start_wait, struct bna_rxf,
  412. enum bna_rxf_event);
  413. bfa_fsm_state_decl(bna_rxf, cam_fltr_mod_wait, struct bna_rxf,
  414. enum bna_rxf_event);
  415. bfa_fsm_state_decl(bna_rxf, started, struct bna_rxf,
  416. enum bna_rxf_event);
  417. bfa_fsm_state_decl(bna_rxf, cam_fltr_clr_wait, struct bna_rxf,
  418. enum bna_rxf_event);
  419. bfa_fsm_state_decl(bna_rxf, stop_wait, struct bna_rxf,
  420. enum bna_rxf_event);
  421. bfa_fsm_state_decl(bna_rxf, pause_wait, struct bna_rxf,
  422. enum bna_rxf_event);
  423. bfa_fsm_state_decl(bna_rxf, resume_wait, struct bna_rxf,
  424. enum bna_rxf_event);
  425. bfa_fsm_state_decl(bna_rxf, stat_clr_wait, struct bna_rxf,
  426. enum bna_rxf_event);
  427. static struct bfa_sm_table rxf_sm_table[] = {
  428. {BFA_SM(bna_rxf_sm_stopped), BNA_RXF_STOPPED},
  429. {BFA_SM(bna_rxf_sm_start_wait), BNA_RXF_START_WAIT},
  430. {BFA_SM(bna_rxf_sm_cam_fltr_mod_wait), BNA_RXF_CAM_FLTR_MOD_WAIT},
  431. {BFA_SM(bna_rxf_sm_started), BNA_RXF_STARTED},
  432. {BFA_SM(bna_rxf_sm_cam_fltr_clr_wait), BNA_RXF_CAM_FLTR_CLR_WAIT},
  433. {BFA_SM(bna_rxf_sm_stop_wait), BNA_RXF_STOP_WAIT},
  434. {BFA_SM(bna_rxf_sm_pause_wait), BNA_RXF_PAUSE_WAIT},
  435. {BFA_SM(bna_rxf_sm_resume_wait), BNA_RXF_RESUME_WAIT},
  436. {BFA_SM(bna_rxf_sm_stat_clr_wait), BNA_RXF_STAT_CLR_WAIT}
  437. };
  438. static void
  439. bna_rxf_sm_stopped_entry(struct bna_rxf *rxf)
  440. {
  441. call_rxf_stop_cbfn(rxf, BNA_CB_SUCCESS);
  442. }
  443. static void
  444. bna_rxf_sm_stopped(struct bna_rxf *rxf, enum bna_rxf_event event)
  445. {
  446. switch (event) {
  447. case RXF_E_START:
  448. bfa_fsm_set_state(rxf, bna_rxf_sm_start_wait);
  449. break;
  450. case RXF_E_STOP:
  451. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  452. break;
  453. case RXF_E_FAIL:
  454. /* No-op */
  455. break;
  456. case RXF_E_CAM_FLTR_MOD:
  457. call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
  458. break;
  459. case RXF_E_STARTED:
  460. case RXF_E_STOPPED:
  461. case RXF_E_CAM_FLTR_RESP:
  462. /**
  463. * These events are received due to flushing of mbox
  464. * when device fails
  465. */
  466. /* No-op */
  467. break;
  468. case RXF_E_PAUSE:
  469. rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED;
  470. call_rxf_pause_cbfn(rxf, BNA_CB_SUCCESS);
  471. break;
  472. case RXF_E_RESUME:
  473. rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING;
  474. call_rxf_resume_cbfn(rxf, BNA_CB_SUCCESS);
  475. break;
  476. default:
  477. bfa_sm_fault(rxf->rx->bna, event);
  478. }
  479. }
  480. static void
  481. bna_rxf_sm_start_wait_entry(struct bna_rxf *rxf)
  482. {
  483. __rxf_config_set(rxf);
  484. __rxf_rit_set(rxf);
  485. rxf_enable(rxf);
  486. }
  487. static void
  488. bna_rxf_sm_start_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  489. {
  490. switch (event) {
  491. case RXF_E_STOP:
  492. /**
  493. * STOP is originated from bnad. When this happens,
  494. * it can not be waiting for filter update
  495. */
  496. call_rxf_start_cbfn(rxf, BNA_CB_INTERRUPT);
  497. bfa_fsm_set_state(rxf, bna_rxf_sm_stop_wait);
  498. break;
  499. case RXF_E_FAIL:
  500. call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
  501. call_rxf_start_cbfn(rxf, BNA_CB_FAIL);
  502. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  503. break;
  504. case RXF_E_CAM_FLTR_MOD:
  505. /* No-op */
  506. break;
  507. case RXF_E_STARTED:
  508. /**
  509. * Force rxf_process_filter() to go through initial
  510. * config
  511. */
  512. if ((rxf->ucast_active_mac != NULL) &&
  513. (rxf->ucast_pending_set == 0))
  514. rxf->ucast_pending_set = 1;
  515. if (rxf->rss_status == BNA_STATUS_T_ENABLED)
  516. rxf->rxf_flags |= BNA_RXF_FL_RSS_CONFIG_PENDING;
  517. rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
  518. bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_mod_wait);
  519. break;
  520. case RXF_E_PAUSE:
  521. case RXF_E_RESUME:
  522. rxf->rxf_flags |= BNA_RXF_FL_OPERSTATE_CHANGED;
  523. break;
  524. default:
  525. bfa_sm_fault(rxf->rx->bna, event);
  526. }
  527. }
  528. static void
  529. bna_rxf_sm_cam_fltr_mod_wait_entry(struct bna_rxf *rxf)
  530. {
  531. if (!rxf_process_packet_filter(rxf)) {
  532. /* No more pending CAM entries to update */
  533. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  534. }
  535. }
  536. static void
  537. bna_rxf_sm_cam_fltr_mod_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  538. {
  539. switch (event) {
  540. case RXF_E_STOP:
  541. /**
  542. * STOP is originated from bnad. When this happens,
  543. * it can not be waiting for filter update
  544. */
  545. call_rxf_start_cbfn(rxf, BNA_CB_INTERRUPT);
  546. bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_clr_wait);
  547. break;
  548. case RXF_E_FAIL:
  549. rxf_reset_packet_filter(rxf);
  550. call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
  551. call_rxf_start_cbfn(rxf, BNA_CB_FAIL);
  552. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  553. break;
  554. case RXF_E_CAM_FLTR_MOD:
  555. /* No-op */
  556. break;
  557. case RXF_E_CAM_FLTR_RESP:
  558. if (!rxf_process_packet_filter(rxf)) {
  559. /* No more pending CAM entries to update */
  560. call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
  561. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  562. }
  563. break;
  564. case RXF_E_PAUSE:
  565. case RXF_E_RESUME:
  566. rxf->rxf_flags |= BNA_RXF_FL_OPERSTATE_CHANGED;
  567. break;
  568. default:
  569. bfa_sm_fault(rxf->rx->bna, event);
  570. }
  571. }
  572. static void
  573. bna_rxf_sm_started_entry(struct bna_rxf *rxf)
  574. {
  575. call_rxf_start_cbfn(rxf, BNA_CB_SUCCESS);
  576. if (rxf->rxf_flags & BNA_RXF_FL_OPERSTATE_CHANGED) {
  577. if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED)
  578. bfa_fsm_send_event(rxf, RXF_E_PAUSE);
  579. else
  580. bfa_fsm_send_event(rxf, RXF_E_RESUME);
  581. }
  582. }
  583. static void
  584. bna_rxf_sm_started(struct bna_rxf *rxf, enum bna_rxf_event event)
  585. {
  586. switch (event) {
  587. case RXF_E_STOP:
  588. bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_clr_wait);
  589. /* Hack to get FSM start clearing CAM entries */
  590. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_RESP);
  591. break;
  592. case RXF_E_FAIL:
  593. rxf_reset_packet_filter(rxf);
  594. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  595. break;
  596. case RXF_E_CAM_FLTR_MOD:
  597. bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_mod_wait);
  598. break;
  599. case RXF_E_PAUSE:
  600. bfa_fsm_set_state(rxf, bna_rxf_sm_pause_wait);
  601. break;
  602. case RXF_E_RESUME:
  603. bfa_fsm_set_state(rxf, bna_rxf_sm_resume_wait);
  604. break;
  605. default:
  606. bfa_sm_fault(rxf->rx->bna, event);
  607. }
  608. }
  609. static void
  610. bna_rxf_sm_cam_fltr_clr_wait_entry(struct bna_rxf *rxf)
  611. {
  612. /**
  613. * Note: Do not add rxf_clear_packet_filter here.
  614. * It will overstep mbox when this transition happens:
  615. * cam_fltr_mod_wait -> cam_fltr_clr_wait on RXF_E_STOP event
  616. */
  617. }
  618. static void
  619. bna_rxf_sm_cam_fltr_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  620. {
  621. switch (event) {
  622. case RXF_E_FAIL:
  623. /**
  624. * FSM was in the process of stopping, initiated by
  625. * bnad. When this happens, no one can be waiting for
  626. * start or filter update
  627. */
  628. rxf_reset_packet_filter(rxf);
  629. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  630. break;
  631. case RXF_E_CAM_FLTR_RESP:
  632. if (!rxf_clear_packet_filter(rxf)) {
  633. /* No more pending CAM entries to clear */
  634. bfa_fsm_set_state(rxf, bna_rxf_sm_stop_wait);
  635. rxf_disable(rxf);
  636. }
  637. break;
  638. default:
  639. bfa_sm_fault(rxf->rx->bna, event);
  640. }
  641. }
  642. static void
  643. bna_rxf_sm_stop_wait_entry(struct bna_rxf *rxf)
  644. {
  645. /**
  646. * NOTE: Do not add rxf_disable here.
  647. * It will overstep mbox when this transition happens:
  648. * start_wait -> stop_wait on RXF_E_STOP event
  649. */
  650. }
  651. static void
  652. bna_rxf_sm_stop_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  653. {
  654. switch (event) {
  655. case RXF_E_FAIL:
  656. /**
  657. * FSM was in the process of stopping, initiated by
  658. * bnad. When this happens, no one can be waiting for
  659. * start or filter update
  660. */
  661. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  662. break;
  663. case RXF_E_STARTED:
  664. /**
  665. * This event is received due to abrupt transition from
  666. * bna_rxf_sm_start_wait state on receiving
  667. * RXF_E_STOP event
  668. */
  669. rxf_disable(rxf);
  670. break;
  671. case RXF_E_STOPPED:
  672. /**
  673. * FSM was in the process of stopping, initiated by
  674. * bnad. When this happens, no one can be waiting for
  675. * start or filter update
  676. */
  677. bfa_fsm_set_state(rxf, bna_rxf_sm_stat_clr_wait);
  678. break;
  679. case RXF_E_PAUSE:
  680. rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED;
  681. break;
  682. case RXF_E_RESUME:
  683. rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING;
  684. break;
  685. default:
  686. bfa_sm_fault(rxf->rx->bna, event);
  687. }
  688. }
  689. static void
  690. bna_rxf_sm_pause_wait_entry(struct bna_rxf *rxf)
  691. {
  692. rxf->rxf_flags &=
  693. ~(BNA_RXF_FL_OPERSTATE_CHANGED | BNA_RXF_FL_RXF_ENABLED);
  694. __rxf_disable(rxf);
  695. }
  696. static void
  697. bna_rxf_sm_pause_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  698. {
  699. switch (event) {
  700. case RXF_E_FAIL:
  701. /**
  702. * FSM was in the process of disabling rxf, initiated by
  703. * bnad.
  704. */
  705. call_rxf_pause_cbfn(rxf, BNA_CB_FAIL);
  706. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  707. break;
  708. case RXF_E_STOPPED:
  709. rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED;
  710. call_rxf_pause_cbfn(rxf, BNA_CB_SUCCESS);
  711. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  712. break;
  713. /*
  714. * Since PAUSE/RESUME can only be sent by bnad, we don't expect
  715. * any other event during these states
  716. */
  717. default:
  718. bfa_sm_fault(rxf->rx->bna, event);
  719. }
  720. }
  721. static void
  722. bna_rxf_sm_resume_wait_entry(struct bna_rxf *rxf)
  723. {
  724. rxf->rxf_flags &= ~(BNA_RXF_FL_OPERSTATE_CHANGED);
  725. rxf->rxf_flags |= BNA_RXF_FL_RXF_ENABLED;
  726. __rxf_enable(rxf);
  727. }
  728. static void
  729. bna_rxf_sm_resume_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  730. {
  731. switch (event) {
  732. case RXF_E_FAIL:
  733. /**
  734. * FSM was in the process of disabling rxf, initiated by
  735. * bnad.
  736. */
  737. call_rxf_resume_cbfn(rxf, BNA_CB_FAIL);
  738. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  739. break;
  740. case RXF_E_STARTED:
  741. rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING;
  742. call_rxf_resume_cbfn(rxf, BNA_CB_SUCCESS);
  743. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  744. break;
  745. /*
  746. * Since PAUSE/RESUME can only be sent by bnad, we don't expect
  747. * any other event during these states
  748. */
  749. default:
  750. bfa_sm_fault(rxf->rx->bna, event);
  751. }
  752. }
  753. static void
  754. bna_rxf_sm_stat_clr_wait_entry(struct bna_rxf *rxf)
  755. {
  756. __bna_rxf_stat_clr(rxf);
  757. }
  758. static void
  759. bna_rxf_sm_stat_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  760. {
  761. switch (event) {
  762. case RXF_E_FAIL:
  763. case RXF_E_STAT_CLEARED:
  764. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  765. break;
  766. default:
  767. bfa_sm_fault(rxf->rx->bna, event);
  768. }
  769. }
  770. static void
  771. __rxf_enable(struct bna_rxf *rxf)
  772. {
  773. struct bfi_ll_rxf_multi_req ll_req;
  774. u32 bm[2] = {0, 0};
  775. if (rxf->rxf_id < 32)
  776. bm[0] = 1 << rxf->rxf_id;
  777. else
  778. bm[1] = 1 << (rxf->rxf_id - 32);
  779. bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0);
  780. ll_req.rxf_id_mask[0] = htonl(bm[0]);
  781. ll_req.rxf_id_mask[1] = htonl(bm[1]);
  782. ll_req.enable = 1;
  783. bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req),
  784. rxf_cb_enabled, rxf);
  785. bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
  786. }
  787. static void
  788. __rxf_disable(struct bna_rxf *rxf)
  789. {
  790. struct bfi_ll_rxf_multi_req ll_req;
  791. u32 bm[2] = {0, 0};
  792. if (rxf->rxf_id < 32)
  793. bm[0] = 1 << rxf->rxf_id;
  794. else
  795. bm[1] = 1 << (rxf->rxf_id - 32);
  796. bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0);
  797. ll_req.rxf_id_mask[0] = htonl(bm[0]);
  798. ll_req.rxf_id_mask[1] = htonl(bm[1]);
  799. ll_req.enable = 0;
  800. bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req),
  801. rxf_cb_disabled, rxf);
  802. bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
  803. }
  804. static void
  805. __rxf_config_set(struct bna_rxf *rxf)
  806. {
  807. u32 i;
  808. struct bna_rss_mem *rss_mem;
  809. struct bna_rx_fndb_ram *rx_fndb_ram;
  810. struct bna *bna = rxf->rx->bna;
  811. void __iomem *base_addr;
  812. unsigned long off;
  813. base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
  814. RSS_TABLE_BASE_OFFSET);
  815. rss_mem = (struct bna_rss_mem *)0;
  816. /* Configure RSS if required */
  817. if (rxf->ctrl_flags & BNA_RXF_CF_RSS_ENABLE) {
  818. /* configure RSS Table */
  819. writel(BNA_GET_PAGE_NUM(RAD0_MEM_BLK_BASE_PG_NUM +
  820. bna->port_num, RSS_TABLE_BASE_OFFSET),
  821. bna->regs.page_addr);
  822. /* temporarily disable RSS, while hash value is written */
  823. off = (unsigned long)&rss_mem[0].type_n_hash;
  824. writel(0, base_addr + off);
  825. for (i = 0; i < BFI_RSS_HASH_KEY_LEN; i++) {
  826. off = (unsigned long)
  827. &rss_mem[0].hash_key[(BFI_RSS_HASH_KEY_LEN - 1) - i];
  828. writel(htonl(rxf->rss_cfg.toeplitz_hash_key[i]),
  829. base_addr + off);
  830. }
  831. off = (unsigned long)&rss_mem[0].type_n_hash;
  832. writel(rxf->rss_cfg.hash_type | rxf->rss_cfg.hash_mask,
  833. base_addr + off);
  834. }
  835. /* Configure RxF */
  836. writel(BNA_GET_PAGE_NUM(
  837. LUT0_MEM_BLK_BASE_PG_NUM + (bna->port_num * 2),
  838. RX_FNDB_RAM_BASE_OFFSET),
  839. bna->regs.page_addr);
  840. base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
  841. RX_FNDB_RAM_BASE_OFFSET);
  842. rx_fndb_ram = (struct bna_rx_fndb_ram *)0;
  843. /* We always use RSS table 0 */
  844. off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].rss_prop;
  845. writel(rxf->ctrl_flags & BNA_RXF_CF_RSS_ENABLE,
  846. base_addr + off);
  847. /* small large buffer enable/disable */
  848. off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].size_routing_props;
  849. writel((rxf->ctrl_flags & BNA_RXF_CF_SM_LG_RXQ) | 0x80,
  850. base_addr + off);
  851. /* RIT offset, HDS forced offset, multicast RxQ Id */
  852. off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].rit_hds_mcastq;
  853. writel((rxf->rit_segment->rit_offset << 16) |
  854. (rxf->forced_offset << 8) |
  855. (rxf->hds_cfg.hdr_type & BNA_HDS_FORCED) | rxf->mcast_rxq_id,
  856. base_addr + off);
  857. /*
  858. * default vlan tag, default function enable, strip vlan bytes,
  859. * HDS type, header size
  860. */
  861. off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].control_flags;
  862. writel(((u32)rxf->default_vlan_tag << 16) |
  863. (rxf->ctrl_flags &
  864. (BNA_RXF_CF_DEFAULT_VLAN |
  865. BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE |
  866. BNA_RXF_CF_VLAN_STRIP)) |
  867. (rxf->hds_cfg.hdr_type & ~BNA_HDS_FORCED) |
  868. rxf->hds_cfg.header_size,
  869. base_addr + off);
  870. }
  871. void
  872. __rxf_vlan_filter_set(struct bna_rxf *rxf, enum bna_status status)
  873. {
  874. struct bna *bna = rxf->rx->bna;
  875. int i;
  876. writel(BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
  877. (bna->port_num * 2), VLAN_RAM_BASE_OFFSET),
  878. bna->regs.page_addr);
  879. if (status == BNA_STATUS_T_ENABLED) {
  880. /* enable VLAN filtering on this function */
  881. for (i = 0; i <= BFI_MAX_VLAN / 32; i++) {
  882. writel(rxf->vlan_filter_table[i],
  883. BNA_GET_VLAN_MEM_ENTRY_ADDR
  884. (bna->pcidev.pci_bar_kva, rxf->rxf_id,
  885. i * 32));
  886. }
  887. } else {
  888. /* disable VLAN filtering on this function */
  889. for (i = 0; i <= BFI_MAX_VLAN / 32; i++) {
  890. writel(0xffffffff,
  891. BNA_GET_VLAN_MEM_ENTRY_ADDR
  892. (bna->pcidev.pci_bar_kva, rxf->rxf_id,
  893. i * 32));
  894. }
  895. }
  896. }
  897. static void
  898. __rxf_rit_set(struct bna_rxf *rxf)
  899. {
  900. struct bna *bna = rxf->rx->bna;
  901. struct bna_rit_mem *rit_mem;
  902. int i;
  903. void __iomem *base_addr;
  904. unsigned long off;
  905. base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
  906. FUNCTION_TO_RXQ_TRANSLATE);
  907. rit_mem = (struct bna_rit_mem *)0;
  908. writel(BNA_GET_PAGE_NUM(RXA0_MEM_BLK_BASE_PG_NUM + bna->port_num,
  909. FUNCTION_TO_RXQ_TRANSLATE),
  910. bna->regs.page_addr);
  911. for (i = 0; i < rxf->rit_segment->rit_size; i++) {
  912. off = (unsigned long)&rit_mem[i + rxf->rit_segment->rit_offset];
  913. writel(rxf->rit_segment->rit[i].large_rxq_id << 6 |
  914. rxf->rit_segment->rit[i].small_rxq_id,
  915. base_addr + off);
  916. }
  917. }
  918. static void
  919. __bna_rxf_stat_clr(struct bna_rxf *rxf)
  920. {
  921. struct bfi_ll_stats_req ll_req;
  922. u32 bm[2] = {0, 0};
  923. if (rxf->rxf_id < 32)
  924. bm[0] = 1 << rxf->rxf_id;
  925. else
  926. bm[1] = 1 << (rxf->rxf_id - 32);
  927. bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_CLEAR_REQ, 0);
  928. ll_req.stats_mask = 0;
  929. ll_req.txf_id_mask[0] = 0;
  930. ll_req.txf_id_mask[1] = 0;
  931. ll_req.rxf_id_mask[0] = htonl(bm[0]);
  932. ll_req.rxf_id_mask[1] = htonl(bm[1]);
  933. bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req),
  934. bna_rxf_cb_stats_cleared, rxf);
  935. bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
  936. }
  937. static void
  938. rxf_enable(struct bna_rxf *rxf)
  939. {
  940. if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED)
  941. bfa_fsm_send_event(rxf, RXF_E_STARTED);
  942. else {
  943. rxf->rxf_flags |= BNA_RXF_FL_RXF_ENABLED;
  944. __rxf_enable(rxf);
  945. }
  946. }
  947. static void
  948. rxf_cb_enabled(void *arg, int status)
  949. {
  950. struct bna_rxf *rxf = (struct bna_rxf *)arg;
  951. bfa_q_qe_init(&rxf->mbox_qe.qe);
  952. bfa_fsm_send_event(rxf, RXF_E_STARTED);
  953. }
  954. static void
  955. rxf_disable(struct bna_rxf *rxf)
  956. {
  957. if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED)
  958. bfa_fsm_send_event(rxf, RXF_E_STOPPED);
  959. else
  960. rxf->rxf_flags &= ~BNA_RXF_FL_RXF_ENABLED;
  961. __rxf_disable(rxf);
  962. }
  963. static void
  964. rxf_cb_disabled(void *arg, int status)
  965. {
  966. struct bna_rxf *rxf = (struct bna_rxf *)arg;
  967. bfa_q_qe_init(&rxf->mbox_qe.qe);
  968. bfa_fsm_send_event(rxf, RXF_E_STOPPED);
  969. }
  970. void
  971. rxf_cb_cam_fltr_mbox_cmd(void *arg, int status)
  972. {
  973. struct bna_rxf *rxf = (struct bna_rxf *)arg;
  974. bfa_q_qe_init(&rxf->mbox_qe.qe);
  975. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_RESP);
  976. }
  977. static void
  978. bna_rxf_cb_stats_cleared(void *arg, int status)
  979. {
  980. struct bna_rxf *rxf = (struct bna_rxf *)arg;
  981. bfa_q_qe_init(&rxf->mbox_qe.qe);
  982. bfa_fsm_send_event(rxf, RXF_E_STAT_CLEARED);
  983. }
  984. void
  985. rxf_cam_mbox_cmd(struct bna_rxf *rxf, u8 cmd,
  986. const struct bna_mac *mac_addr)
  987. {
  988. struct bfi_ll_mac_addr_req req;
  989. bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
  990. req.rxf_id = rxf->rxf_id;
  991. memcpy(&req.mac_addr, (void *)&mac_addr->addr, ETH_ALEN);
  992. bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req),
  993. rxf_cb_cam_fltr_mbox_cmd, rxf);
  994. bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
  995. }
  996. static int
  997. rxf_process_packet_filter_mcast(struct bna_rxf *rxf)
  998. {
  999. struct bna_mac *mac = NULL;
  1000. struct list_head *qe;
  1001. /* Add multicast entries */
  1002. if (!list_empty(&rxf->mcast_pending_add_q)) {
  1003. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  1004. bfa_q_qe_init(qe);
  1005. mac = (struct bna_mac *)qe;
  1006. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_ADD_REQ, mac);
  1007. list_add_tail(&mac->qe, &rxf->mcast_active_q);
  1008. return 1;
  1009. }
  1010. /* Delete multicast entries previousely added */
  1011. if (!list_empty(&rxf->mcast_pending_del_q)) {
  1012. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  1013. bfa_q_qe_init(qe);
  1014. mac = (struct bna_mac *)qe;
  1015. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac);
  1016. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  1017. return 1;
  1018. }
  1019. return 0;
  1020. }
  1021. static int
  1022. rxf_process_packet_filter_vlan(struct bna_rxf *rxf)
  1023. {
  1024. /* Apply the VLAN filter */
  1025. if (rxf->rxf_flags & BNA_RXF_FL_VLAN_CONFIG_PENDING) {
  1026. rxf->rxf_flags &= ~BNA_RXF_FL_VLAN_CONFIG_PENDING;
  1027. if (!(rxf->rxmode_active & BNA_RXMODE_PROMISC))
  1028. __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
  1029. }
  1030. /* Apply RSS configuration */
  1031. if (rxf->rxf_flags & BNA_RXF_FL_RSS_CONFIG_PENDING) {
  1032. rxf->rxf_flags &= ~BNA_RXF_FL_RSS_CONFIG_PENDING;
  1033. if (rxf->rss_status == BNA_STATUS_T_DISABLED) {
  1034. /* RSS is being disabled */
  1035. rxf->ctrl_flags &= ~BNA_RXF_CF_RSS_ENABLE;
  1036. __rxf_rit_set(rxf);
  1037. __rxf_config_set(rxf);
  1038. } else {
  1039. /* RSS is being enabled or reconfigured */
  1040. rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE;
  1041. __rxf_rit_set(rxf);
  1042. __rxf_config_set(rxf);
  1043. }
  1044. }
  1045. return 0;
  1046. }
  1047. /**
  1048. * Processes pending ucast, mcast entry addition/deletion and issues mailbox
  1049. * command. Also processes pending filter configuration - promiscuous mode,
  1050. * default mode, allmutli mode and issues mailbox command or directly applies
  1051. * to h/w
  1052. */
  1053. static int
  1054. rxf_process_packet_filter(struct bna_rxf *rxf)
  1055. {
  1056. /* Set the default MAC first */
  1057. if (rxf->ucast_pending_set > 0) {
  1058. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_SET_REQ,
  1059. rxf->ucast_active_mac);
  1060. rxf->ucast_pending_set--;
  1061. return 1;
  1062. }
  1063. if (rxf_process_packet_filter_ucast(rxf))
  1064. return 1;
  1065. if (rxf_process_packet_filter_mcast(rxf))
  1066. return 1;
  1067. if (rxf_process_packet_filter_promisc(rxf))
  1068. return 1;
  1069. if (rxf_process_packet_filter_allmulti(rxf))
  1070. return 1;
  1071. if (rxf_process_packet_filter_vlan(rxf))
  1072. return 1;
  1073. return 0;
  1074. }
  1075. static int
  1076. rxf_clear_packet_filter_mcast(struct bna_rxf *rxf)
  1077. {
  1078. struct bna_mac *mac = NULL;
  1079. struct list_head *qe;
  1080. /* 3. delete pending mcast entries */
  1081. if (!list_empty(&rxf->mcast_pending_del_q)) {
  1082. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  1083. bfa_q_qe_init(qe);
  1084. mac = (struct bna_mac *)qe;
  1085. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac);
  1086. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  1087. return 1;
  1088. }
  1089. /* 4. clear active mcast entries; move them to pending_add_q */
  1090. if (!list_empty(&rxf->mcast_active_q)) {
  1091. bfa_q_deq(&rxf->mcast_active_q, &qe);
  1092. bfa_q_qe_init(qe);
  1093. mac = (struct bna_mac *)qe;
  1094. rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac);
  1095. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  1096. return 1;
  1097. }
  1098. return 0;
  1099. }
  1100. /**
  1101. * In the rxf stop path, processes pending ucast/mcast delete queue and issues
  1102. * the mailbox command. Moves the active ucast/mcast entries to pending add q,
  1103. * so that they are added to CAM again in the rxf start path. Moves the current
  1104. * filter settings - promiscuous, default, allmutli - to pending filter
  1105. * configuration
  1106. */
  1107. static int
  1108. rxf_clear_packet_filter(struct bna_rxf *rxf)
  1109. {
  1110. if (rxf_clear_packet_filter_ucast(rxf))
  1111. return 1;
  1112. if (rxf_clear_packet_filter_mcast(rxf))
  1113. return 1;
  1114. /* 5. clear active default MAC in the CAM */
  1115. if (rxf->ucast_pending_set > 0)
  1116. rxf->ucast_pending_set = 0;
  1117. if (rxf_clear_packet_filter_promisc(rxf))
  1118. return 1;
  1119. if (rxf_clear_packet_filter_allmulti(rxf))
  1120. return 1;
  1121. return 0;
  1122. }
  1123. static void
  1124. rxf_reset_packet_filter_mcast(struct bna_rxf *rxf)
  1125. {
  1126. struct list_head *qe;
  1127. struct bna_mac *mac;
  1128. /* 3. Move active mcast entries to pending_add_q */
  1129. while (!list_empty(&rxf->mcast_active_q)) {
  1130. bfa_q_deq(&rxf->mcast_active_q, &qe);
  1131. bfa_q_qe_init(qe);
  1132. list_add_tail(qe, &rxf->mcast_pending_add_q);
  1133. }
  1134. /* 4. Throw away delete pending mcast entries */
  1135. while (!list_empty(&rxf->mcast_pending_del_q)) {
  1136. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  1137. bfa_q_qe_init(qe);
  1138. mac = (struct bna_mac *)qe;
  1139. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  1140. }
  1141. }
  1142. /**
  1143. * In the rxf fail path, throws away the ucast/mcast entries pending for
  1144. * deletion, moves all active ucast/mcast entries to pending queue so that
  1145. * they are added back to CAM in the rxf start path. Also moves the current
  1146. * filter configuration to pending filter configuration.
  1147. */
  1148. static void
  1149. rxf_reset_packet_filter(struct bna_rxf *rxf)
  1150. {
  1151. rxf_reset_packet_filter_ucast(rxf);
  1152. rxf_reset_packet_filter_mcast(rxf);
  1153. /* 5. Turn off ucast set flag */
  1154. rxf->ucast_pending_set = 0;
  1155. rxf_reset_packet_filter_promisc(rxf);
  1156. rxf_reset_packet_filter_allmulti(rxf);
  1157. }
  1158. static void
  1159. bna_rxf_init(struct bna_rxf *rxf,
  1160. struct bna_rx *rx,
  1161. struct bna_rx_config *q_config)
  1162. {
  1163. struct list_head *qe;
  1164. struct bna_rxp *rxp;
  1165. /* rxf_id is initialized during rx_mod init */
  1166. rxf->rx = rx;
  1167. INIT_LIST_HEAD(&rxf->ucast_pending_add_q);
  1168. INIT_LIST_HEAD(&rxf->ucast_pending_del_q);
  1169. rxf->ucast_pending_set = 0;
  1170. INIT_LIST_HEAD(&rxf->ucast_active_q);
  1171. rxf->ucast_active_mac = NULL;
  1172. INIT_LIST_HEAD(&rxf->mcast_pending_add_q);
  1173. INIT_LIST_HEAD(&rxf->mcast_pending_del_q);
  1174. INIT_LIST_HEAD(&rxf->mcast_active_q);
  1175. bfa_q_qe_init(&rxf->mbox_qe.qe);
  1176. if (q_config->vlan_strip_status == BNA_STATUS_T_ENABLED)
  1177. rxf->ctrl_flags |= BNA_RXF_CF_VLAN_STRIP;
  1178. rxf->rxf_oper_state = (q_config->paused) ?
  1179. BNA_RXF_OPER_STATE_PAUSED : BNA_RXF_OPER_STATE_RUNNING;
  1180. bna_rxf_adv_init(rxf, rx, q_config);
  1181. rxf->rit_segment = bna_rit_mod_seg_get(&rxf->rx->bna->rit_mod,
  1182. q_config->num_paths);
  1183. list_for_each(qe, &rx->rxp_q) {
  1184. rxp = (struct bna_rxp *)qe;
  1185. if (q_config->rxp_type == BNA_RXP_SINGLE)
  1186. rxf->mcast_rxq_id = rxp->rxq.single.only->rxq_id;
  1187. else
  1188. rxf->mcast_rxq_id = rxp->rxq.slr.large->rxq_id;
  1189. break;
  1190. }
  1191. rxf->vlan_filter_status = BNA_STATUS_T_DISABLED;
  1192. memset(rxf->vlan_filter_table, 0,
  1193. (sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32)));
  1194. /* Set up VLAN 0 for pure priority tagged packets */
  1195. rxf->vlan_filter_table[0] |= 1;
  1196. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  1197. }
  1198. static void
  1199. bna_rxf_uninit(struct bna_rxf *rxf)
  1200. {
  1201. struct bna *bna = rxf->rx->bna;
  1202. struct bna_mac *mac;
  1203. bna_rit_mod_seg_put(&rxf->rx->bna->rit_mod, rxf->rit_segment);
  1204. rxf->rit_segment = NULL;
  1205. rxf->ucast_pending_set = 0;
  1206. while (!list_empty(&rxf->ucast_pending_add_q)) {
  1207. bfa_q_deq(&rxf->ucast_pending_add_q, &mac);
  1208. bfa_q_qe_init(&mac->qe);
  1209. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  1210. }
  1211. if (rxf->ucast_active_mac) {
  1212. bfa_q_qe_init(&rxf->ucast_active_mac->qe);
  1213. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod,
  1214. rxf->ucast_active_mac);
  1215. rxf->ucast_active_mac = NULL;
  1216. }
  1217. while (!list_empty(&rxf->mcast_pending_add_q)) {
  1218. bfa_q_deq(&rxf->mcast_pending_add_q, &mac);
  1219. bfa_q_qe_init(&mac->qe);
  1220. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  1221. }
  1222. /* Turn off pending promisc mode */
  1223. if (is_promisc_enable(rxf->rxmode_pending,
  1224. rxf->rxmode_pending_bitmask)) {
  1225. /* system promisc state should be pending */
  1226. BUG_ON(!(bna->rxf_promisc_id == rxf->rxf_id));
  1227. promisc_inactive(rxf->rxmode_pending,
  1228. rxf->rxmode_pending_bitmask);
  1229. bna->rxf_promisc_id = BFI_MAX_RXF;
  1230. }
  1231. /* Promisc mode should not be active */
  1232. BUG_ON(rxf->rxmode_active & BNA_RXMODE_PROMISC);
  1233. /* Turn off pending all-multi mode */
  1234. if (is_allmulti_enable(rxf->rxmode_pending,
  1235. rxf->rxmode_pending_bitmask)) {
  1236. allmulti_inactive(rxf->rxmode_pending,
  1237. rxf->rxmode_pending_bitmask);
  1238. }
  1239. /* Allmulti mode should not be active */
  1240. BUG_ON(rxf->rxmode_active & BNA_RXMODE_ALLMULTI);
  1241. rxf->rx = NULL;
  1242. }
  1243. static void
  1244. bna_rx_cb_rxf_started(struct bna_rx *rx, enum bna_cb_status status)
  1245. {
  1246. bfa_fsm_send_event(rx, RX_E_RXF_STARTED);
  1247. if (rx->rxf.rxf_id < 32)
  1248. rx->bna->rx_mod.rxf_bmap[0] |= ((u32)1 << rx->rxf.rxf_id);
  1249. else
  1250. rx->bna->rx_mod.rxf_bmap[1] |= ((u32)
  1251. 1 << (rx->rxf.rxf_id - 32));
  1252. }
  1253. static void
  1254. bna_rxf_start(struct bna_rxf *rxf)
  1255. {
  1256. rxf->start_cbfn = bna_rx_cb_rxf_started;
  1257. rxf->start_cbarg = rxf->rx;
  1258. rxf->rxf_flags &= ~BNA_RXF_FL_FAILED;
  1259. bfa_fsm_send_event(rxf, RXF_E_START);
  1260. }
  1261. static void
  1262. bna_rx_cb_rxf_stopped(struct bna_rx *rx, enum bna_cb_status status)
  1263. {
  1264. bfa_fsm_send_event(rx, RX_E_RXF_STOPPED);
  1265. if (rx->rxf.rxf_id < 32)
  1266. rx->bna->rx_mod.rxf_bmap[0] &= ~(u32)1 << rx->rxf.rxf_id;
  1267. else
  1268. rx->bna->rx_mod.rxf_bmap[1] &= ~(u32)
  1269. 1 << (rx->rxf.rxf_id - 32);
  1270. }
  1271. static void
  1272. bna_rxf_stop(struct bna_rxf *rxf)
  1273. {
  1274. rxf->stop_cbfn = bna_rx_cb_rxf_stopped;
  1275. rxf->stop_cbarg = rxf->rx;
  1276. bfa_fsm_send_event(rxf, RXF_E_STOP);
  1277. }
  1278. static void
  1279. bna_rxf_fail(struct bna_rxf *rxf)
  1280. {
  1281. rxf->rxf_flags |= BNA_RXF_FL_FAILED;
  1282. bfa_fsm_send_event(rxf, RXF_E_FAIL);
  1283. }
  1284. int
  1285. bna_rxf_state_get(struct bna_rxf *rxf)
  1286. {
  1287. return bfa_sm_to_state(rxf_sm_table, rxf->fsm);
  1288. }
  1289. enum bna_cb_status
  1290. bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac,
  1291. void (*cbfn)(struct bnad *, struct bna_rx *,
  1292. enum bna_cb_status))
  1293. {
  1294. struct bna_rxf *rxf = &rx->rxf;
  1295. if (rxf->ucast_active_mac == NULL) {
  1296. rxf->ucast_active_mac =
  1297. bna_ucam_mod_mac_get(&rxf->rx->bna->ucam_mod);
  1298. if (rxf->ucast_active_mac == NULL)
  1299. return BNA_CB_UCAST_CAM_FULL;
  1300. bfa_q_qe_init(&rxf->ucast_active_mac->qe);
  1301. }
  1302. memcpy(rxf->ucast_active_mac->addr, ucmac, ETH_ALEN);
  1303. rxf->ucast_pending_set++;
  1304. rxf->cam_fltr_cbfn = cbfn;
  1305. rxf->cam_fltr_cbarg = rx->bna->bnad;
  1306. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
  1307. return BNA_CB_SUCCESS;
  1308. }
  1309. enum bna_cb_status
  1310. bna_rx_mcast_add(struct bna_rx *rx, u8 *addr,
  1311. void (*cbfn)(struct bnad *, struct bna_rx *,
  1312. enum bna_cb_status))
  1313. {
  1314. struct bna_rxf *rxf = &rx->rxf;
  1315. struct list_head *qe;
  1316. struct bna_mac *mac;
  1317. /* Check if already added */
  1318. list_for_each(qe, &rxf->mcast_active_q) {
  1319. mac = (struct bna_mac *)qe;
  1320. if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
  1321. if (cbfn)
  1322. (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
  1323. return BNA_CB_SUCCESS;
  1324. }
  1325. }
  1326. /* Check if pending addition */
  1327. list_for_each(qe, &rxf->mcast_pending_add_q) {
  1328. mac = (struct bna_mac *)qe;
  1329. if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
  1330. if (cbfn)
  1331. (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
  1332. return BNA_CB_SUCCESS;
  1333. }
  1334. }
  1335. mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
  1336. if (mac == NULL)
  1337. return BNA_CB_MCAST_LIST_FULL;
  1338. bfa_q_qe_init(&mac->qe);
  1339. memcpy(mac->addr, addr, ETH_ALEN);
  1340. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  1341. rxf->cam_fltr_cbfn = cbfn;
  1342. rxf->cam_fltr_cbarg = rx->bna->bnad;
  1343. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
  1344. return BNA_CB_SUCCESS;
  1345. }
  1346. enum bna_cb_status
  1347. bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mclist,
  1348. void (*cbfn)(struct bnad *, struct bna_rx *,
  1349. enum bna_cb_status))
  1350. {
  1351. struct bna_rxf *rxf = &rx->rxf;
  1352. struct list_head list_head;
  1353. struct list_head *qe;
  1354. u8 *mcaddr;
  1355. struct bna_mac *mac;
  1356. struct bna_mac *mac1;
  1357. int skip;
  1358. int delete;
  1359. int need_hw_config = 0;
  1360. int i;
  1361. /* Allocate nodes */
  1362. INIT_LIST_HEAD(&list_head);
  1363. for (i = 0, mcaddr = mclist; i < count; i++) {
  1364. mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
  1365. if (mac == NULL)
  1366. goto err_return;
  1367. bfa_q_qe_init(&mac->qe);
  1368. memcpy(mac->addr, mcaddr, ETH_ALEN);
  1369. list_add_tail(&mac->qe, &list_head);
  1370. mcaddr += ETH_ALEN;
  1371. }
  1372. /* Schedule for addition */
  1373. while (!list_empty(&list_head)) {
  1374. bfa_q_deq(&list_head, &qe);
  1375. mac = (struct bna_mac *)qe;
  1376. bfa_q_qe_init(&mac->qe);
  1377. skip = 0;
  1378. /* Skip if already added */
  1379. list_for_each(qe, &rxf->mcast_active_q) {
  1380. mac1 = (struct bna_mac *)qe;
  1381. if (BNA_MAC_IS_EQUAL(mac1->addr, mac->addr)) {
  1382. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod,
  1383. mac);
  1384. skip = 1;
  1385. break;
  1386. }
  1387. }
  1388. if (skip)
  1389. continue;
  1390. /* Skip if pending addition */
  1391. list_for_each(qe, &rxf->mcast_pending_add_q) {
  1392. mac1 = (struct bna_mac *)qe;
  1393. if (BNA_MAC_IS_EQUAL(mac1->addr, mac->addr)) {
  1394. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod,
  1395. mac);
  1396. skip = 1;
  1397. break;
  1398. }
  1399. }
  1400. if (skip)
  1401. continue;
  1402. need_hw_config = 1;
  1403. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  1404. }
  1405. /**
  1406. * Delete the entries that are in the pending_add_q but not
  1407. * in the new list
  1408. */
  1409. while (!list_empty(&rxf->mcast_pending_add_q)) {
  1410. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  1411. mac = (struct bna_mac *)qe;
  1412. bfa_q_qe_init(&mac->qe);
  1413. for (i = 0, mcaddr = mclist, delete = 1; i < count; i++) {
  1414. if (BNA_MAC_IS_EQUAL(mcaddr, mac->addr)) {
  1415. delete = 0;
  1416. break;
  1417. }
  1418. mcaddr += ETH_ALEN;
  1419. }
  1420. if (delete)
  1421. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  1422. else
  1423. list_add_tail(&mac->qe, &list_head);
  1424. }
  1425. while (!list_empty(&list_head)) {
  1426. bfa_q_deq(&list_head, &qe);
  1427. mac = (struct bna_mac *)qe;
  1428. bfa_q_qe_init(&mac->qe);
  1429. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  1430. }
  1431. /**
  1432. * Schedule entries for deletion that are in the active_q but not
  1433. * in the new list
  1434. */
  1435. while (!list_empty(&rxf->mcast_active_q)) {
  1436. bfa_q_deq(&rxf->mcast_active_q, &qe);
  1437. mac = (struct bna_mac *)qe;
  1438. bfa_q_qe_init(&mac->qe);
  1439. for (i = 0, mcaddr = mclist, delete = 1; i < count; i++) {
  1440. if (BNA_MAC_IS_EQUAL(mcaddr, mac->addr)) {
  1441. delete = 0;
  1442. break;
  1443. }
  1444. mcaddr += ETH_ALEN;
  1445. }
  1446. if (delete) {
  1447. list_add_tail(&mac->qe, &rxf->mcast_pending_del_q);
  1448. need_hw_config = 1;
  1449. } else {
  1450. list_add_tail(&mac->qe, &list_head);
  1451. }
  1452. }
  1453. while (!list_empty(&list_head)) {
  1454. bfa_q_deq(&list_head, &qe);
  1455. mac = (struct bna_mac *)qe;
  1456. bfa_q_qe_init(&mac->qe);
  1457. list_add_tail(&mac->qe, &rxf->mcast_active_q);
  1458. }
  1459. if (need_hw_config) {
  1460. rxf->cam_fltr_cbfn = cbfn;
  1461. rxf->cam_fltr_cbarg = rx->bna->bnad;
  1462. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
  1463. } else if (cbfn)
  1464. (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
  1465. return BNA_CB_SUCCESS;
  1466. err_return:
  1467. while (!list_empty(&list_head)) {
  1468. bfa_q_deq(&list_head, &qe);
  1469. mac = (struct bna_mac *)qe;
  1470. bfa_q_qe_init(&mac->qe);
  1471. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  1472. }
  1473. return BNA_CB_MCAST_LIST_FULL;
  1474. }
  1475. void
  1476. bna_rx_vlan_add(struct bna_rx *rx, int vlan_id)
  1477. {
  1478. struct bna_rxf *rxf = &rx->rxf;
  1479. int index = (vlan_id >> 5);
  1480. int bit = (1 << (vlan_id & 0x1F));
  1481. rxf->vlan_filter_table[index] |= bit;
  1482. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  1483. rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
  1484. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
  1485. }
  1486. }
  1487. void
  1488. bna_rx_vlan_del(struct bna_rx *rx, int vlan_id)
  1489. {
  1490. struct bna_rxf *rxf = &rx->rxf;
  1491. int index = (vlan_id >> 5);
  1492. int bit = (1 << (vlan_id & 0x1F));
  1493. rxf->vlan_filter_table[index] &= ~bit;
  1494. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  1495. rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
  1496. bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
  1497. }
  1498. }
  1499. /**
  1500. * RX
  1501. */
  1502. #define RXQ_RCB_INIT(q, rxp, qdepth, bna, _id, unmapq_mem) do { \
  1503. struct bna_doorbell_qset *_qset; \
  1504. unsigned long off; \
  1505. (q)->rcb->producer_index = (q)->rcb->consumer_index = 0; \
  1506. (q)->rcb->q_depth = (qdepth); \
  1507. (q)->rcb->unmap_q = unmapq_mem; \
  1508. (q)->rcb->rxq = (q); \
  1509. (q)->rcb->cq = &(rxp)->cq; \
  1510. (q)->rcb->bnad = (bna)->bnad; \
  1511. _qset = (struct bna_doorbell_qset *)0; \
  1512. off = (unsigned long)&_qset[(q)->rxq_id].rxq[0]; \
  1513. (q)->rcb->q_dbell = off + \
  1514. BNA_GET_DOORBELL_BASE_ADDR((bna)->pcidev.pci_bar_kva); \
  1515. (q)->rcb->id = _id; \
  1516. } while (0)
  1517. #define BNA_GET_RXQS(qcfg) (((qcfg)->rxp_type == BNA_RXP_SINGLE) ? \
  1518. (qcfg)->num_paths : ((qcfg)->num_paths * 2))
  1519. #define SIZE_TO_PAGES(size) (((size) >> PAGE_SHIFT) + ((((size) &\
  1520. (PAGE_SIZE - 1)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT))
  1521. #define call_rx_stop_callback(rx, status) \
  1522. if ((rx)->stop_cbfn) { \
  1523. (*(rx)->stop_cbfn)((rx)->stop_cbarg, rx, (status)); \
  1524. (rx)->stop_cbfn = NULL; \
  1525. (rx)->stop_cbarg = NULL; \
  1526. }
  1527. /*
  1528. * Since rx_enable is synchronous callback, there is no start_cbfn required.
  1529. * Instead, we'll call bnad_rx_post(rxp) so that bnad can post the buffers
  1530. * for each rxpath.
  1531. */
  1532. #define call_rx_disable_cbfn(rx, status) \
  1533. if ((rx)->disable_cbfn) { \
  1534. (*(rx)->disable_cbfn)((rx)->disable_cbarg, \
  1535. status); \
  1536. (rx)->disable_cbfn = NULL; \
  1537. (rx)->disable_cbarg = NULL; \
  1538. } \
  1539. #define rxqs_reqd(type, num_rxqs) \
  1540. (((type) == BNA_RXP_SINGLE) ? (num_rxqs) : ((num_rxqs) * 2))
  1541. #define rx_ib_fail(rx) \
  1542. do { \
  1543. struct bna_rxp *rxp; \
  1544. struct list_head *qe; \
  1545. list_for_each(qe, &(rx)->rxp_q) { \
  1546. rxp = (struct bna_rxp *)qe; \
  1547. bna_ib_fail(rxp->cq.ib); \
  1548. } \
  1549. } while (0)
  1550. static void __bna_multi_rxq_stop(struct bna_rxp *, u32 *);
  1551. static void __bna_rxq_start(struct bna_rxq *rxq);
  1552. static void __bna_cq_start(struct bna_cq *cq);
  1553. static void bna_rit_create(struct bna_rx *rx);
  1554. static void bna_rx_cb_multi_rxq_stopped(void *arg, int status);
  1555. static void bna_rx_cb_rxq_stopped_all(void *arg);
  1556. bfa_fsm_state_decl(bna_rx, stopped,
  1557. struct bna_rx, enum bna_rx_event);
  1558. bfa_fsm_state_decl(bna_rx, rxf_start_wait,
  1559. struct bna_rx, enum bna_rx_event);
  1560. bfa_fsm_state_decl(bna_rx, started,
  1561. struct bna_rx, enum bna_rx_event);
  1562. bfa_fsm_state_decl(bna_rx, rxf_stop_wait,
  1563. struct bna_rx, enum bna_rx_event);
  1564. bfa_fsm_state_decl(bna_rx, rxq_stop_wait,
  1565. struct bna_rx, enum bna_rx_event);
  1566. static const struct bfa_sm_table rx_sm_table[] = {
  1567. {BFA_SM(bna_rx_sm_stopped), BNA_RX_STOPPED},
  1568. {BFA_SM(bna_rx_sm_rxf_start_wait), BNA_RX_RXF_START_WAIT},
  1569. {BFA_SM(bna_rx_sm_started), BNA_RX_STARTED},
  1570. {BFA_SM(bna_rx_sm_rxf_stop_wait), BNA_RX_RXF_STOP_WAIT},
  1571. {BFA_SM(bna_rx_sm_rxq_stop_wait), BNA_RX_RXQ_STOP_WAIT},
  1572. };
  1573. static void bna_rx_sm_stopped_entry(struct bna_rx *rx)
  1574. {
  1575. struct bna_rxp *rxp;
  1576. struct list_head *qe_rxp;
  1577. list_for_each(qe_rxp, &rx->rxp_q) {
  1578. rxp = (struct bna_rxp *)qe_rxp;
  1579. rx->rx_cleanup_cbfn(rx->bna->bnad, rxp->cq.ccb);
  1580. }
  1581. call_rx_stop_callback(rx, BNA_CB_SUCCESS);
  1582. }
  1583. static void bna_rx_sm_stopped(struct bna_rx *rx,
  1584. enum bna_rx_event event)
  1585. {
  1586. switch (event) {
  1587. case RX_E_START:
  1588. bfa_fsm_set_state(rx, bna_rx_sm_rxf_start_wait);
  1589. break;
  1590. case RX_E_STOP:
  1591. call_rx_stop_callback(rx, BNA_CB_SUCCESS);
  1592. break;
  1593. case RX_E_FAIL:
  1594. /* no-op */
  1595. break;
  1596. default:
  1597. bfa_sm_fault(rx->bna, event);
  1598. break;
  1599. }
  1600. }
  1601. static void bna_rx_sm_rxf_start_wait_entry(struct bna_rx *rx)
  1602. {
  1603. struct bna_rxp *rxp;
  1604. struct list_head *qe_rxp;
  1605. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1606. /* Setup the RIT */
  1607. bna_rit_create(rx);
  1608. list_for_each(qe_rxp, &rx->rxp_q) {
  1609. rxp = (struct bna_rxp *)qe_rxp;
  1610. bna_ib_start(rxp->cq.ib);
  1611. GET_RXQS(rxp, q0, q1);
  1612. q0->buffer_size = bna_port_mtu_get(&rx->bna->port);
  1613. __bna_rxq_start(q0);
  1614. rx->rx_post_cbfn(rx->bna->bnad, q0->rcb);
  1615. if (q1) {
  1616. __bna_rxq_start(q1);
  1617. rx->rx_post_cbfn(rx->bna->bnad, q1->rcb);
  1618. }
  1619. __bna_cq_start(&rxp->cq);
  1620. }
  1621. bna_rxf_start(&rx->rxf);
  1622. }
  1623. static void bna_rx_sm_rxf_start_wait(struct bna_rx *rx,
  1624. enum bna_rx_event event)
  1625. {
  1626. switch (event) {
  1627. case RX_E_STOP:
  1628. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1629. break;
  1630. case RX_E_FAIL:
  1631. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1632. rx_ib_fail(rx);
  1633. bna_rxf_fail(&rx->rxf);
  1634. break;
  1635. case RX_E_RXF_STARTED:
  1636. bfa_fsm_set_state(rx, bna_rx_sm_started);
  1637. break;
  1638. default:
  1639. bfa_sm_fault(rx->bna, event);
  1640. break;
  1641. }
  1642. }
  1643. void
  1644. bna_rx_sm_started_entry(struct bna_rx *rx)
  1645. {
  1646. struct bna_rxp *rxp;
  1647. struct list_head *qe_rxp;
  1648. /* Start IB */
  1649. list_for_each(qe_rxp, &rx->rxp_q) {
  1650. rxp = (struct bna_rxp *)qe_rxp;
  1651. bna_ib_ack(&rxp->cq.ib->door_bell, 0);
  1652. }
  1653. bna_llport_rx_started(&rx->bna->port.llport);
  1654. }
  1655. void
  1656. bna_rx_sm_started(struct bna_rx *rx, enum bna_rx_event event)
  1657. {
  1658. switch (event) {
  1659. case RX_E_FAIL:
  1660. bna_llport_rx_stopped(&rx->bna->port.llport);
  1661. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1662. rx_ib_fail(rx);
  1663. bna_rxf_fail(&rx->rxf);
  1664. break;
  1665. case RX_E_STOP:
  1666. bna_llport_rx_stopped(&rx->bna->port.llport);
  1667. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1668. break;
  1669. default:
  1670. bfa_sm_fault(rx->bna, event);
  1671. break;
  1672. }
  1673. }
  1674. void
  1675. bna_rx_sm_rxf_stop_wait_entry(struct bna_rx *rx)
  1676. {
  1677. bna_rxf_stop(&rx->rxf);
  1678. }
  1679. void
  1680. bna_rx_sm_rxf_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1681. {
  1682. switch (event) {
  1683. case RX_E_RXF_STOPPED:
  1684. bfa_fsm_set_state(rx, bna_rx_sm_rxq_stop_wait);
  1685. break;
  1686. case RX_E_RXF_STARTED:
  1687. /**
  1688. * RxF was in the process of starting up when
  1689. * RXF_E_STOP was issued. Ignore this event
  1690. */
  1691. break;
  1692. case RX_E_FAIL:
  1693. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1694. rx_ib_fail(rx);
  1695. bna_rxf_fail(&rx->rxf);
  1696. break;
  1697. default:
  1698. bfa_sm_fault(rx->bna, event);
  1699. break;
  1700. }
  1701. }
  1702. void
  1703. bna_rx_sm_rxq_stop_wait_entry(struct bna_rx *rx)
  1704. {
  1705. struct bna_rxp *rxp = NULL;
  1706. struct bna_rxq *q0 = NULL;
  1707. struct bna_rxq *q1 = NULL;
  1708. struct list_head *qe;
  1709. u32 rxq_mask[2] = {0, 0};
  1710. /* Only one call to multi-rxq-stop for all RXPs in this RX */
  1711. bfa_wc_up(&rx->rxq_stop_wc);
  1712. list_for_each(qe, &rx->rxp_q) {
  1713. rxp = (struct bna_rxp *)qe;
  1714. GET_RXQS(rxp, q0, q1);
  1715. if (q0->rxq_id < 32)
  1716. rxq_mask[0] |= ((u32)1 << q0->rxq_id);
  1717. else
  1718. rxq_mask[1] |= ((u32)1 << (q0->rxq_id - 32));
  1719. if (q1) {
  1720. if (q1->rxq_id < 32)
  1721. rxq_mask[0] |= ((u32)1 << q1->rxq_id);
  1722. else
  1723. rxq_mask[1] |= ((u32)
  1724. 1 << (q1->rxq_id - 32));
  1725. }
  1726. }
  1727. __bna_multi_rxq_stop(rxp, rxq_mask);
  1728. }
  1729. void
  1730. bna_rx_sm_rxq_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1731. {
  1732. struct bna_rxp *rxp = NULL;
  1733. struct list_head *q