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/drivers/net/bna/bfi_ctreg.h

https://bitbucket.org/slukk/jb-tsm-kernel-4.2
C Header | 646 lines | 587 code | 13 blank | 46 comment | 0 complexity | 2f85ef73a31bc0fa75663b027f561af4 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0 
    

  1. /*
    2. 

  2.  * Linux network driver for Brocade Converged Network Adapter.
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or modify it
    5. 

  5.  * under the terms of the GNU General Public License (GPL) Version 2 as
    6. 

  6.  * published by the Free Software Foundation
    7. 

  7.  *
    8. 

  8.  * This program is distributed in the hope that it will be useful, but
    9. 

  9.  * WITHOUT ANY WARRANTY; without even the implied warranty of
    10. 

  10.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
    11. 

  11.  * General Public License for more details.
    12. 

  12.  */
    13. 

  13. /*
    14. 

  14.  * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
    15. 

  15.  * All rights reserved
    16. 

  16.  * www.brocade.com
    17. 

  17.  */
    18. 

  18. 

  19. /*
    20. 

  20.  * bfi_ctreg.h catapult host block register definitions
    21. 

  21.  *
    22. 

  22.  * !!! Do not edit. Auto generated. !!!
    23. 

  23.  */
    24. 

  24. 

  25. #ifndef __BFI_CTREG_H__
    26. 

  26. #define __BFI_CTREG_H__
    27. 

  27. 

  28. #define HOSTFN0_LPU_MBOX0_0		0x00019200
    29. 

  29. #define HOSTFN1_LPU_MBOX0_8		0x00019260
    30. 

  30. #define LPU_HOSTFN0_MBOX0_0		0x00019280
    31. 

  31. #define LPU_HOSTFN1_MBOX0_8		0x000192e0
    32. 

  32. #define HOSTFN2_LPU_MBOX0_0		0x00019400
    33. 

  33. #define HOSTFN3_LPU_MBOX0_8		0x00019460
    34. 

  34. #define LPU_HOSTFN2_MBOX0_0		0x00019480
    35. 

  35. #define LPU_HOSTFN3_MBOX0_8		0x000194e0
    36. 

  36. #define HOSTFN0_INT_STATUS		0x00014000
    37. 

  37. #define __HOSTFN0_HALT_OCCURRED		0x01000000
    38. 

  38. #define __HOSTFN0_INT_STATUS_LVL_MK	0x00f00000
    39. 

  39. #define __HOSTFN0_INT_STATUS_LVL_SH	20
    40. 

  40. #define __HOSTFN0_INT_STATUS_LVL(_v)	((_v) << __HOSTFN0_INT_STATUS_LVL_SH)
    41. 

  41. #define __HOSTFN0_INT_STATUS_P_MK	0x000f0000
    42. 

  42. #define __HOSTFN0_INT_STATUS_P_SH	16
    43. 

  43. #define __HOSTFN0_INT_STATUS_P(_v)	((_v) << __HOSTFN0_INT_STATUS_P_SH)
    44. 

  44. #define __HOSTFN0_INT_STATUS_F		0x0000ffff
    45. 

  45. #define HOSTFN0_INT_MSK			0x00014004
    46. 

  46. #define HOST_PAGE_NUM_FN0		0x00014008
    47. 

  47. #define __HOST_PAGE_NUM_FN		0x000001ff
    48. 

  48. #define HOST_MSIX_ERR_INDEX_FN0		0x0001400c
    49. 

  49. #define __MSIX_ERR_INDEX_FN		0x000001ff
    50. 

  50. #define HOSTFN1_INT_STATUS		0x00014100
    51. 

  51. #define __HOSTFN1_HALT_OCCURRED		0x01000000
    52. 

  52. #define __HOSTFN1_INT_STATUS_LVL_MK	0x00f00000
    53. 

  53. #define __HOSTFN1_INT_STATUS_LVL_SH	20
    54. 

  54. #define __HOSTFN1_INT_STATUS_LVL(_v)	((_v) << __HOSTFN1_INT_STATUS_LVL_SH)
    55. 

  55. #define __HOSTFN1_INT_STATUS_P_MK	0x000f0000
    56. 

  56. #define __HOSTFN1_INT_STATUS_P_SH	16
    57. 

  57. #define __HOSTFN1_INT_STATUS_P(_v)	((_v) << __HOSTFN1_INT_STATUS_P_SH)
    58. 

  58. #define __HOSTFN1_INT_STATUS_F		0x0000ffff
    59. 

  59. #define HOSTFN1_INT_MSK			0x00014104
    60. 

  60. #define HOST_PAGE_NUM_FN1		0x00014108
    61. 

  61. #define HOST_MSIX_ERR_INDEX_FN1		0x0001410c
    62. 

  62. #define APP_PLL_425_CTL_REG		0x00014204
    63. 

  63. #define __P_425_PLL_LOCK		0x80000000
    64. 

  64. #define __APP_PLL_425_SRAM_USE_100MHZ	0x00100000
    65. 

  65. #define __APP_PLL_425_RESET_TIMER_MK	0x000e0000
    66. 

  66. #define __APP_PLL_425_RESET_TIMER_SH	17
    67. 

  67. #define __APP_PLL_425_RESET_TIMER(_v)	((_v) << __APP_PLL_425_RESET_TIMER_SH)
    68. 

  68. #define __APP_PLL_425_LOGIC_SOFT_RESET	0x00010000
    69. 

  69. #define __APP_PLL_425_CNTLMT0_1_MK	0x0000c000
    70. 

  70. #define __APP_PLL_425_CNTLMT0_1_SH	14
    71. 

  71. #define __APP_PLL_425_CNTLMT0_1(_v)	((_v) << __APP_PLL_425_CNTLMT0_1_SH)
    72. 

  72. #define __APP_PLL_425_JITLMT0_1_MK	0x00003000
    73. 

  73. #define __APP_PLL_425_JITLMT0_1_SH	12
    74. 

  74. #define __APP_PLL_425_JITLMT0_1(_v)	((_v) << __APP_PLL_425_JITLMT0_1_SH)
    75. 

  75. #define __APP_PLL_425_HREF		0x00000800
    76. 

  76. #define __APP_PLL_425_HDIV		0x00000400
    77. 

  77. #define __APP_PLL_425_P0_1_MK		0x00000300
    78. 

  78. #define __APP_PLL_425_P0_1_SH		8
    79. 

  79. #define __APP_PLL_425_P0_1(_v)		((_v) << __APP_PLL_425_P0_1_SH)
    80. 

  80. #define __APP_PLL_425_Z0_2_MK		0x000000e0
    81. 

  81. #define __APP_PLL_425_Z0_2_SH		5
    82. 

  82. #define __APP_PLL_425_Z0_2(_v)		((_v) << __APP_PLL_425_Z0_2_SH)
    83. 

  83. #define __APP_PLL_425_RSEL200500	0x00000010
    84. 

  84. #define __APP_PLL_425_ENARST		0x00000008
    85. 

  85. #define __APP_PLL_425_BYPASS		0x00000004
    86. 

  86. #define __APP_PLL_425_LRESETN		0x00000002
    87. 

  87. #define __APP_PLL_425_ENABLE		0x00000001
    88. 

  88. #define APP_PLL_312_CTL_REG		0x00014208
    89. 

  89. #define __P_312_PLL_LOCK		0x80000000
    90. 

  90. #define __ENABLE_MAC_AHB_1		0x00800000
    91. 

  91. #define __ENABLE_MAC_AHB_0		0x00400000
    92. 

  92. #define __ENABLE_MAC_1			0x00200000
    93. 

  93. #define __ENABLE_MAC_0			0x00100000
    94. 

  94. #define __APP_PLL_312_RESET_TIMER_MK	0x000e0000
    95. 

  95. #define __APP_PLL_312_RESET_TIMER_SH	17
    96. 

  96. #define __APP_PLL_312_RESET_TIMER(_v)	((_v) << __APP_PLL_312_RESET_TIMER_SH)
    97. 

  97. #define __APP_PLL_312_LOGIC_SOFT_RESET	0x00010000
    98. 

  98. #define __APP_PLL_312_CNTLMT0_1_MK	0x0000c000
    99. 

  99. #define __APP_PLL_312_CNTLMT0_1_SH	14
    100. 

  100. #define __APP_PLL_312_CNTLMT0_1(_v)	((_v) << __APP_PLL_312_CNTLMT0_1_SH)
    101. 

  101. #define __APP_PLL_312_JITLMT0_1_MK	0x00003000
    102. 

  102. #define __APP_PLL_312_JITLMT0_1_SH	12
    103. 

  103. #define __APP_PLL_312_JITLMT0_1(_v)	((_v) << __APP_PLL_312_JITLMT0_1_SH)
    104. 

  104. #define __APP_PLL_312_HREF		0x00000800
    105. 

  105. #define __APP_PLL_312_HDIV		0x00000400
    106. 

  106. #define __APP_PLL_312_P0_1_MK		0x00000300
    107. 

  107. #define __APP_PLL_312_P0_1_SH		8
    108. 

  108. #define __APP_PLL_312_P0_1(_v)		((_v) << __APP_PLL_312_P0_1_SH)
    109. 

  109. #define __APP_PLL_312_Z0_2_MK		0x000000e0
    110. 

  110. #define __APP_PLL_312_Z0_2_SH		5
    111. 

  111. #define __APP_PLL_312_Z0_2(_v)		((_v) << __APP_PLL_312_Z0_2_SH)
    112. 

  112. #define __APP_PLL_312_RSEL200500	0x00000010
    113. 

  113. #define __APP_PLL_312_ENARST		0x00000008
    114. 

  114. #define __APP_PLL_312_BYPASS		0x00000004
    115. 

  115. #define __APP_PLL_312_LRESETN		0x00000002
    116. 

  116. #define __APP_PLL_312_ENABLE		0x00000001
    117. 

  117. #define MBIST_CTL_REG			0x00014220
    118. 

  118. #define __EDRAM_BISTR_START		0x00000004
    119. 

  119. #define __MBIST_RESET			0x00000002
    120. 

  120. #define __MBIST_START			0x00000001
    121. 

  121. #define MBIST_STAT_REG			0x00014224
    122. 

  122. #define __EDRAM_BISTR_STATUS		0x00000008
    123. 

  123. #define __EDRAM_BISTR_DONE		0x00000004
    124. 

  124. #define __MEM_BIT_STATUS		0x00000002
    125. 

  125. #define __MBIST_DONE			0x00000001
    126. 

  126. #define HOST_SEM0_REG			0x00014230
    127. 

  127. #define __HOST_SEMAPHORE		0x00000001
    128. 

  128. #define HOST_SEM1_REG			0x00014234
    129. 

  129. #define HOST_SEM2_REG			0x00014238
    130. 

  130. #define HOST_SEM3_REG			0x0001423c
    131. 

  131. #define HOST_SEM0_INFO_REG		0x00014240
    132. 

  132. #define HOST_SEM1_INFO_REG		0x00014244
    133. 

  133. #define HOST_SEM2_INFO_REG		0x00014248
    134. 

  134. #define HOST_SEM3_INFO_REG		0x0001424c
    135. 

  135. #define ETH_MAC_SER_REG			0x00014288
    136. 

  136. #define __APP_EMS_CKBUFAMPIN		0x00000020
    137. 

  137. #define __APP_EMS_REFCLKSEL		0x00000010
    138. 

  138. #define __APP_EMS_CMLCKSEL		0x00000008
    139. 

  139. #define __APP_EMS_REFCKBUFEN2		0x00000004
    140. 

  140. #define __APP_EMS_REFCKBUFEN1		0x00000002
    141. 

  141. #define __APP_EMS_CHANNEL_SEL		0x00000001
    142. 

  142. #define HOSTFN2_INT_STATUS		0x00014300
    143. 

  143. #define __HOSTFN2_HALT_OCCURRED		0x01000000
    144. 

  144. #define __HOSTFN2_INT_STATUS_LVL_MK	0x00f00000
    145. 

  145. #define __HOSTFN2_INT_STATUS_LVL_SH	20
    146. 

  146. #define __HOSTFN2_INT_STATUS_LVL(_v)	((_v) << __HOSTFN2_INT_STATUS_LVL_SH)
    147. 

  147. #define __HOSTFN2_INT_STATUS_P_MK	0x000f0000
    148. 

  148. #define __HOSTFN2_INT_STATUS_P_SH	16
    149. 

  149. #define __HOSTFN2_INT_STATUS_P(_v)	((_v) << __HOSTFN2_INT_STATUS_P_SH)
    150. 

  150. #define __HOSTFN2_INT_STATUS_F		0x0000ffff
    151. 

  151. #define HOSTFN2_INT_MSK			0x00014304
    152. 

  152. #define HOST_PAGE_NUM_FN2		0x00014308
    153. 

  153. #define HOST_MSIX_ERR_INDEX_FN2		0x0001430c
    154. 

  154. #define HOSTFN3_INT_STATUS		0x00014400
    155. 

  155. #define __HALT_OCCURRED			0x01000000
    156. 

  156. #define __HOSTFN3_INT_STATUS_LVL_MK	0x00f00000
    157. 

  157. #define __HOSTFN3_INT_STATUS_LVL_SH	20
    158. 

  158. #define __HOSTFN3_INT_STATUS_LVL(_v)	((_v) << __HOSTFN3_INT_STATUS_LVL_SH)
    159. 

  159. #define __HOSTFN3_INT_STATUS_P_MK	0x000f0000
    160. 

  160. #define __HOSTFN3_INT_STATUS_P_SH	16
    161. 

  161. #define __HOSTFN3_INT_STATUS_P(_v)	((_v) << __HOSTFN3_INT_STATUS_P_SH)
    162. 

  162. #define __HOSTFN3_INT_STATUS_F		0x0000ffff
    163. 

  163. #define HOSTFN3_INT_MSK			0x00014404
    164. 

  164. #define HOST_PAGE_NUM_FN3		0x00014408
    165. 

  165. #define HOST_MSIX_ERR_INDEX_FN3		0x0001440c
    166. 

  166. #define FNC_ID_REG			0x00014600
    167. 

  167. #define __FUNCTION_NUMBER		0x00000007
    168. 

  168. #define FNC_PERS_REG			0x00014604
    169. 

  169. #define __F3_FUNCTION_ACTIVE		0x80000000
    170. 

  170. #define __F3_FUNCTION_MODE		0x40000000
    171. 

  171. #define __F3_PORT_MAP_MK		0x30000000
    172. 

  172. #define __F3_PORT_MAP_SH		28
    173. 

  173. #define __F3_PORT_MAP(_v)		((_v) << __F3_PORT_MAP_SH)
    174. 

  174. #define __F3_VM_MODE			0x08000000
    175. 

  175. #define __F3_INTX_STATUS_MK		0x07000000
    176. 

  176. #define __F3_INTX_STATUS_SH		24
    177. 

  177. #define __F3_INTX_STATUS(_v)		((_v) << __F3_INTX_STATUS_SH)
    178. 

  178. #define __F2_FUNCTION_ACTIVE		0x00800000
    179. 

  179. #define __F2_FUNCTION_MODE		0x00400000
    180. 

  180. #define __F2_PORT_MAP_MK		0x00300000
    181. 

  181. #define __F2_PORT_MAP_SH		20
    182. 

  182. #define __F2_PORT_MAP(_v)		((_v) << __F2_PORT_MAP_SH)
    183. 

  183. #define __F2_VM_MODE			0x00080000
    184. 

  184. #define __F2_INTX_STATUS_MK		0x00070000
    185. 

  185. #define __F2_INTX_STATUS_SH		16
    186. 

  186. #define __F2_INTX_STATUS(_v)		((_v) << __F2_INTX_STATUS_SH)
    187. 

  187. #define __F1_FUNCTION_ACTIVE		0x00008000
    188. 

  188. #define __F1_FUNCTION_MODE		0x00004000
    189. 

  189. #define __F1_PORT_MAP_MK		0x00003000
    190. 

  190. #define __F1_PORT_MAP_SH		12
    191. 

  191. #define __F1_PORT_MAP(_v)		((_v) << __F1_PORT_MAP_SH)
    192. 

  192. #define __F1_VM_MODE			0x00000800
    193. 

  193. #define __F1_INTX_STATUS_MK		0x00000700
    194. 

  194. #define __F1_INTX_STATUS_SH		8
    195. 

  195. #define __F1_INTX_STATUS(_v)		((_v) << __F1_INTX_STATUS_SH)
    196. 

  196. #define __F0_FUNCTION_ACTIVE		0x00000080
    197. 

  197. #define __F0_FUNCTION_MODE		0x00000040
    198. 

  198. #define __F0_PORT_MAP_MK		0x00000030
    199. 

  199. #define __F0_PORT_MAP_SH		4
    200. 

  200. #define __F0_PORT_MAP(_v)		((_v) << __F0_PORT_MAP_SH)
    201. 

  201. #define __F0_VM_MODE		0x00000008
    202. 

  202. #define __F0_INTX_STATUS		0x00000007
    203. 

  203. enum {
    204. 

  204. 	__F0_INTX_STATUS_MSIX		= 0x0,
    205. 

  205. 	__F0_INTX_STATUS_INTA		= 0x1,
    206. 

  206. 	__F0_INTX_STATUS_INTB		= 0x2,
    207. 

  207. 	__F0_INTX_STATUS_INTC		= 0x3,
    208. 

  208. 	__F0_INTX_STATUS_INTD		= 0x4,
    209. 

  209. };
    210. 

  210. #define OP_MODE				0x0001460c
    211. 

  211. #define __APP_ETH_CLK_LOWSPEED		0x00000004
    212. 

  212. #define __GLOBAL_CORECLK_HALFSPEED	0x00000002
    213. 

  213. #define __GLOBAL_FCOE_MODE		0x00000001
    214. 

  214. #define HOST_SEM4_REG			0x00014610
    215. 

  215. #define HOST_SEM5_REG			0x00014614
    216. 

  216. #define HOST_SEM6_REG			0x00014618
    217. 

  217. #define HOST_SEM7_REG			0x0001461c
    218. 

  218. #define HOST_SEM4_INFO_REG		0x00014620
    219. 

  219. #define HOST_SEM5_INFO_REG		0x00014624
    220. 

  220. #define HOST_SEM6_INFO_REG		0x00014628
    221. 

  221. #define HOST_SEM7_INFO_REG		0x0001462c
    222. 

  222. #define HOSTFN0_LPU0_MBOX0_CMD_STAT	0x00019000
    223. 

  223. #define __HOSTFN0_LPU0_MBOX0_INFO_MK	0xfffffffe
    224. 

  224. #define __HOSTFN0_LPU0_MBOX0_INFO_SH	1
    225. 

  225. #define __HOSTFN0_LPU0_MBOX0_INFO(_v)	((_v) << __HOSTFN0_LPU0_MBOX0_INFO_SH)
    226. 

  226. #define __HOSTFN0_LPU0_MBOX0_CMD_STATUS 0x00000001
    227. 

  227. #define HOSTFN0_LPU1_MBOX0_CMD_STAT	0x00019004
    228. 

  228. #define __HOSTFN0_LPU1_MBOX0_INFO_MK	0xfffffffe
    229. 

  229. #define __HOSTFN0_LPU1_MBOX0_INFO_SH	1
    230. 

  230. #define __HOSTFN0_LPU1_MBOX0_INFO(_v)	((_v) << __HOSTFN0_LPU1_MBOX0_INFO_SH)
    231. 

  231. #define __HOSTFN0_LPU1_MBOX0_CMD_STATUS 0x00000001
    232. 

  232. #define LPU0_HOSTFN0_MBOX0_CMD_STAT	0x00019008
    233. 

  233. #define __LPU0_HOSTFN0_MBOX0_INFO_MK	0xfffffffe
    234. 

  234. #define __LPU0_HOSTFN0_MBOX0_INFO_SH	1
    235. 

  235. #define __LPU0_HOSTFN0_MBOX0_INFO(_v)	((_v) << __LPU0_HOSTFN0_MBOX0_INFO_SH)
    236. 

  236. #define __LPU0_HOSTFN0_MBOX0_CMD_STATUS 0x00000001
    237. 

  237. #define LPU1_HOSTFN0_MBOX0_CMD_STAT	0x0001900c
    238. 

  238. #define __LPU1_HOSTFN0_MBOX0_INFO_MK	0xfffffffe
    239. 

  239. #define __LPU1_HOSTFN0_MBOX0_INFO_SH	1
    240. 

  240. #define __LPU1_HOSTFN0_MBOX0_INFO(_v)	((_v) << __LPU1_HOSTFN0_MBOX0_INFO_SH)
    241. 

  241. #define __LPU1_HOSTFN0_MBOX0_CMD_STATUS 0x00000001
    242. 

  242. #define HOSTFN1_LPU0_MBOX0_CMD_STAT	0x00019010
    243. 

  243. #define __HOSTFN1_LPU0_MBOX0_INFO_MK	0xfffffffe
    244. 

  244. #define __HOSTFN1_LPU0_MBOX0_INFO_SH	1
    245. 

  245. #define __HOSTFN1_LPU0_MBOX0_INFO(_v)	((_v) << __HOSTFN1_LPU0_MBOX0_INFO_SH)
    246. 

  246. #define __HOSTFN1_LPU0_MBOX0_CMD_STATUS 0x00000001
    247. 

  247. #define HOSTFN1_LPU1_MBOX0_CMD_STAT	0x00019014
    248. 

  248. #define __HOSTFN1_LPU1_MBOX0_INFO_MK	0xfffffffe
    249. 

  249. #define __HOSTFN1_LPU1_MBOX0_INFO_SH	1
    250. 

  250. #define __HOSTFN1_LPU1_MBOX0_INFO(_v)	((_v) << __HOSTFN1_LPU1_MBOX0_INFO_SH)
    251. 

  251. #define __HOSTFN1_LPU1_MBOX0_CMD_STATUS 0x00000001
    252. 

  252. #define LPU0_HOSTFN1_MBOX0_CMD_STAT	0x00019018
    253. 

  253. #define __LPU0_HOSTFN1_MBOX0_INFO_MK	0xfffffffe
    254. 

  254. #define __LPU0_HOSTFN1_MBOX0_INFO_SH	1
    255. 

  255. #define __LPU0_HOSTFN1_MBOX0_INFO(_v)	((_v) << __LPU0_HOSTFN1_MBOX0_INFO_SH)
    256. 

  256. #define __LPU0_HOSTFN1_MBOX0_CMD_STATUS 0x00000001
    257. 

  257. #define LPU1_HOSTFN1_MBOX0_CMD_STAT	0x0001901c
    258. 

  258. #define __LPU1_HOSTFN1_MBOX0_INFO_MK	0xfffffffe
    259. 

  259. #define __LPU1_HOSTFN1_MBOX0_INFO_SH	1
    260. 

  260. #define __LPU1_HOSTFN1_MBOX0_INFO(_v)	((_v) << __LPU1_HOSTFN1_MBOX0_INFO_SH)
    261. 

  261. #define __LPU1_HOSTFN1_MBOX0_CMD_STATUS 0x00000001
    262. 

  262. #define HOSTFN2_LPU0_MBOX0_CMD_STAT	0x00019150
    263. 

  263. #define __HOSTFN2_LPU0_MBOX0_INFO_MK	0xfffffffe
    264. 

  264. #define __HOSTFN2_LPU0_MBOX0_INFO_SH	1
    265. 

  265. #define __HOSTFN2_LPU0_MBOX0_INFO(_v)	((_v) << __HOSTFN2_LPU0_MBOX0_INFO_SH)
    266. 

  266. #define __HOSTFN2_LPU0_MBOX0_CMD_STATUS 0x00000001
    267. 

  267. #define HOSTFN2_LPU1_MBOX0_CMD_STAT	0x00019154
    268. 

  268. #define __HOSTFN2_LPU1_MBOX0_INFO_MK	0xfffffffe
    269. 

  269. #define __HOSTFN2_LPU1_MBOX0_INFO_SH	1
    270. 

  270. #define __HOSTFN2_LPU1_MBOX0_INFO(_v)	((_v) << __HOSTFN2_LPU1_MBOX0_INFO_SH)
    271. 

  271. #define __HOSTFN2_LPU1_MBOX0BOX0_CMD_STATUS 0x00000001
    272. 

  272. #define LPU0_HOSTFN2_MBOX0_CMD_STAT	0x00019158
    273. 

  273. #define __LPU0_HOSTFN2_MBOX0_INFO_MK	0xfffffffe
    274. 

  274. #define __LPU0_HOSTFN2_MBOX0_INFO_SH	1
    275. 

  275. #define __LPU0_HOSTFN2_MBOX0_INFO(_v)	((_v) << __LPU0_HOSTFN2_MBOX0_INFO_SH)
    276. 

  276. #define __LPU0_HOSTFN2_MBOX0_CMD_STATUS 0x00000001
    277. 

  277. #define LPU1_HOSTFN2_MBOX0_CMD_STAT	0x0001915c
    278. 

  278. #define __LPU1_HOSTFN2_MBOX0_INFO_MK	0xfffffffe
    279. 

  279. #define __LPU1_HOSTFN2_MBOX0_INFO_SH	1
    280. 

  280. #define __LPU1_HOSTFN2_MBOX0_INFO(_v)	((_v) << __LPU1_HOSTFN2_MBOX0_INFO_SH)
    281. 

  281. #define __LPU1_HOSTFN2_MBOX0_CMD_STATUS 0x00000001
    282. 

  282. #define HOSTFN3_LPU0_MBOX0_CMD_STAT	0x00019160
    283. 

  283. #define __HOSTFN3_LPU0_MBOX0_INFO_MK	0xfffffffe
    284. 

  284. #define __HOSTFN3_LPU0_MBOX0_INFO_SH	1
    285. 

  285. #define __HOSTFN3_LPU0_MBOX0_INFO(_v)	((_v) << __HOSTFN3_LPU0_MBOX0_INFO_SH)
    286. 

  286. #define __HOSTFN3_LPU0_MBOX0_CMD_STATUS 0x00000001
    287. 

  287. #define HOSTFN3_LPU1_MBOX0_CMD_STAT	0x00019164
    288. 

  288. #define __HOSTFN3_LPU1_MBOX0_INFO_MK	0xfffffffe
    289. 

  289. #define __HOSTFN3_LPU1_MBOX0_INFO_SH	1
    290. 

  290. #define __HOSTFN3_LPU1_MBOX0_INFO(_v)	((_v) << __HOSTFN3_LPU1_MBOX0_INFO_SH)
    291. 

  291. #define __HOSTFN3_LPU1_MBOX0_CMD_STATUS 0x00000001
    292. 

  292. #define LPU0_HOSTFN3_MBOX0_CMD_STAT	0x00019168
    293. 

  293. #define __LPU0_HOSTFN3_MBOX0_INFO_MK	0xfffffffe
    294. 

  294. #define __LPU0_HOSTFN3_MBOX0_INFO_SH	1
    295. 

  295. #define __LPU0_HOSTFN3_MBOX0_INFO(_v)	((_v) << __LPU0_HOSTFN3_MBOX0_INFO_SH)
    296. 

  296. #define __LPU0_HOSTFN3_MBOX0_CMD_STATUS 0x00000001
    297. 

  297. #define LPU1_HOSTFN3_MBOX0_CMD_STAT	0x0001916c
    298. 

  298. #define __LPU1_HOSTFN3_MBOX0_INFO_MK	0xfffffffe
    299. 

  299. #define __LPU1_HOSTFN3_MBOX0_INFO_SH	1
    300. 

  300. #define __LPU1_HOSTFN3_MBOX0_INFO(_v)	((_v) << __LPU1_HOSTFN3_MBOX0_INFO_SH)
    301. 

  301. #define __LPU1_HOSTFN3_MBOX0_CMD_STATUS	0x00000001
    302. 

  302. #define FW_INIT_HALT_P0			0x000191ac
    303. 

  303. #define __FW_INIT_HALT_P		0x00000001
    304. 

  304. #define FW_INIT_HALT_P1			0x000191bc
    305. 

  305. #define CPE_PI_PTR_Q0			0x00038000
    306. 

  306. #define __CPE_PI_UNUSED_MK		0xffff0000
    307. 

  307. #define __CPE_PI_UNUSED_SH		16
    308. 

  308. #define __CPE_PI_UNUSED(_v)		((_v) << __CPE_PI_UNUSED_SH)
    309. 

  309. #define __CPE_PI_PTR			0x0000ffff
    310. 

  310. #define CPE_PI_PTR_Q1			0x00038040
    311. 

  311. #define CPE_CI_PTR_Q0			0x00038004
    312. 

  312. #define __CPE_CI_UNUSED_MK		0xffff0000
    313. 

  313. #define __CPE_CI_UNUSED_SH		16
    314. 

  314. #define __CPE_CI_UNUSED(_v)		((_v) << __CPE_CI_UNUSED_SH)
    315. 

  315. #define __CPE_CI_PTR			0x0000ffff
    316. 

  316. #define CPE_CI_PTR_Q1			0x00038044
    317. 

  317. #define CPE_DEPTH_Q0			0x00038008
    318. 

  318. #define __CPE_DEPTH_UNUSED_MK		0xf8000000
    319. 

  319. #define __CPE_DEPTH_UNUSED_SH		27
    320. 

  320. #define __CPE_DEPTH_UNUSED(_v)		((_v) << __CPE_DEPTH_UNUSED_SH)
    321. 

  321. #define __CPE_MSIX_VEC_INDEX_MK		0x07ff0000
    322. 

  322. #define __CPE_MSIX_VEC_INDEX_SH		16
    323. 

  323. #define __CPE_MSIX_VEC_INDEX(_v)	((_v) << __CPE_MSIX_VEC_INDEX_SH)
    324. 

  324. #define __CPE_DEPTH			0x0000ffff
    325. 

  325. #define CPE_DEPTH_Q1			0x00038048
    326. 

  326. #define CPE_QCTRL_Q0			0x0003800c
    327. 

  327. #define __CPE_CTRL_UNUSED30_MK		0xfc000000
    328. 

  328. #define __CPE_CTRL_UNUSED30_SH		26
    329. 

  329. #define __CPE_CTRL_UNUSED30(_v)		((_v) << __CPE_CTRL_UNUSED30_SH)
    330. 

  330. #define __CPE_FUNC_INT_CTRL_MK		0x03000000
    331. 

  331. #define __CPE_FUNC_INT_CTRL_SH		24
    332. 

  332. #define __CPE_FUNC_INT_CTRL(_v)		((_v) << __CPE_FUNC_INT_CTRL_SH)
    333. 

  333. enum {
    334. 

  334. 	__CPE_FUNC_INT_CTRL_DISABLE		= 0x0,
    335. 

  335. 	__CPE_FUNC_INT_CTRL_F2NF		= 0x1,
    336. 

  336. 	__CPE_FUNC_INT_CTRL_3QUART		= 0x2,
    337. 

  337. 	__CPE_FUNC_INT_CTRL_HALF		= 0x3,
    338. 

  338. };
    339. 

  339. #define __CPE_CTRL_UNUSED20_MK		0x00f00000
    340. 

  340. #define __CPE_CTRL_UNUSED20_SH		20
    341. 

  341. #define __CPE_CTRL_UNUSED20(_v)		((_v) << __CPE_CTRL_UNUSED20_SH)
    342. 

  342. #define __CPE_SCI_TH_MK			0x000f0000
    343. 

  343. #define __CPE_SCI_TH_SH			16
    344. 

  344. #define __CPE_SCI_TH(_v)		((_v) << __CPE_SCI_TH_SH)
    345. 

  345. #define __CPE_CTRL_UNUSED10_MK		0x0000c000
    346. 

  346. #define __CPE_CTRL_UNUSED10_SH		14
    347. 

  347. #define __CPE_CTRL_UNUSED10(_v)		((_v) << __CPE_CTRL_UNUSED10_SH)
    348. 

  348. #define __CPE_ACK_PENDING		0x00002000
    349. 

  349. #define __CPE_CTRL_UNUSED40_MK		0x00001c00
    350. 

  350. #define __CPE_CTRL_UNUSED40_SH		10
    351. 

  351. #define __CPE_CTRL_UNUSED40(_v)		((_v) << __CPE_CTRL_UNUSED40_SH)
    352. 

  352. #define __CPE_PCIEID_MK			0x00000300
    353. 

  353. #define __CPE_PCIEID_SH			8
    354. 

  354. #define __CPE_PCIEID(_v)		((_v) << __CPE_PCIEID_SH)
    355. 

  355. #define __CPE_CTRL_UNUSED00_MK		0x000000fe
    356. 

  356. #define __CPE_CTRL_UNUSED00_SH		1
    357. 

  357. #define __CPE_CTRL_UNUSED00(_v)		((_v) << __CPE_CTRL_UNUSED00_SH)
    358. 

  358. #define __CPE_ESIZE			0x00000001
    359. 

  359. #define CPE_QCTRL_Q1			0x0003804c
    360. 

  360. #define __CPE_CTRL_UNUSED31_MK		0xfc000000
    361. 

  361. #define __CPE_CTRL_UNUSED31_SH		26
    362. 

  362. #define __CPE_CTRL_UNUSED31(_v)		((_v) << __CPE_CTRL_UNUSED31_SH)
    363. 

  363. #define __CPE_CTRL_UNUSED21_MK		0x00f00000
    364. 

  364. #define __CPE_CTRL_UNUSED21_SH		20
    365. 

  365. #define __CPE_CTRL_UNUSED21(_v)		((_v) << __CPE_CTRL_UNUSED21_SH)
    366. 

  366. #define __CPE_CTRL_UNUSED11_MK		0x0000c000
    367. 

  367. #define __CPE_CTRL_UNUSED11_SH		14
    368. 

  368. #define __CPE_CTRL_UNUSED11(_v)		((_v) << __CPE_CTRL_UNUSED11_SH)
    369. 

  369. #define __CPE_CTRL_UNUSED41_MK		0x00001c00
    370. 

  370. #define __CPE_CTRL_UNUSED41_SH		10
    371. 

  371. #define __CPE_CTRL_UNUSED41(_v)		((_v) << __CPE_CTRL_UNUSED41_SH)
    372. 

  372. #define __CPE_CTRL_UNUSED01_MK		0x000000fe
    373. 

  373. #define __CPE_CTRL_UNUSED01_SH		1
    374. 

  374. #define __CPE_CTRL_UNUSED01(_v)		((_v) << __CPE_CTRL_UNUSED01_SH)
    375. 

  375. #define RME_PI_PTR_Q0			0x00038020
    376. 

  376. #define __LATENCY_TIME_STAMP_MK		0xffff0000
    377. 

  377. #define __LATENCY_TIME_STAMP_SH		16
    378. 

  378. #define __LATENCY_TIME_STAMP(_v)	((_v) << __LATENCY_TIME_STAMP_SH)
    379. 

  379. #define __RME_PI_PTR			0x0000ffff
    380. 

  380. #define RME_PI_PTR_Q1			0x00038060
    381. 

  381. #define RME_CI_PTR_Q0			0x00038024
    382. 

  382. #define __DELAY_TIME_STAMP_MK		0xffff0000
    383. 

  383. #define __DELAY_TIME_STAMP_SH		16
    384. 

  384. #define __DELAY_TIME_STAMP(_v)		((_v) << __DELAY_TIME_STAMP_SH)
    385. 

  385. #define __RME_CI_PTR			0x0000ffff
    386. 

  386. #define RME_CI_PTR_Q1			0x00038064
    387. 

  387. #define RME_DEPTH_Q0			0x00038028
    388. 

  388. #define __RME_DEPTH_UNUSED_MK		0xf8000000
    389. 

  389. #define __RME_DEPTH_UNUSED_SH		27
    390. 

  390. #define __RME_DEPTH_UNUSED(_v)		((_v) << __RME_DEPTH_UNUSED_SH)
    391. 

  391. #define __RME_MSIX_VEC_INDEX_MK		0x07ff0000
    392. 

  392. #define __RME_MSIX_VEC_INDEX_SH		16
    393. 

  393. #define __RME_MSIX_VEC_INDEX(_v)	((_v) << __RME_MSIX_VEC_INDEX_SH)
    394. 

  394. #define __RME_DEPTH			0x0000ffff
    395. 

  395. #define RME_DEPTH_Q1			0x00038068
    396. 

  396. #define RME_QCTRL_Q0			0x0003802c
    397. 

  397. #define __RME_INT_LATENCY_TIMER_MK	0xff000000
    398. 

  398. #define __RME_INT_LATENCY_TIMER_SH	24
    399. 

  399. #define __RME_INT_LATENCY_TIMER(_v)	((_v) << __RME_INT_LATENCY_TIMER_SH)
    400. 

  400. #define __RME_INT_DELAY_TIMER_MK	0x00ff0000
    401. 

  401. #define __RME_INT_DELAY_TIMER_SH	16
    402. 

  402. #define __RME_INT_DELAY_TIMER(_v)	((_v) << __RME_INT_DELAY_TIMER_SH)
    403. 

  403. #define __RME_INT_DELAY_DISABLE		0x00008000
    404. 

  404. #define __RME_DLY_DELAY_DISABLE		0x00004000
    405. 

  405. #define __RME_ACK_PENDING		0x00002000
    406. 

  406. #define __RME_FULL_INTERRUPT_DISABLE	0x00001000
    407. 

  407. #define __RME_CTRL_UNUSED10_MK		0x00000c00
    408. 

  408. #define __RME_CTRL_UNUSED10_SH		10
    409. 

  409. #define __RME_CTRL_UNUSED10(_v)		((_v) << __RME_CTRL_UNUSED10_SH)
    410. 

  410. #define __RME_PCIEID_MK			0x00000300
    411. 

  411. #define __RME_PCIEID_SH			8
    412. 

  412. #define __RME_PCIEID(_v)		((_v) << __RME_PCIEID_SH)
    413. 

  413. #define __RME_CTRL_UNUSED00_MK		0x000000fe
    414. 

  414. #define __RME_CTRL_UNUSED00_SH		1
    415. 

  415. #define __RME_CTRL_UNUSED00(_v)		((_v) << __RME_CTRL_UNUSED00_SH)
    416. 

  416. #define __RME_ESIZE			0x00000001
    417. 

  417. #define RME_QCTRL_Q1			0x0003806c
    418. 

  418. #define __RME_CTRL_UNUSED11_MK		0x00000c00
    419. 

  419. #define __RME_CTRL_UNUSED11_SH		10
    420. 

  420. #define __RME_CTRL_UNUSED11(_v)		((_v) << __RME_CTRL_UNUSED11_SH)
    421. 

  421. #define __RME_CTRL_UNUSED01_MK		0x000000fe
    422. 

  422. #define __RME_CTRL_UNUSED01_SH		1
    423. 

  423. #define __RME_CTRL_UNUSED01(_v)		((_v) << __RME_CTRL_UNUSED01_SH)
    424. 

  424. #define PSS_CTL_REG			0x00018800
    425. 

  425. #define __PSS_I2C_CLK_DIV_MK		0x007f0000
    426. 

  426. #define __PSS_I2C_CLK_DIV_SH		16
    427. 

  427. #define __PSS_I2C_CLK_DIV(_v)		((_v) << __PSS_I2C_CLK_DIV_SH)
    428. 

  428. #define __PSS_LMEM_INIT_DONE		0x00001000
    429. 

  429. #define __PSS_LMEM_RESET		0x00000200
    430. 

  430. #define __PSS_LMEM_INIT_EN		0x00000100
    431. 

  431. #define __PSS_LPU1_RESET		0x00000002
    432. 

  432. #define __PSS_LPU0_RESET		0x00000001
    433. 

  433. #define PSS_ERR_STATUS_REG		0x00018810
    434. 

  434. #define __PSS_LPU1_TCM_READ_ERR		0x00200000
    435. 

  435. #define __PSS_LPU0_TCM_READ_ERR		0x00100000
    436. 

  436. #define __PSS_LMEM5_CORR_ERR		0x00080000
    437. 

  437. #define __PSS_LMEM4_CORR_ERR		0x00040000
    438. 

  438. #define __PSS_LMEM3_CORR_ERR		0x00020000
    439. 

  439. #define __PSS_LMEM2_CORR_ERR		0x00010000
    440. 

  440. #define __PSS_LMEM1_CORR_ERR		0x00008000
    441. 

  441. #define __PSS_LMEM0_CORR_ERR		0x00004000
    442. 

  442. #define __PSS_LMEM5_UNCORR_ERR		0x00002000
    443. 

  443. #define __PSS_LMEM4_UNCORR_ERR		0x00001000
    444. 

  444. #define __PSS_LMEM3_UNCORR_ERR		0x00000800
    445. 

  445. #define __PSS_LMEM2_UNCORR_ERR		0x00000400
    446. 

  446. #define __PSS_LMEM1_UNCORR_ERR		0x00000200
    447. 

  447. #define __PSS_LMEM0_UNCORR_ERR		0x00000100
    448. 

  448. #define __PSS_BAL_PERR			0x00000080
    449. 

  449. #define __PSS_DIP_IF_ERR		0x00000040
    450. 

  450. #define __PSS_IOH_IF_ERR		0x00000020
    451. 

  451. #define __PSS_TDS_IF_ERR		0x00000010
    452. 

  452. #define __PSS_RDS_IF_ERR		0x00000008
    453. 

  453. #define __PSS_SGM_IF_ERR		0x00000004
    454. 

  454. #define __PSS_LPU1_RAM_ERR		0x00000002
    455. 

  455. #define __PSS_LPU0_RAM_ERR		0x00000001
    456. 

  456. #define ERR_SET_REG			0x00018818
    457. 

  457. #define __PSS_ERR_STATUS_SET		0x003fffff
    458. 

  458. #define PMM_1T_RESET_REG_P0		0x0002381c
    459. 

  459. #define __PMM_1T_RESET_P		0x00000001
    460. 

  460. #define PMM_1T_RESET_REG_P1		0x00023c1c
    461. 

  461. #define HQM_QSET0_RXQ_DRBL_P0		0x00038000
    462. 

  462. #define __RXQ0_ADD_VECTORS_P		0x80000000
    463. 

  463. #define __RXQ0_STOP_P			0x40000000
    464. 

  464. #define __RXQ0_PRD_PTR_P		0x0000ffff
    465. 

  465. #define HQM_QSET1_RXQ_DRBL_P0		0x00038080
    466. 

  466. #define __RXQ1_ADD_VECTORS_P		0x80000000
    467. 

  467. #define __RXQ1_STOP_P			0x40000000
    468. 

  468. #define __RXQ1_PRD_PTR_P		0x0000ffff
    469. 

  469. #define HQM_QSET0_RXQ_DRBL_P1		0x0003c000
    470. 

  470. #define HQM_QSET1_RXQ_DRBL_P1		0x0003c080
    471. 

  471. #define HQM_QSET0_TXQ_DRBL_P0		0x00038020
    472. 

  472. #define __TXQ0_ADD_VECTORS_P		0x80000000
    473. 

  473. #define __TXQ0_STOP_P			0x40000000
    474. 

  474. #define __TXQ0_PRD_PTR_P		0x0000ffff
    475. 

  475. #define HQM_QSET1_TXQ_DRBL_P0		0x000380a0
    476. 

  476. #define __TXQ1_ADD_VECTORS_P		0x80000000
    477. 

  477. #define __TXQ1_STOP_P			0x40000000
    478. 

  478. #define __TXQ1_PRD_PTR_P		0x0000ffff
    479. 

  479. #define HQM_QSET0_TXQ_DRBL_P1		0x0003c020
    480. 

  480. #define HQM_QSET1_TXQ_DRBL_P1		0x0003c0a0
    481. 

  481. #define HQM_QSET0_IB_DRBL_1_P0		0x00038040
    482. 

  482. #define __IB1_0_ACK_P			0x80000000
    483. 

  483. #define __IB1_0_DISABLE_P		0x40000000
    484. 

  484. #define __IB1_0_COALESCING_CFG_P_MK	0x00ff0000
    485. 

  485. #define __IB1_0_COALESCING_CFG_P_SH	16
    486. 

  486. #define __IB1_0_COALESCING_CFG_P(_v)	((_v) << __IB1_0_COALESCING_CFG_P_SH)
    487. 

  487. #define __IB1_0_NUM_OF_ACKED_EVENTS_P	0x0000ffff
    488. 

  488. #define HQM_QSET1_IB_DRBL_1_P0		0x000380c0
    489. 

  489. #define __IB1_1_ACK_P			0x80000000
    490. 

  490. #define __IB1_1_DISABLE_P		0x40000000
    491. 

  491. #define __IB1_1_COALESCING_CFG_P_MK	0x00ff0000
    492. 

  492. #define __IB1_1_COALESCING_CFG_P_SH	16
    493. 

  493. #define __IB1_1_COALESCING_CFG_P(_v)	((_v) << __IB1_1_COALESCING_CFG_P_SH)
    494. 

  494. #define __IB1_1_NUM_OF_ACKED_EVENTS_P	0x0000ffff
    495. 

  495. #define HQM_QSET0_IB_DRBL_1_P1		0x0003c040
    496. 

  496. #define HQM_QSET1_IB_DRBL_1_P1		0x0003c0c0
    497. 

  497. #define HQM_QSET0_IB_DRBL_2_P0		0x00038060
    498. 

  498. #define __IB2_0_ACK_P			0x80000000
    499. 

  499. #define __IB2_0_DISABLE_P		0x40000000
    500. 

  500. #define __IB2_0_COALESCING_CFG_P_MK	0x00ff0000
    501. 

  501. #define __IB2_0_COALESCING_CFG_P_SH	16
    502. 

  502. #define __IB2_0_COALESCING_CFG_P(_v)	((_v) << __IB2_0_COALESCING_CFG_P_SH)
    503. 

  503. #define __IB2_0_NUM_OF_ACKED_EVENTS_P	0x0000ffff
    504. 

  504. #define HQM_QSET1_IB_DRBL_2_P0		0x000380e0
    505. 

  505. #define __IB2_1_ACK_P			0x80000000
    506. 

  506. #define __IB2_1_DISABLE_P		0x40000000
    507. 

  507. #define __IB2_1_COALESCING_CFG_P_MK	0x00ff0000
    508. 

  508. #define __IB2_1_COALESCING_CFG_P_SH	16
    509. 

  509. #define __IB2_1_COALESCING_CFG_P(_v)	((_v) << __IB2_1_COALESCING_CFG_P_SH)
    510. 

  510. #define __IB2_1_NUM_OF_ACKED_EVENTS_P	0x0000ffff
    511. 

  511. #define HQM_QSET0_IB_DRBL_2_P1		0x0003c060
    512. 

  512. #define HQM_QSET1_IB_DRBL_2_P1		0x0003c0e0
    513. 

  513. 

  514. /*
    515. 

  515.  * These definitions are either in error/missing in spec. Its auto-generated
    516. 

  516.  * from hard coded values in regparse.pl.
    517. 

  517.  */
    518. 

  518. #define __EMPHPOST_AT_4G_MK_FIX		0x0000001c
    519. 

  519. #define __EMPHPOST_AT_4G_SH_FIX		0x00000002
    520. 

  520. #define __EMPHPRE_AT_4G_FIX		0x00000003
    521. 

  521. #define __SFP_TXRATE_EN_FIX		0x00000100
    522. 

  522. #define __SFP_RXRATE_EN_FIX		0x00000080
    523. 

  523. 

  524. /*
    525. 

  525.  * These register definitions are auto-generated from hard coded values
    526. 

  526.  * in regparse.pl.
    527. 

  527.  */
    528. 

  528. 

  529. /*
    530. 

  530.  * These register mapping definitions are auto-generated from mapping tables
    531. 

  531.  * in regparse.pl.
    532. 

  532.  */
    533. 

  533. #define BFA_IOC0_HBEAT_REG		HOST_SEM0_INFO_REG
    534. 

  534. #define BFA_IOC0_STATE_REG		HOST_SEM1_INFO_REG
    535. 

  535. #define BFA_IOC1_HBEAT_REG		HOST_SEM2_INFO_REG
    536. 

  536. #define BFA_IOC1_STATE_REG		HOST_SEM3_INFO_REG
    537. 

  537. #define BFA_FW_USE_COUNT		 HOST_SEM4_INFO_REG
    538. 

  538. #define BFA_IOC_FAIL_SYNC		HOST_SEM5_INFO_REG
    539. 

  539. 

  540. #define CPE_DEPTH_Q(__n) \
    541. 

  541. 	(CPE_DEPTH_Q0 + (__n) * (CPE_DEPTH_Q1 - CPE_DEPTH_Q0))
    542. 

  542. #define CPE_QCTRL_Q(__n) \
    543. 

  543. 	(CPE_QCTRL_Q0 + (__n) * (CPE_QCTRL_Q1 - CPE_QCTRL_Q0))
    544. 

  544. #define CPE_PI_PTR_Q(__n) \
    545. 

  545. 	(CPE_PI_PTR_Q0 + (__n) * (CPE_PI_PTR_Q1 - CPE_PI_PTR_Q0))
    546. 

  546. #define CPE_CI_PTR_Q(__n) \
    547. 

  547. 	(CPE_CI_PTR_Q0 + (__n) * (CPE_CI_PTR_Q1 - CPE_CI_PTR_Q0))
    548. 

  548. #define RME_DEPTH_Q(__n) \
    549. 

  549. 	(RME_DEPTH_Q0 + (__n) * (RME_DEPTH_Q1 - RME_DEPTH_Q0))
    550. 

  550. #define RME_QCTRL_Q(__n) \
    551. 

  551. 	(RME_QCTRL_Q0 + (__n) * (RME_QCTRL_Q1 - RME_QCTRL_Q0))
    552. 

  552. #define RME_PI_PTR_Q(__n) \
    553. 

  553. 	(RME_PI_PTR_Q0 + (__n) * (RME_PI_PTR_Q1 - RME_PI_PTR_Q0))
    554. 

  554. #define RME_CI_PTR_Q(__n) \
    555. 

  555. 	(RME_CI_PTR_Q0 + (__n) * (RME_CI_PTR_Q1 - RME_CI_PTR_Q0))
    556. 

  556. #define HQM_QSET_RXQ_DRBL_P0(__n) \
    557. 

  557. 	(HQM_QSET0_RXQ_DRBL_P0 + (__n) * \
    558. 

  558. 		(HQM_QSET1_RXQ_DRBL_P0 - HQM_QSET0_RXQ_DRBL_P0))
    559. 

  559. #define HQM_QSET_TXQ_DRBL_P0(__n) \
    560. 

  560. 	(HQM_QSET0_TXQ_DRBL_P0 + (__n) * \
    561. 

  561. 		(HQM_QSET1_TXQ_DRBL_P0 - HQM_QSET0_TXQ_DRBL_P0))
    562. 

  562. #define HQM_QSET_IB_DRBL_1_P0(__n) \
    563. 

  563. 	(HQM_QSET0_IB_DRBL_1_P0 + (__n) * \
    564. 

  564. 		(HQM_QSET1_IB_DRBL_1_P0 - HQM_QSET0_IB_DRBL_1_P0))
    565. 

  565. #define HQM_QSET_IB_DRBL_2_P0(__n) \
    566. 

  566. 	(HQM_QSET0_IB_DRBL_2_P0 + (__n) * \
    567. 

  567. 		(HQM_QSET1_IB_DRBL_2_P0 - HQM_QSET0_IB_DRBL_2_P0))
    568. 

  568. #define HQM_QSET_RXQ_DRBL_P1(__n) \
    569. 

  569. 	(HQM_QSET0_RXQ_DRBL_P1 + (__n) * \
    570. 

  570. 		(HQM_QSET1_RXQ_DRBL_P1 - HQM_QSET0_RXQ_DRBL_P1))
    571. 

  571. #define HQM_QSET_TXQ_DRBL_P1(__n) \
    572. 

  572. 	(HQM_QSET0_TXQ_DRBL_P1 + (__n) * \
    573. 

  573. 		(HQM_QSET1_TXQ_DRBL_P1 - HQM_QSET0_TXQ_DRBL_P1))
    574. 

  574. #define HQM_QSET_IB_DRBL_1_P1(__n) \
    575. 

  575. 	(HQM_QSET0_IB_DRBL_1_P1 + (__n) * \
    576. 

  576. 		(HQM_QSET1_IB_DRBL_1_P1 - HQM_QSET0_IB_DRBL_1_P1))
    577. 

  577. #define HQM_QSET_IB_DRBL_2_P1(__n) \
    578. 

  578. 	(HQM_QSET0_IB_DRBL_2_P1 + (__n) * \
    579. 

  579. 		(HQM_QSET1_IB_DRBL_2_P1 - HQM_QSET0_IB_DRBL_2_P1))
    580. 

  580. 

  581. #define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
    582. 

  582. #define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
    583. 

  583. #define CPE_Q_MASK(__q) ((__q) & 0x3)
    584. 

  584. #define RME_Q_MASK(__q) ((__q) & 0x3)
    585. 

  585. 

  586. /*
    587. 

  587.  * PCI MSI-X vector defines
    588. 

  588.  */
    589. 

  589. enum {
    590. 

  590. 	BFA_MSIX_CPE_Q0 = 0,
    591. 

  591. 	BFA_MSIX_CPE_Q1 = 1,
    592. 

  592. 	BFA_MSIX_CPE_Q2 = 2,
    593. 

  593. 	BFA_MSIX_CPE_Q3 = 3,
    594. 

  594. 	BFA_MSIX_RME_Q0 = 4,
    595. 

  595. 	BFA_MSIX_RME_Q1 = 5,
    596. 

  596. 	BFA_MSIX_RME_Q2 = 6,
    597. 

  597. 	BFA_MSIX_RME_Q3 = 7,
    598. 

  598. 	BFA_MSIX_LPU_ERR = 8,
    599. 

  599. 	BFA_MSIX_CT_MAX = 9,
    600. 

  600. };
    601. 

  601. 

  602. /*
    603. 

  603.  * And corresponding host interrupt status bit field defines
    604. 

  604.  */
    605. 

  605. #define __HFN_INT_CPE_Q0		0x00000001U
    606. 

  606. #define __HFN_INT_CPE_Q1		0x00000002U
    607. 

  607. #define __HFN_INT_CPE_Q2		0x00000004U
    608. 

  608. #define __HFN_INT_CPE_Q3		0x00000008U
    609. 

  609. #define __HFN_INT_CPE_Q4		0x00000010U
    610. 

  610. #define __HFN_INT_CPE_Q5		0x00000020U
    611. 

  611. #define __HFN_INT_CPE_Q6		0x00000040U
    612. 

  612. #define __HFN_INT_CPE_Q7		0x00000080U
    613. 

  613. #define __HFN_INT_RME_Q0		0x00000100U
    614. 

  614. #define __HFN_INT_RME_Q1		0x00000200U
    615. 

  615. #define __HFN_INT_RME_Q2		0x00000400U
    616. 

  616. #define __HFN_INT_RME_Q3		0x00000800U
    617. 

  617. #define __HFN_INT_RME_Q4		0x00001000U
    618. 

  618. #define __HFN_INT_RME_Q5		0x00002000U
    619. 

  619. #define __HFN_INT_RME_Q6		0x00004000U
    620. 

  620. #define __HFN_INT_RME_Q7		0x00008000U
    621. 

  621. #define __HFN_INT_ERR_EMC		0x00010000U
    622. 

  622. #define __HFN_INT_ERR_LPU0		0x00020000U
    623. 

  623. #define __HFN_INT_ERR_LPU1		0x00040000U
    624. 

  624. #define __HFN_INT_ERR_PSS		0x00080000U
    625. 

  625. #define __HFN_INT_MBOX_LPU0		0x00100000U
    626. 

  626. #define __HFN_INT_MBOX_LPU1		0x00200000U
    627. 

  627. #define __HFN_INT_MBOX1_LPU0		0x00400000U
    628. 

  628. #define __HFN_INT_MBOX1_LPU1		0x00800000U
    629. 

  629. #define __HFN_INT_LL_HALT		0x01000000U
    630. 

  630. #define __HFN_INT_CPE_MASK		0x000000ffU
    631. 

  631. #define __HFN_INT_RME_MASK		0x0000ff00U
    632. 

  632. 

  633. /*
    634. 

  634.  * catapult memory map.
    635. 

  635.  */
    636. 

  636. #define LL_PGN_HQM0		0x0096
    637. 

  637. #define LL_PGN_HQM1		0x0097
    638. 

  638. #define PSS_SMEM_PAGE_START	0x8000
    639. 

  639. #define PSS_SMEM_PGNUM(_pg0, _ma)	((_pg0) + ((_ma) >> 15))
    640. 

  640. #define PSS_SMEM_PGOFF(_ma)	((_ma) & 0x7fff)
    641. 

  641. 

  642. /*
    643. 

  643.  * End of catapult memory map
    644. 

  644.  */
    645. 

  645. 

  646. #endif /* __BFI_CTREG_H__ */
    647. 

  647.