/drivers/mtd/maps/intel_vr_nor.c

  1/*
  2 * drivers/mtd/maps/intel_vr_nor.c
  3 *
  4 * An MTD map driver for a NOR flash bank on the Expansion Bus of the Intel
  5 * Vermilion Range chipset.
  6 *
  7 * The Vermilion Range Expansion Bus supports four chip selects, each of which
  8 * has 64MiB of address space.  The 2nd BAR of the Expansion Bus PCI Device
  9 * is a 256MiB memory region containing the address spaces for all four of the
 10 * chip selects, with start addresses hardcoded on 64MiB boundaries.
 11 *
 12 * This map driver only supports NOR flash on chip select 0.  The buswidth
 13 * (either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
 14 * and Control Register for Chip Select 0 (EXP_TIMING_CS0).  This driver does
 15 * not modify the value in the EXP_TIMING_CS0 register except to enable writing
 16 * and disable boot acceleration.  The timing parameters in the register are
 17 * assumed to have been properly initialized by the BIOS.  The reset default
 18 * timing parameters are maximally conservative (slow), so access to the flash
 19 * will be slower than it should be if the BIOS has not initialized the timing
 20 * parameters.
 21 *
 22 * Author: Andy Lowe <alowe@mvista.com>
 23 *
 24 * 2006 (c) MontaVista Software, Inc. This file is licensed under
 25 * the terms of the GNU General Public License version 2. This program
 26 * is licensed "as is" without any warranty of any kind, whether express
 27 * or implied.
 28 */
 29
 30#include <linux/module.h>
 31#include <linux/kernel.h>
 32#include <linux/slab.h>
 33#include <linux/pci.h>
 34#include <linux/init.h>
 35#include <linux/mtd/mtd.h>
 36#include <linux/mtd/map.h>
 37#include <linux/mtd/partitions.h>
 38#include <linux/mtd/cfi.h>
 39#include <linux/mtd/flashchip.h>
 40
 41#define DRV_NAME "vr_nor"
 42
 43struct vr_nor_mtd {
 44	void __iomem *csr_base;
 45	struct map_info map;
 46	struct mtd_info *info;
 47	int nr_parts;
 48	struct pci_dev *dev;
 49};
 50
 51/* Expansion Bus Configuration and Status Registers are in BAR 0 */
 52#define EXP_CSR_MBAR 0
 53/* Expansion Bus Memory Window is BAR 1 */
 54#define EXP_WIN_MBAR 1
 55/* Maximum address space for Chip Select 0 is 64MiB */
 56#define CS0_SIZE 0x04000000
 57/* Chip Select 0 is at offset 0 in the Memory Window */
 58#define CS0_START 0x0
 59/* Chip Select 0 Timing Register is at offset 0 in CSR */
 60#define EXP_TIMING_CS0 0x00
 61#define TIMING_CS_EN		(1 << 31)	/* Chip Select Enable */
 62#define TIMING_BOOT_ACCEL_DIS	(1 <<  8)	/* Boot Acceleration Disable */
 63#define TIMING_WR_EN		(1 <<  1)	/* Write Enable */
 64#define TIMING_BYTE_EN		(1 <<  0)	/* 8-bit vs 16-bit bus */
 65#define TIMING_MASK		0x3FFF0000
 66
 67static void __devexit vr_nor_destroy_partitions(struct vr_nor_mtd *p)
 68{
 69	mtd_device_unregister(p->info);
 70}
 71
 72static int __devinit vr_nor_init_partitions(struct vr_nor_mtd *p)
 73{
 74	struct mtd_partition *parts;
 75	static const char *part_probes[] = { "cmdlinepart", NULL };
 76
 77	/* register the flash bank */
 78	/* partition the flash bank */
 79	p->nr_parts = parse_mtd_partitions(p->info, part_probes, &parts, 0);
 80	return mtd_device_register(p->info, parts, p->nr_parts);
 81}
 82
 83static void __devexit vr_nor_destroy_mtd_setup(struct vr_nor_mtd *p)
 84{
 85	map_destroy(p->info);
 86}
 87
 88static int __devinit vr_nor_mtd_setup(struct vr_nor_mtd *p)
 89{
 90	static const char *probe_types[] =
 91	    { "cfi_probe", "jedec_probe", NULL };
 92	const char **type;
 93
 94	for (type = probe_types; !p->info && *type; type++)
 95		p->info = do_map_probe(*type, &p->map);
 96	if (!p->info)
 97		return -ENODEV;
 98
 99	p->info->owner = THIS_MODULE;
100
101	return 0;
102}
103
104static void __devexit vr_nor_destroy_maps(struct vr_nor_mtd *p)
105{
106	unsigned int exp_timing_cs0;
107
108	/* write-protect the flash bank */
109	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
110	exp_timing_cs0 &= ~TIMING_WR_EN;
111	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
112
113	/* unmap the flash window */
114	iounmap(p->map.virt);
115
116	/* unmap the csr window */
117	iounmap(p->csr_base);
118}
119
120/*
121 * Initialize the map_info structure and map the flash.
122 * Returns 0 on success, nonzero otherwise.
123 */
124static int __devinit vr_nor_init_maps(struct vr_nor_mtd *p)
125{
126	unsigned long csr_phys, csr_len;
127	unsigned long win_phys, win_len;
128	unsigned int exp_timing_cs0;
129	int err;
130
131	csr_phys = pci_resource_start(p->dev, EXP_CSR_MBAR);
132	csr_len = pci_resource_len(p->dev, EXP_CSR_MBAR);
133	win_phys = pci_resource_start(p->dev, EXP_WIN_MBAR);
134	win_len = pci_resource_len(p->dev, EXP_WIN_MBAR);
135
136	if (!csr_phys || !csr_len || !win_phys || !win_len)
137		return -ENODEV;
138
139	if (win_len < (CS0_START + CS0_SIZE))
140		return -ENXIO;
141
142	p->csr_base = ioremap_nocache(csr_phys, csr_len);
143	if (!p->csr_base)
144		return -ENOMEM;
145
146	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
147	if (!(exp_timing_cs0 & TIMING_CS_EN)) {
148		dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
149		       "is disabled.\n");
150		err = -ENODEV;
151		goto release;
152	}
153	if ((exp_timing_cs0 & TIMING_MASK) == TIMING_MASK) {
154		dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
155		       "is configured for maximally slow access times.\n");
156	}
157	p->map.name = DRV_NAME;
158	p->map.bankwidth = (exp_timing_cs0 & TIMING_BYTE_EN) ? 1 : 2;
159	p->map.phys = win_phys + CS0_START;
160	p->map.size = CS0_SIZE;
161	p->map.virt = ioremap_nocache(p->map.phys, p->map.size);
162	if (!p->map.virt) {
163		err = -ENOMEM;
164		goto release;
165	}
166	simple_map_init(&p->map);
167
168	/* Enable writes to flash bank */
169	exp_timing_cs0 |= TIMING_BOOT_ACCEL_DIS | TIMING_WR_EN;
170	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
171
172	return 0;
173
174      release:
175	iounmap(p->csr_base);
176	return err;
177}
178
179static struct pci_device_id vr_nor_pci_ids[] = {
180	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x500D)},
181	{0,}
182};
183
184static void __devexit vr_nor_pci_remove(struct pci_dev *dev)
185{
186	struct vr_nor_mtd *p = pci_get_drvdata(dev);
187
188	pci_set_drvdata(dev, NULL);
189	vr_nor_destroy_partitions(p);
190	vr_nor_destroy_mtd_setup(p);
191	vr_nor_destroy_maps(p);
192	kfree(p);
193	pci_release_regions(dev);
194	pci_disable_device(dev);
195}
196
197static int __devinit
198vr_nor_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
199{
200	struct vr_nor_mtd *p = NULL;
201	unsigned int exp_timing_cs0;
202	int err;
203
204	err = pci_enable_device(dev);
205	if (err)
206		goto out;
207
208	err = pci_request_regions(dev, DRV_NAME);
209	if (err)
210		goto disable_dev;
211
212	p = kzalloc(sizeof(*p), GFP_KERNEL);
213	err = -ENOMEM;
214	if (!p)
215		goto release;
216
217	p->dev = dev;
218
219	err = vr_nor_init_maps(p);
220	if (err)
221		goto release;
222
223	err = vr_nor_mtd_setup(p);
224	if (err)
225		goto destroy_maps;
226
227	err = vr_nor_init_partitions(p);
228	if (err)
229		goto destroy_mtd_setup;
230
231	pci_set_drvdata(dev, p);
232
233	return 0;
234
235      destroy_mtd_setup:
236	map_destroy(p->info);
237
238      destroy_maps:
239	/* write-protect the flash bank */
240	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
241	exp_timing_cs0 &= ~TIMING_WR_EN;
242	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
243
244	/* unmap the flash window */
245	iounmap(p->map.virt);
246
247	/* unmap the csr window */
248	iounmap(p->csr_base);
249
250      release:
251	kfree(p);
252	pci_release_regions(dev);
253
254      disable_dev:
255	pci_disable_device(dev);
256
257      out:
258	return err;
259}
260
261static struct pci_driver vr_nor_pci_driver = {
262	.name = DRV_NAME,
263	.probe = vr_nor_pci_probe,
264	.remove = __devexit_p(vr_nor_pci_remove),
265	.id_table = vr_nor_pci_ids,
266};
267
268static int __init vr_nor_mtd_init(void)
269{
270	return pci_register_driver(&vr_nor_pci_driver);
271}
272
273static void __exit vr_nor_mtd_exit(void)
274{
275	pci_unregister_driver(&vr_nor_pci_driver);
276}
277
278module_init(vr_nor_mtd_init);
279module_exit(vr_nor_mtd_exit);
280
281MODULE_AUTHOR("Andy Lowe");
282MODULE_DESCRIPTION("MTD map driver for NOR flash on Intel Vermilion Range");
283MODULE_LICENSE("GPL");
284MODULE_DEVICE_TABLE(pci, vr_nor_pci_ids);