/drivers/media/video/cx231xx/cx231xx-reg.h
C Header | 1564 lines | 1040 code | 174 blank | 350 comment | 0 complexity | 7ad4fddc3f4d906afe8d2e1130ec657d MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
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1/*
2 cx231xx-reg.h - driver for Conexant Cx23100/101/102
3 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef _CX231XX_REG_H
23#define _CX231XX_REG_H
24
25/*****************************************************************************
26 * VBI codes *
27*****************************************************************************/
28
29#define SAV_ACTIVE_VIDEO_FIELD1 0x80
30#define EAV_ACTIVE_VIDEO_FIELD1 0x90
31
32#define SAV_ACTIVE_VIDEO_FIELD2 0xc0
33#define EAV_ACTIVE_VIDEO_FIELD2 0xd0
34
35#define SAV_VBLANK_FIELD1 0xa0
36#define EAV_VBLANK_FIELD1 0xb0
37
38#define SAV_VBLANK_FIELD2 0xe0
39#define EAV_VBLANK_FIELD2 0xf0
40
41#define SAV_VBI_FIELD1 0x20
42#define EAV_VBI_FIELD1 0x30
43
44#define SAV_VBI_FIELD2 0x60
45#define EAV_VBI_FIELD2 0x70
46
47/*****************************************************************************/
48/* Audio ADC Registers */
49#define CH_PWR_CTRL1 0x0000000e
50#define CH_PWR_CTRL2 0x0000000f
51/*****************************************************************************/
52
53#define HOST_REG1 0x000
54#define FLD_FORCE_CHIP_SEL 0x80
55#define FLD_AUTO_INC_DIS 0x20
56#define FLD_PREFETCH_EN 0x10
57/* Reserved [2:3] */
58#define FLD_DIGITAL_PWR_DN 0x02
59#define FLD_SLEEP 0x01
60
61/*****************************************************************************/
62#define HOST_REG2 0x001
63
64/*****************************************************************************/
65#define HOST_REG3 0x002
66
67/*****************************************************************************/
68/* added for polaris */
69#define GPIO_PIN_CTL0 0x3
70#define GPIO_PIN_CTL1 0x4
71#define GPIO_PIN_CTL2 0x5
72#define GPIO_PIN_CTL3 0x6
73#define TS1_PIN_CTL0 0x7
74#define TS1_PIN_CTL1 0x8
75/*****************************************************************************/
76
77#define FLD_CLK_IN_EN 0x80
78#define FLD_XTAL_CTRL 0x70
79#define FLD_BB_CLK_MODE 0x0C
80#define FLD_REF_DIV_PLL 0x02
81#define FLD_REF_SEL_PLL1 0x01
82
83/*****************************************************************************/
84#define CHIP_CTRL 0x100
85/* Reserved [27] */
86/* Reserved [31:21] */
87#define FLD_CHIP_ACFG_DIS 0x00100000
88/* Reserved [19] */
89#define FLD_DUAL_MODE_ADC2 0x00040000
90#define FLD_SIF_EN 0x00020000
91#define FLD_SOFT_RST 0x00010000
92#define FLD_DEVICE_ID 0x0000ffff
93
94/*****************************************************************************/
95#define AFE_CTRL 0x104
96#define AFE_CTRL_C2HH_SRC_CTRL 0x104
97#define FLD_DIF_OUT_SEL 0xc0000000
98#define FLD_AUX_PLL_CLK_ALT_SEL 0x3c000000
99#define FLD_UV_ORDER_MODE 0x02000000
100#define FLD_FUNC_MODE 0x01800000
101#define FLD_ROT1_PHASE_CTL 0x007f8000
102#define FLD_AUD_IN_SEL 0x00004000
103#define FLD_LUMA_IN_SEL 0x00002000
104#define FLD_CHROMA_IN_SEL 0x00001000
105/* reserve [11:10] */
106#define FLD_INV_SPEC_DIS 0x00000200
107#define FLD_VGA_SEL_CH3 0x00000100
108#define FLD_VGA_SEL_CH2 0x00000080
109#define FLD_VGA_SEL_CH1 0x00000040
110#define FLD_DCR_BYP_CH1 0x00000020
111#define FLD_DCR_BYP_CH2 0x00000010
112#define FLD_DCR_BYP_CH3 0x00000008
113#define FLD_EN_12DB_CH3 0x00000004
114#define FLD_EN_12DB_CH2 0x00000002
115#define FLD_EN_12DB_CH1 0x00000001
116
117/* redefine in Cx231xx */
118/*****************************************************************************/
119#define DC_CTRL1 0x108
120/* reserve [31:30] */
121#define FLD_CLAMP_LVL_CH1 0x3fff8000
122#define FLD_CLAMP_LVL_CH2 0x00007fff
123/*****************************************************************************/
124
125/*****************************************************************************/
126#define DC_CTRL2 0x10c
127/* reserve [31:28] */
128#define FLD_CLAMP_LVL_CH3 0x00fffe00
129#define FLD_CLAMP_WIND_LENTH 0x000001e0
130#define FLD_C2HH_SAT_MIN 0x0000001e
131#define FLD_FLT_BYP_SEL 0x00000001
132/*****************************************************************************/
133
134/*****************************************************************************/
135#define DC_CTRL3 0x110
136/* reserve [31:16] */
137#define FLD_ERR_GAIN_CTL 0x00070000
138#define FLD_LPF_MIN 0x0000ffff
139/*****************************************************************************/
140
141/*****************************************************************************/
142#define DC_CTRL4 0x114
143/* reserve [31:31] */
144#define FLD_INTG_CH1 0x7fffffff
145/*****************************************************************************/
146
147/*****************************************************************************/
148#define DC_CTRL5 0x118
149/* reserve [31:31] */
150#define FLD_INTG_CH2 0x7fffffff
151/*****************************************************************************/
152
153/*****************************************************************************/
154#define DC_CTRL6 0x11c
155/* reserve [31:31] */
156#define FLD_INTG_CH3 0x7fffffff
157/*****************************************************************************/
158
159/*****************************************************************************/
160#define PIN_CTRL 0x120
161#define FLD_OEF_AGC_RF 0x00000001
162#define FLD_OEF_AGC_IFVGA 0x00000002
163#define FLD_OEF_AGC_IF 0x00000004
164#define FLD_REG_BO_PUD 0x80000000
165#define FLD_IR_IRQ_STAT 0x40000000
166#define FLD_AUD_IRQ_STAT 0x20000000
167#define FLD_VID_IRQ_STAT 0x10000000
168/* Reserved [27:26] */
169#define FLD_IRQ_N_OUT_EN 0x02000000
170#define FLD_IRQ_N_POLAR 0x01000000
171/* Reserved [23:6] */
172#define FLD_OE_AUX_PLL_CLK 0x00000020
173#define FLD_OE_I2S_BCLK 0x00000010
174#define FLD_OE_I2S_WCLK 0x00000008
175#define FLD_OE_AGC_IF 0x00000004
176#define FLD_OE_AGC_IFVGA 0x00000002
177#define FLD_OE_AGC_RF 0x00000001
178
179/*****************************************************************************/
180#define AUD_IO_CTRL 0x124
181/* Reserved [31:8] */
182#define FLD_I2S_PORT_DIR 0x00000080
183#define FLD_I2S_OUT_SRC 0x00000040
184#define FLD_AUD_CHAN3_SRC 0x00000030
185#define FLD_AUD_CHAN2_SRC 0x0000000c
186#define FLD_AUD_CHAN1_SRC 0x00000003
187
188/*****************************************************************************/
189#define AUD_LOCK1 0x128
190#define FLD_AUD_LOCK_KI_SHIFT 0xc0000000
191#define FLD_AUD_LOCK_KD_SHIFT 0x30000000
192/* Reserved [27:25] */
193#define FLD_EN_AV_LOCK 0x01000000
194#define FLD_VID_COUNT 0x00ffffff
195
196/*****************************************************************************/
197#define AUD_LOCK2 0x12c
198#define FLD_AUD_LOCK_KI_MULT 0xf0000000
199#define FLD_AUD_LOCK_KD_MULT 0x0F000000
200/* Reserved [23:22] */
201#define FLD_AUD_LOCK_FREQ_SHIFT 0x00300000
202#define FLD_AUD_COUNT 0x000fffff
203
204/*****************************************************************************/
205#define AFE_DIAG_CTRL1 0x134
206/* Reserved [31:16] */
207#define FLD_CUV_DLY_LENGTH 0x0000ff00
208#define FLD_YC_DLY_LENGTH 0x000000ff
209
210/*****************************************************************************/
211/* Poalris redefine */
212#define AFE_DIAG_CTRL3 0x138
213/* Reserved [31:26] */
214#define FLD_AUD_DUAL_FLAG_POL 0x02000000
215#define FLD_VID_DUAL_FLAG_POL 0x01000000
216/* Reserved [23:23] */
217#define FLD_COL_CLAMP_DIS_CH1 0x00400000
218#define FLD_COL_CLAMP_DIS_CH2 0x00200000
219#define FLD_COL_CLAMP_DIS_CH3 0x00100000
220
221#define TEST_CTRL1 0x144
222/* Reserved [31:29] */
223#define FLD_LBIST_EN 0x10000000
224/* Reserved [27:10] */
225#define FLD_FI_BIST_INTR_R 0x0000200
226#define FLD_FI_BIST_INTR_L 0x0000100
227#define FLD_BIST_FAIL_AUD_PLL 0x0000080
228#define FLD_BIST_INTR_AUD_PLL 0x0000040
229#define FLD_BIST_FAIL_VID_PLL 0x0000020
230#define FLD_BIST_INTR_VID_PLL 0x0000010
231/* Reserved [3:1] */
232#define FLD_CIR_TEST_DIS 0x00000001
233
234/*****************************************************************************/
235#define TEST_CTRL2 0x148
236#define FLD_TSXCLK_POL_CTL 0x80000000
237#define FLD_ISO_CTL_SEL 0x40000000
238#define FLD_ISO_CTL_EN 0x20000000
239#define FLD_BIST_DEBUGZ 0x10000000
240#define FLD_AUD_BIST_TEST_H 0x0f000000
241/* Reserved [23:22] */
242#define FLD_FLTRN_BIST_TEST_H 0x00020000
243#define FLD_VID_BIST_TEST_H 0x00010000
244/* Reserved [19:17] */
245#define FLD_BIST_TEST_H 0x00010000
246/* Reserved [15:13] */
247#define FLD_TAB_EN 0x00001000
248/* Reserved [11:0] */
249
250/*****************************************************************************/
251#define BIST_STAT 0x14c
252#define FLD_AUD_BIST_FAIL_H 0xfff00000
253#define FLD_FLTRN_BIST_FAIL_H 0x00180000
254#define FLD_VID_BIST_FAIL_H 0x00070000
255#define FLD_AUD_BIST_TST_DONE 0x0000fff0
256#define FLD_FLTRN_BIST_TST_DONE 0x00000008
257#define FLD_VID_BIST_TST_DONE 0x00000007
258
259/*****************************************************************************/
260/* DirectIF registers definition have been moved to DIF_reg.h */
261/*****************************************************************************/
262#define MODE_CTRL 0x400
263#define FLD_AFD_PAL60_DIS 0x20000000
264#define FLD_AFD_FORCE_SECAM 0x10000000
265#define FLD_AFD_FORCE_PALNC 0x08000000
266#define FLD_AFD_FORCE_PAL 0x04000000
267#define FLD_AFD_PALM_SEL 0x03000000
268#define FLD_CKILL_MODE 0x00300000
269#define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */
270#define FLD_CLR_LOCK_STAT 0x00020000
271#define FLD_FAST_LOCK_MD 0x00010000
272#define FLD_WCEN 0x00008000
273#define FLD_CAGCEN 0x00004000
274#define FLD_CKILLEN 0x00002000
275#define FLD_AUTO_SC_LOCK 0x00001000
276#define FLD_MAN_SC_FAST_LOCK 0x00000800
277#define FLD_INPUT_MODE 0x00000600
278#define FLD_AFD_ACQUIRE 0x00000100
279#define FLD_AFD_NTSC_SEL 0x00000080
280#define FLD_AFD_PAL_SEL 0x00000040
281#define FLD_ACFG_DIS 0x00000020
282#define FLD_SQ_PIXEL 0x00000010
283#define FLD_VID_FMT_SEL 0x0000000f
284
285/*****************************************************************************/
286#define OUT_CTRL1 0x404
287#define FLD_POLAR 0x7f000000
288/* Reserved [23] */
289#define FLD_RND_MODE 0x00600000
290#define FLD_VIPCLAMP_EN 0x00100000
291#define FLD_VIPBLANK_EN 0x00080000
292#define FLD_VIP_OPT_AL 0x00040000
293#define FLD_IDID0_SOURCE 0x00020000
294#define FLD_DCMODE 0x00010000
295#define FLD_CLK_GATING 0x0000c000
296#define FLD_CLK_INVERT 0x00002000
297#define FLD_HSFMT 0x00001000
298#define FLD_VALIDFMT 0x00000800
299#define FLD_ACTFMT 0x00000400
300#define FLD_SWAPRAW 0x00000200
301#define FLD_CLAMPRAW_EN 0x00000100
302#define FLD_BLUE_FIELD_EN 0x00000080
303#define FLD_BLUE_FIELD_ACT 0x00000040
304#define FLD_TASKBIT_VAL 0x00000020
305#define FLD_ANC_DATA_EN 0x00000010
306#define FLD_VBIHACTRAW_EN 0x00000008
307#define FLD_MODE10B 0x00000004
308#define FLD_OUT_MODE 0x00000003
309
310/*****************************************************************************/
311#define OUT_CTRL2 0x408
312#define FLD_AUD_GRP 0xc0000000
313#define FLD_SAMPLE_RATE 0x30000000
314#define FLD_AUD_ANC_EN 0x08000000
315#define FLD_EN_C 0x04000000
316#define FLD_EN_B 0x02000000
317#define FLD_EN_A 0x01000000
318/* Reserved [23:20] */
319#define FLD_IDID1_LSB 0x000c0000
320#define FLD_IDID0_LSB 0x00030000
321#define FLD_IDID1_MSB 0x0000ff00
322#define FLD_IDID0_MSB 0x000000ff
323
324/*****************************************************************************/
325#define GEN_STAT 0x40c
326#define FLD_VCR_DETECT 0x00800000
327#define FLD_SPECIAL_PLAY_N 0x00400000
328#define FLD_VPRES 0x00200000
329#define FLD_AGC_LOCK 0x00100000
330#define FLD_CSC_LOCK 0x00080000
331#define FLD_VLOCK 0x00040000
332#define FLD_SRC_LOCK 0x00020000
333#define FLD_HLOCK 0x00010000
334#define FLD_VSYNC_N 0x00008000
335#define FLD_SRC_FIFO_UFLOW 0x00004000
336#define FLD_SRC_FIFO_OFLOW 0x00002000
337#define FLD_FIELD 0x00001000
338#define FLD_AFD_FMT_STAT 0x00000f00
339#define FLD_MV_TYPE2_PAIR 0x00000080
340#define FLD_MV_T3CS 0x00000040
341#define FLD_MV_CS 0x00000020
342#define FLD_MV_PSP 0x00000010
343/* Reserved [3] */
344#define FLD_MV_CDAT 0x00000003
345
346/*****************************************************************************/
347#define INT_STAT_MASK 0x410
348#define FLD_COMB_3D_FIFO_MSK 0x80000000
349#define FLD_WSS_DAT_AVAIL_MSK 0x40000000
350#define FLD_GS2_DAT_AVAIL_MSK 0x20000000
351#define FLD_GS1_DAT_AVAIL_MSK 0x10000000
352#define FLD_CC_DAT_AVAIL_MSK 0x08000000
353#define FLD_VPRES_CHANGE_MSK 0x04000000
354#define FLD_MV_CHANGE_MSK 0x02000000
355#define FLD_END_VBI_EVEN_MSK 0x01000000
356#define FLD_END_VBI_ODD_MSK 0x00800000
357#define FLD_FMT_CHANGE_MSK 0x00400000
358#define FLD_VSYNC_TRAIL_MSK 0x00200000
359#define FLD_HLOCK_CHANGE_MSK 0x00100000
360#define FLD_VLOCK_CHANGE_MSK 0x00080000
361#define FLD_CSC_LOCK_CHANGE_MSK 0x00040000
362#define FLD_SRC_FIFO_UFLOW_MSK 0x00020000
363#define FLD_SRC_FIFO_OFLOW_MSK 0x00010000
364#define FLD_COMB_3D_FIFO_STAT 0x00008000
365#define FLD_WSS_DAT_AVAIL_STAT 0x00004000
366#define FLD_GS2_DAT_AVAIL_STAT 0x00002000
367#define FLD_GS1_DAT_AVAIL_STAT 0x00001000
368#define FLD_CC_DAT_AVAIL_STAT 0x00000800
369#define FLD_VPRES_CHANGE_STAT 0x00000400
370#define FLD_MV_CHANGE_STAT 0x00000200
371#define FLD_END_VBI_EVEN_STAT 0x00000100
372#define FLD_END_VBI_ODD_STAT 0x00000080
373#define FLD_FMT_CHANGE_STAT 0x00000040
374#define FLD_VSYNC_TRAIL_STAT 0x00000020
375#define FLD_HLOCK_CHANGE_STAT 0x00000010
376#define FLD_VLOCK_CHANGE_STAT 0x00000008
377#define FLD_CSC_LOCK_CHANGE_STAT 0x00000004
378#define FLD_SRC_FIFO_UFLOW_STAT 0x00000002
379#define FLD_SRC_FIFO_OFLOW_STAT 0x00000001
380
381/*****************************************************************************/
382#define LUMA_CTRL 0x414
383#define BRIGHTNESS_CTRL_BYTE 0x414
384#define CONTRAST_CTRL_BYTE 0x415
385#define LUMA_CTRL_BYTE_3 0x416
386#define FLD_LUMA_CORE_SEL 0x00c00000
387#define FLD_RANGE 0x00300000
388/* Reserved [19] */
389#define FLD_PEAK_EN 0x00040000
390#define FLD_PEAK_SEL 0x00030000
391#define FLD_CNTRST 0x0000ff00
392#define FLD_BRITE 0x000000ff
393
394/*****************************************************************************/
395#define HSCALE_CTRL 0x418
396#define FLD_HFILT 0x03000000
397#define FLD_HSCALE 0x00ffffff
398
399/*****************************************************************************/
400#define VSCALE_CTRL 0x41c
401#define FLD_LINE_AVG_DIS 0x01000000
402/* Reserved [23:20] */
403#define FLD_VS_INTRLACE 0x00080000
404#define FLD_VFILT 0x00070000
405/* Reserved [15:13] */
406#define FLD_VSCALE 0x00001fff
407
408/*****************************************************************************/
409#define CHROMA_CTRL 0x420
410#define USAT_CTRL_BYTE 0x420
411#define VSAT_CTRL_BYTE 0x421
412#define HUE_CTRL_BYTE 0x422
413#define FLD_C_LPF_EN 0x20000000
414#define FLD_CHR_DELAY 0x1c000000
415#define FLD_C_CORE_SEL 0x03000000
416#define FLD_HUE 0x00ff0000
417#define FLD_VSAT 0x0000ff00
418#define FLD_USAT 0x000000ff
419
420/*****************************************************************************/
421#define VBI_LINE_CTRL1 0x424
422#define FLD_VBI_MD_LINE4 0xff000000
423#define FLD_VBI_MD_LINE3 0x00ff0000
424#define FLD_VBI_MD_LINE2 0x0000ff00
425#define FLD_VBI_MD_LINE1 0x000000ff
426
427/*****************************************************************************/
428#define VBI_LINE_CTRL2 0x428
429#define FLD_VBI_MD_LINE8 0xff000000
430#define FLD_VBI_MD_LINE7 0x00ff0000
431#define FLD_VBI_MD_LINE6 0x0000ff00
432#define FLD_VBI_MD_LINE5 0x000000ff
433
434/*****************************************************************************/
435#define VBI_LINE_CTRL3 0x42c
436#define FLD_VBI_MD_LINE12 0xff000000
437#define FLD_VBI_MD_LINE11 0x00ff0000
438#define FLD_VBI_MD_LINE10 0x0000ff00
439#define FLD_VBI_MD_LINE9 0x000000ff
440
441/*****************************************************************************/
442#define VBI_LINE_CTRL4 0x430
443#define FLD_VBI_MD_LINE16 0xff000000
444#define FLD_VBI_MD_LINE15 0x00ff0000
445#define FLD_VBI_MD_LINE14 0x0000ff00
446#define FLD_VBI_MD_LINE13 0x000000ff
447
448/*****************************************************************************/
449#define VBI_LINE_CTRL5 0x434
450#define FLD_VBI_MD_LINE17 0x000000ff
451
452/*****************************************************************************/
453#define VBI_FC_CFG 0x438
454#define FLD_FC_ALT2 0xff000000
455#define FLD_FC_ALT1 0x00ff0000
456#define FLD_FC_ALT2_TYPE 0x0000f000
457#define FLD_FC_ALT1_TYPE 0x00000f00
458/* Reserved [7:1] */
459#define FLD_FC_SEARCH_MODE 0x00000001
460
461/*****************************************************************************/
462#define VBI_MISC_CFG1 0x43c
463#define FLD_TTX_PKTADRU 0xfff00000
464#define FLD_TTX_PKTADRL 0x000fff00
465/* Reserved [7:6] */
466#define FLD_MOJI_PACK_DIS 0x00000020
467#define FLD_VPS_DEC_DIS 0x00000010
468#define FLD_CRI_MARG_SCALE 0x0000000c
469#define FLD_EDGE_RESYNC_EN 0x00000002
470#define FLD_ADAPT_SLICE_DIS 0x00000001
471
472/*****************************************************************************/
473#define VBI_MISC_CFG2 0x440
474#define FLD_HAMMING_TYPE 0x0f000000
475/* Reserved [23:20] */
476#define FLD_WSS_FIFO_RST 0x00080000
477#define FLD_GS2_FIFO_RST 0x00040000
478#define FLD_GS1_FIFO_RST 0x00020000
479#define FLD_CC_FIFO_RST 0x00010000
480/* Reserved [15:12] */
481#define FLD_VBI3_SDID 0x00000f00
482#define FLD_VBI2_SDID 0x000000f0
483#define FLD_VBI1_SDID 0x0000000f
484
485/*****************************************************************************/
486#define VBI_PAY1 0x444
487#define FLD_GS1_FIFO_DAT 0xFF000000
488#define FLD_GS1_STAT 0x00FF0000
489#define FLD_CC_FIFO_DAT 0x0000FF00
490#define FLD_CC_STAT 0x000000FF
491
492/*****************************************************************************/
493#define VBI_PAY2 0x448
494#define FLD_WSS_FIFO_DAT 0xff000000
495#define FLD_WSS_STAT 0x00ff0000
496#define FLD_GS2_FIFO_DAT 0x0000ff00
497#define FLD_GS2_STAT 0x000000ff
498
499/*****************************************************************************/
500#define VBI_CUST1_CFG1 0x44c
501/* Reserved [31] */
502#define FLD_VBI1_CRIWIN 0x7f000000
503#define FLD_VBI1_SLICE_DIST 0x00f00000
504#define FLD_VBI1_BITINC 0x000fff00
505#define FLD_VBI1_HDELAY 0x000000ff
506
507/*****************************************************************************/
508#define VBI_CUST1_CFG2 0x450
509#define FLD_VBI1_FC_LENGTH 0x1f000000
510#define FLD_VBI1_FRAME_CODE 0x00ffffff
511
512/*****************************************************************************/
513#define VBI_CUST1_CFG3 0x454
514#define FLD_VBI1_HAM_EN 0x80000000
515#define FLD_VBI1_FIFO_MODE 0x70000000
516#define FLD_VBI1_FORMAT_TYPE 0x0f000000
517#define FLD_VBI1_PAYLD_LENGTH 0x00ff0000
518#define FLD_VBI1_CRI_LENGTH 0x0000f000
519#define FLD_VBI1_CRI_MARGIN 0x00000f00
520#define FLD_VBI1_CRI_TIME 0x000000ff
521
522/*****************************************************************************/
523#define VBI_CUST2_CFG1 0x458
524/* Reserved [31] */
525#define FLD_VBI2_CRIWIN 0x7f000000
526#define FLD_VBI2_SLICE_DIST 0x00f00000
527#define FLD_VBI2_BITINC 0x000fff00
528#define FLD_VBI2_HDELAY 0x000000ff
529
530/*****************************************************************************/
531#define VBI_CUST2_CFG2 0x45c
532#define FLD_VBI2_FC_LENGTH 0x1f000000
533#define FLD_VBI2_FRAME_CODE 0x00ffffff
534
535/*****************************************************************************/
536#define VBI_CUST2_CFG3 0x460
537#define FLD_VBI2_HAM_EN 0x80000000
538#define FLD_VBI2_FIFO_MODE 0x70000000
539#define FLD_VBI2_FORMAT_TYPE 0x0f000000
540#define FLD_VBI2_PAYLD_LENGTH 0x00ff0000
541#define FLD_VBI2_CRI_LENGTH 0x0000f000
542#define FLD_VBI2_CRI_MARGIN 0x00000f00
543#define FLD_VBI2_CRI_TIME 0x000000ff
544
545/*****************************************************************************/
546#define VBI_CUST3_CFG1 0x464
547/* Reserved [31] */
548#define FLD_VBI3_CRIWIN 0x7f000000
549#define FLD_VBI3_SLICE_DIST 0x00f00000
550#define FLD_VBI3_BITINC 0x000fff00
551#define FLD_VBI3_HDELAY 0x000000ff
552
553/*****************************************************************************/
554#define VBI_CUST3_CFG2 0x468
555#define FLD_VBI3_FC_LENGTH 0x1f000000
556#define FLD_VBI3_FRAME_CODE 0x00ffffff
557
558/*****************************************************************************/
559#define VBI_CUST3_CFG3 0x46c
560#define FLD_VBI3_HAM_EN 0x80000000
561#define FLD_VBI3_FIFO_MODE 0x70000000
562#define FLD_VBI3_FORMAT_TYPE 0x0f000000
563#define FLD_VBI3_PAYLD_LENGTH 0x00ff0000
564#define FLD_VBI3_CRI_LENGTH 0x0000f000
565#define FLD_VBI3_CRI_MARGIN 0x00000f00
566#define FLD_VBI3_CRI_TIME 0x000000ff
567
568/*****************************************************************************/
569#define HORIZ_TIM_CTRL 0x470
570#define FLD_BGDEL_CNT 0xff000000
571/* Reserved [23:22] */
572#define FLD_HACTIVE_CNT 0x003ff000
573/* Reserved [11:10] */
574#define FLD_HBLANK_CNT 0x000003ff
575
576/*****************************************************************************/
577#define VERT_TIM_CTRL 0x474
578#define FLD_V656BLANK_CNT 0xff000000
579/* Reserved [23:22] */
580#define FLD_VACTIVE_CNT 0x003ff000
581/* Reserved [11:10] */
582#define FLD_VBLANK_CNT 0x000003ff
583
584/*****************************************************************************/
585#define SRC_COMB_CFG 0x478
586#define FLD_CCOMB_2LN_CHECK 0x80000000
587#define FLD_CCOMB_3LN_EN 0x40000000
588#define FLD_CCOMB_2LN_EN 0x20000000
589#define FLD_CCOMB_3D_EN 0x10000000
590/* Reserved [27] */
591#define FLD_LCOMB_3LN_EN 0x04000000
592#define FLD_LCOMB_2LN_EN 0x02000000
593#define FLD_LCOMB_3D_EN 0x01000000
594#define FLD_LUMA_LPF_SEL 0x00c00000
595#define FLD_UV_LPF_SEL 0x00300000
596#define FLD_BLEND_SLOPE 0x000f0000
597#define FLD_CCOMB_REDUCE_EN 0x00008000
598/* Reserved [14:10] */
599#define FLD_SRC_DECIM_RATIO 0x000003ff
600
601/*****************************************************************************/
602#define CHROMA_VBIOFF_CFG 0x47c
603#define FLD_VBI_VOFFSET 0x1f000000
604/* Reserved [23:20] */
605#define FLD_SC_STEP 0x000fffff
606
607/*****************************************************************************/
608#define FIELD_COUNT 0x480
609#define FLD_FIELD_COUNT_FLD 0x000003ff
610
611/*****************************************************************************/
612#define MISC_TIM_CTRL 0x484
613#define FLD_DEBOUNCE_COUNT 0xc0000000
614#define FLD_VT_LINE_CNT_HYST 0x30000000
615/* Reserved [27] */
616#define FLD_AFD_STAT 0x07ff0000
617#define FLD_VPRES_VERT_EN 0x00008000
618/* Reserved [14:12] */
619#define FLD_HR32 0x00000800
620#define FLD_TDALGN 0x00000400
621#define FLD_TDFIELD 0x00000200
622/* Reserved [8:6] */
623#define FLD_TEMPDEC 0x0000003f
624
625/*****************************************************************************/
626#define DFE_CTRL1 0x488
627#define FLD_CLAMP_AUTO_EN 0x80000000
628#define FLD_AGC_AUTO_EN 0x40000000
629#define FLD_VGA_CRUSH_EN 0x20000000
630#define FLD_VGA_AUTO_EN 0x10000000
631#define FLD_VBI_GATE_EN 0x08000000
632#define FLD_CLAMP_LEVEL 0x07000000
633/* Reserved [23:22] */
634#define FLD_CLAMP_SKIP_CNT 0x00300000
635#define FLD_AGC_GAIN 0x000fff00
636/* Reserved [7:6] */
637#define FLD_VGA_GAIN 0x0000003f
638
639/*****************************************************************************/
640#define DFE_CTRL2 0x48c
641#define FLD_VGA_ACQUIRE_RANGE 0x00ff0000
642#define FLD_VGA_TRACK_RANGE 0x0000ff00
643#define FLD_VGA_SYNC 0x000000ff
644
645/*****************************************************************************/
646#define DFE_CTRL3 0x490
647#define FLD_BP_PERCENT 0xff000000
648#define FLD_DFT_THRESHOLD 0x00ff0000
649/* Reserved [15:12] */
650#define FLD_SYNC_WIDTH_SEL 0x00000600
651#define FLD_BP_LOOP_GAIN 0x00000300
652#define FLD_SYNC_LOOP_GAIN 0x000000c0
653/* Reserved [5:4] */
654#define FLD_AGC_LOOP_GAIN 0x0000000c
655#define FLD_DCC_LOOP_GAIN 0x00000003
656
657/*****************************************************************************/
658#define PLL_CTRL 0x494
659#define FLD_PLL_KD 0xff000000
660#define FLD_PLL_KI 0x00ff0000
661#define FLD_PLL_MAX_OFFSET 0x0000ffff
662
663/*****************************************************************************/
664#define HTL_CTRL 0x498
665/* Reserved [31:24] */
666#define FLD_AUTO_LOCK_SPD 0x00080000
667#define FLD_MAN_FAST_LOCK 0x00040000
668#define FLD_HTL_15K_EN 0x00020000
669#define FLD_HTL_500K_EN 0x00010000
670#define FLD_HTL_KD 0x0000ff00
671#define FLD_HTL_KI 0x000000ff
672
673/*****************************************************************************/
674#define COMB_CTRL 0x49c
675#define FLD_COMB_PHASE_LIMIT 0xff000000
676#define FLD_CCOMB_ERR_LIMIT 0x00ff0000
677#define FLD_LUMA_THRESHOLD 0x0000ff00
678#define FLD_LCOMB_ERR_LIMIT 0x000000ff
679
680/*****************************************************************************/
681#define CRUSH_CTRL 0x4a0
682#define FLD_WTW_EN 0x00400000
683#define FLD_CRUSH_FREQ 0x00200000
684#define FLD_MAJ_SEL_EN 0x00100000
685#define FLD_MAJ_SEL 0x000c0000
686/* Reserved [17:15] */
687#define FLD_SYNC_TIP_REDUCE 0x00007e00
688/* Reserved [8:6] */
689#define FLD_SYNC_TIP_INC 0x0000003f
690
691/*****************************************************************************/
692#define SOFT_RST_CTRL 0x4a4
693#define FLD_VD_SOFT_RST 0x00008000
694/* Reserved [14:12] */
695#define FLD_REG_RST_MSK 0x00000800
696#define FLD_VOF_RST_MSK 0x00000400
697#define FLD_MVDET_RST_MSK 0x00000200
698#define FLD_VBI_RST_MSK 0x00000100
699#define FLD_SCALE_RST_MSK 0x00000080
700#define FLD_CHROMA_RST_MSK 0x00000040
701#define FLD_LUMA_RST_MSK 0x00000020
702#define FLD_VTG_RST_MSK 0x00000010
703#define FLD_YCSEP_RST_MSK 0x00000008
704#define FLD_SRC_RST_MSK 0x00000004
705#define FLD_DFE_RST_MSK 0x00000002
706/* Reserved [0] */
707
708/*****************************************************************************/
709#define MV_DT_CTRL1 0x4a8
710/* Reserved [31:29] */
711#define FLD_PSP_STOP_LINE 0x1f000000
712/* Reserved [23:21] */
713#define FLD_PSP_STRT_LINE 0x001f0000
714/* Reserved [15] */
715#define FLD_PSP_LLIMW 0x00007f00
716/* Reserved [7] */
717#define FLD_PSP_ULIMW 0x0000007f
718
719/*****************************************************************************/
720#define MV_DT_CTRL2 0x4aC
721#define FLD_CS_STOPWIN 0xff000000
722#define FLD_CS_STRTWIN 0x00ff0000
723#define FLD_CS_WIDTH 0x0000ff00
724#define FLD_PSP_SPEC_VAL 0x000000ff
725
726/*****************************************************************************/
727#define MV_DT_CTRL3 0x4B0
728#define FLD_AUTO_RATE_DIS 0x80000000
729#define FLD_HLOCK_DIS 0x40000000
730#define FLD_SEL_FIELD_CNT 0x20000000
731#define FLD_CS_TYPE2_SEL 0x10000000
732#define FLD_CS_LINE_THRSH_SEL 0x08000000
733#define FLD_CS_ATHRESH_SEL 0x04000000
734#define FLD_PSP_SPEC_SEL 0x02000000
735#define FLD_PSP_LINES_SEL 0x01000000
736#define FLD_FIELD_CNT 0x00f00000
737#define FLD_CS_TYPE2_CNT 0x000fc000
738#define FLD_CS_LINE_CNT 0x00003f00
739#define FLD_CS_ATHRESH_LEV 0x000000ff
740
741/*****************************************************************************/
742#define CHIP_VERSION 0x4b4
743/* Cx231xx redefine */
744#define VERSION 0x4b4
745#define FLD_REV_ID 0x000000ff
746
747/*****************************************************************************/
748#define MISC_DIAG_CTRL 0x4b8
749/* Reserved [31:24] */
750#define FLD_SC_CONVERGE_THRESH 0x00ff0000
751#define FLD_CCOMB_ERR_LIMIT_3D 0x0000ff00
752#define FLD_LCOMB_ERR_LIMIT_3D 0x000000ff
753
754/*****************************************************************************/
755#define VBI_PASS_CTRL 0x4bc
756#define FLD_VBI_PASS_MD 0x00200000
757#define FLD_VBI_SETUP_DIS 0x00100000
758#define FLD_PASS_LINE_CTRL 0x000fffff
759
760/*****************************************************************************/
761/* Cx231xx redefine */
762#define VCR_DET_CTRL 0x4c0
763#define FLD_EN_FIELD_PHASE_DET 0x80000000
764#define FLD_EN_HEAD_SW_DET 0x40000000
765#define FLD_FIELD_PHASE_LENGTH 0x01ff0000
766/* Reserved [29:25] */
767#define FLD_FIELD_PHASE_DELAY 0x0000ff00
768#define FLD_FIELD_PHASE_LIMIT 0x000000f0
769#define FLD_HEAD_SW_DET_LIMIT 0x0000000f
770
771/*****************************************************************************/
772#define DL_CTL 0x800
773#define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */
774#define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */
775#define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */
776#define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */
777/* Reserved [31:5] */
778#define FLD_START_8051 0x10000000
779#define FLD_DL_ENABLE 0x08000000
780#define FLD_DL_AUTO_INC 0x04000000
781#define FLD_DL_MAP 0x03000000
782
783/*****************************************************************************/
784#define STD_DET_STATUS 0x804
785#define FLD_SPARE_STATUS1 0xff000000
786#define FLD_SPARE_STATUS0 0x00ff0000
787#define FLD_MOD_DET_STATUS1 0x0000ff00
788#define FLD_MOD_DET_STATUS0 0x000000ff
789
790/*****************************************************************************/
791#define AUD_BUILD_NUM 0x806
792#define AUD_VER_NUM 0x807
793#define STD_DET_CTL 0x808
794#define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */
795#define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */
796#define FLD_SPARE_CTL0 0xff000000
797#define FLD_DIS_DBX 0x00800000
798#define FLD_DIS_BTSC 0x00400000
799#define FLD_DIS_NICAM_A2 0x00200000
800#define FLD_VIDEO_PRESENT 0x00100000
801#define FLD_DW8051_VIDEO_FORMAT 0x000f0000
802#define FLD_PREF_DEC_MODE 0x0000ff00
803#define FLD_AUD_CONFIG 0x000000ff
804
805/*****************************************************************************/
806#define DW8051_INT 0x80c
807#define FLD_VIDEO_PRESENT_CHANGE 0x80000000
808#define FLD_VIDEO_CHANGE 0x40000000
809#define FLD_RDS_READY 0x20000000
810#define FLD_AC97_INT 0x10000000
811#define FLD_NICAM_BIT_ERROR_TOO_HIGH 0x08000000
812#define FLD_NICAM_LOCK 0x04000000
813#define FLD_NICAM_UNLOCK 0x02000000
814#define FLD_DFT4_TH_CMP 0x01000000
815/* Reserved [23:22] */
816#define FLD_LOCK_IND_INT 0x00200000
817#define FLD_DFT3_TH_CMP 0x00100000
818#define FLD_DFT2_TH_CMP 0x00080000
819#define FLD_DFT1_TH_CMP 0x00040000
820#define FLD_FM2_DFT_TH_CMP 0x00020000
821#define FLD_FM1_DFT_TH_CMP 0x00010000
822#define FLD_VIDEO_PRESENT_EN 0x00008000
823#define FLD_VIDEO_CHANGE_EN 0x00004000
824#define FLD_RDS_READY_EN 0x00002000
825#define FLD_AC97_INT_EN 0x00001000
826#define FLD_NICAM_BIT_ERROR_TOO_HIGH_EN 0x00000800
827#define FLD_NICAM_LOCK_EN 0x00000400
828#define FLD_NICAM_UNLOCK_EN 0x00000200
829#define FLD_DFT4_TH_CMP_EN 0x00000100
830/* Reserved [7] */
831#define FLD_DW8051_INT6_CTL1 0x00000040
832#define FLD_DW8051_INT5_CTL1 0x00000020
833#define FLD_DW8051_INT4_CTL1 0x00000010
834#define FLD_DW8051_INT3_CTL1 0x00000008
835#define FLD_DW8051_INT2_CTL1 0x00000004
836#define FLD_DW8051_INT1_CTL1 0x00000002
837#define FLD_DW8051_INT0_CTL1 0x00000001
838
839/*****************************************************************************/
840#define GENERAL_CTL 0x810
841#define FLD_RDS_INT 0x80000000
842#define FLD_NBER_INT 0x40000000
843#define FLD_NLL_INT 0x20000000
844#define FLD_IFL_INT 0x10000000
845#define FLD_FDL_INT 0x08000000
846#define FLD_AFC_INT 0x04000000
847#define FLD_AMC_INT 0x02000000
848#define FLD_AC97_INT_CTL 0x01000000
849#define FLD_RDS_INT_DIS 0x00800000
850#define FLD_NBER_INT_DIS 0x00400000
851#define FLD_NLL_INT_DIS 0x00200000
852#define FLD_IFL_INT_DIS 0x00100000
853#define FLD_FDL_INT_DIS 0x00080000
854#define FLD_FC_INT_DIS 0x00040000
855#define FLD_AMC_INT_DIS 0x00020000
856#define FLD_AC97_INT_DIS 0x00010000
857#define FLD_REV_NUM 0x0000ff00
858/* Reserved [7:5] */
859#define FLD_DBX_SOFT_RESET_REG 0x00000010
860#define FLD_AD_SOFT_RESET_REG 0x00000008
861#define FLD_SRC_SOFT_RESET_REG 0x00000004
862#define FLD_CDMOD_SOFT_RESET 0x00000002
863#define FLD_8051_SOFT_RESET 0x00000001
864
865/*****************************************************************************/
866#define AAGC_CTL 0x814
867#define FLD_AFE_12DB_EN 0x80000000
868#define FLD_AAGC_DEFAULT_EN 0x40000000
869#define FLD_AAGC_DEFAULT 0x3f000000
870/* Reserved [23] */
871#define FLD_AAGC_GAIN 0x00600000
872#define FLD_AAGC_TH 0x001f0000
873/* Reserved [15:14] */
874#define FLD_AAGC_HYST2 0x00003f00
875/* Reserved [7:6] */
876#define FLD_AAGC_HYST1 0x0000003f
877
878/*****************************************************************************/
879#define IF_SRC_CTL 0x818
880#define FLD_DBX_BYPASS 0x80000000
881/* Reserved [30:25] */
882#define FLD_IF_SRC_MODE 0x01000000
883/* Reserved [23:18] */
884#define FLD_IF_SRC_PHASE_INC 0x0001ffff
885
886/*****************************************************************************/
887#define ANALOG_DEMOD_CTL 0x81c
888#define FLD_ROT1_PHACC_PROG 0xffff0000
889/* Reserved [15] */
890#define FLD_FM1_DELAY_FIX 0x00007000
891#define FLD_PDF4_SHIFT 0x00000c00
892#define FLD_PDF3_SHIFT 0x00000300
893#define FLD_PDF2_SHIFT 0x000000c0
894#define FLD_PDF1_SHIFT 0x00000030
895#define FLD_FMBYPASS_MODE2 0x00000008
896#define FLD_FMBYPASS_MODE1 0x00000004
897#define FLD_NICAM_MODE 0x00000002
898#define FLD_BTSC_FMRADIO_MODE 0x00000001
899
900/*****************************************************************************/
901#define ROT_FREQ_CTL 0x820
902#define FLD_ROT3_PHACC_PROG 0xffff0000
903#define FLD_ROT2_PHACC_PROG 0x0000ffff
904
905/*****************************************************************************/
906#define FM_CTL 0x824
907#define FLD_FM2_DC_FB_SHIFT 0xf0000000
908#define FLD_FM2_DC_INT_SHIFT 0x0f000000
909#define FLD_FM2_AFC_RESET 0x00800000
910#define FLD_FM2_DC_PASS_IN 0x00400000
911#define FLD_FM2_DAGC_SHIFT 0x00380000
912#define FLD_FM2_CORDIC_SHIFT 0x00070000
913#define FLD_FM1_DC_FB_SHIFT 0x0000f000
914#define FLD_FM1_DC_INT_SHIFT 0x00000f00
915#define FLD_FM1_AFC_RESET 0x00000080
916#define FLD_FM1_DC_PASS_IN 0x00000040
917#define FLD_FM1_DAGC_SHIFT 0x00000038
918#define FLD_FM1_CORDIC_SHIFT 0x00000007
919
920/*****************************************************************************/
921#define LPF_PDF_CTL 0x828
922/* Reserved [31:30] */
923#define FLD_LPF32_SHIFT1 0x30000000
924#define FLD_LPF32_SHIFT2 0x0c000000
925#define FLD_LPF160_SHIFTA 0x03000000
926#define FLD_LPF160_SHIFTB 0x00c00000
927#define FLD_LPF160_SHIFTC 0x00300000
928#define FLD_LPF32_COEF_SEL2 0x000c0000
929#define FLD_LPF32_COEF_SEL1 0x00030000
930#define FLD_LPF160_COEF_SELC 0x0000c000
931#define FLD_LPF160_COEF_SELB 0x00003000
932#define FLD_LPF160_COEF_SELA 0x00000c00
933#define FLD_LPF160_IN_EN_REG 0x00000300
934#define FLD_PDF4_PDF_SEL 0x000000c0
935#define FLD_PDF3_PDF_SEL 0x00000030
936#define FLD_PDF2_PDF_SEL 0x0000000c
937#define FLD_PDF1_PDF_SEL 0x00000003
938
939/*****************************************************************************/
940#define DFT1_CTL1 0x82c
941#define FLD_DFT1_DWELL 0xffff0000
942#define FLD_DFT1_FREQ 0x0000ffff
943
944/*****************************************************************************/
945#define DFT1_CTL2 0x830
946#define FLD_DFT1_THRESHOLD 0xffffff00
947#define FLD_DFT1_CMP_CTL 0x00000080
948#define FLD_DFT1_AVG 0x00000070
949/* Reserved [3:1] */
950#define FLD_DFT1_START 0x00000001
951
952/*****************************************************************************/
953#define DFT1_STATUS 0x834
954#define FLD_DFT1_DONE 0x80000000
955#define FLD_DFT1_TH_CMP_STAT 0x40000000
956#define FLD_DFT1_RESULT 0x3fffffff
957
958/*****************************************************************************/
959#define DFT2_CTL1 0x838
960#define FLD_DFT2_DWELL 0xffff0000
961#define FLD_DFT2_FREQ 0x0000ffff
962
963/*****************************************************************************/
964#define DFT2_CTL2 0x83C
965#define FLD_DFT2_THRESHOLD 0xffffff00
966#define FLD_DFT2_CMP_CTL 0x00000080
967#define FLD_DFT2_AVG 0x00000070
968/* Reserved [3:1] */
969#define FLD_DFT2_START 0x00000001
970
971/*****************************************************************************/
972#define DFT2_STATUS 0x840
973#define FLD_DFT2_DONE 0x80000000
974#define FLD_DFT2_TH_CMP_STAT 0x40000000
975#define FLD_DFT2_RESULT 0x3fffffff
976
977/*****************************************************************************/
978#define DFT3_CTL1 0x844
979#define FLD_DFT3_DWELL 0xffff0000
980#define FLD_DFT3_FREQ 0x0000ffff
981
982/*****************************************************************************/
983#define DFT3_CTL2 0x848
984#define FLD_DFT3_THRESHOLD 0xffffff00
985#define FLD_DFT3_CMP_CTL 0x00000080
986#define FLD_DFT3_AVG 0x00000070
987/* Reserved [3:1] */
988#define FLD_DFT3_START 0x00000001
989
990/*****************************************************************************/
991#define DFT3_STATUS 0x84c
992#define FLD_DFT3_DONE 0x80000000
993#define FLD_DFT3_TH_CMP_STAT 0x40000000
994#define FLD_DFT3_RESULT 0x3fffffff
995
996/*****************************************************************************/
997#define DFT4_CTL1 0x850
998#define FLD_DFT4_DWELL 0xffff0000
999#define FLD_DFT4_FREQ 0x0000ffff
1000
1001/*****************************************************************************/
1002#define DFT4_CTL2 0x854
1003#define FLD_DFT4_THRESHOLD 0xffffff00
1004#define FLD_DFT4_CMP_CTL 0x00000080
1005#define FLD_DFT4_AVG 0x00000070
1006/* Reserved [3:1] */
1007#define FLD_DFT4_START 0x00000001
1008
1009/*****************************************************************************/
1010#define DFT4_STATUS 0x858
1011#define FLD_DFT4_DONE 0x80000000
1012#define FLD_DFT4_TH_CMP_STAT 0x40000000
1013#define FLD_DFT4_RESULT 0x3fffffff
1014
1015/*****************************************************************************/
1016#define AM_MTS_DET 0x85c
1017#define FLD_AM_MTS_MODE 0x80000000
1018/* Reserved [30:26] */
1019#define FLD_AM_SUB 0x02000000
1020#define FLD_AM_GAIN_EN 0x01000000
1021/* Reserved [23:16] */
1022#define FLD_AMMTS_GAIN_SCALE 0x0000e000
1023#define FLD_MTS_PDF_SHIFT 0x00001800
1024#define FLD_AM_REG_GAIN 0x00000700
1025#define FLD_AGC_REF 0x000000ff
1026
1027/*****************************************************************************/
1028#define ANALOG_MUX_CTL 0x860
1029/* Reserved [31:29] */
1030#define FLD_MUX21_SEL 0x10000000
1031#define FLD_MUX20_SEL 0x08000000
1032#define FLD_MUX19_SEL 0x04000000
1033#define FLD_MUX18_SEL 0x02000000
1034#define FLD_MUX17_SEL 0x01000000
1035#define FLD_MUX16_SEL 0x00800000
1036#define FLD_MUX15_SEL 0x00400000
1037#define FLD_MUX14_SEL 0x00300000
1038#define FLD_MUX13_SEL 0x000C0000
1039#define FLD_MUX12_SEL 0x00020000
1040#define FLD_MUX11_SEL 0x00018000
1041#define FLD_MUX10_SEL 0x00004000
1042#define FLD_MUX9_SEL 0x00002000
1043#define FLD_MUX8_SEL 0x00001000
1044#define FLD_MUX7_SEL 0x00000800
1045#define FLD_MUX6_SEL 0x00000600
1046#define FLD_MUX5_SEL 0x00000100
1047#define FLD_MUX4_SEL 0x000000c0
1048#define FLD_MUX3_SEL 0x00000030
1049#define FLD_MUX2_SEL 0x0000000c
1050#define FLD_MUX1_SEL 0x00000003
1051
1052/*****************************************************************************/
1053/* Cx231xx redefine */
1054#define DPLL_CTRL1 0x864
1055#define DIG_PLL_CTL1 0x864
1056
1057#define FLD_PLL_STATUS 0x07000000
1058#define FLD_BANDWIDTH_SELECT 0x00030000
1059#define FLD_PLL_SHIFT_REG 0x00007000
1060#define FLD_PHASE_SHIFT 0x000007ff
1061
1062/*****************************************************************************/
1063/* Cx231xx redefine */
1064#define DPLL_CTRL2 0x868
1065#define DIG_PLL_CTL2 0x868
1066#define FLD_PLL_UNLOCK_THR 0xff000000
1067#define FLD_PLL_LOCK_THR 0x00ff0000
1068/* Reserved [15:8] */
1069#define FLD_AM_PDF_SEL2 0x000000c0
1070#define FLD_AM_PDF_SEL1 0x00000030
1071#define FLD_DPLL_FSM_CTRL 0x0000000c
1072/* Reserved [1] */
1073#define FLD_PLL_PILOT_DET 0x00000001
1074
1075/*****************************************************************************/
1076/* Cx231xx redefine */
1077#define DPLL_CTRL3 0x86c
1078#define DIG_PLL_CTL3 0x86c
1079#define FLD_DISABLE_LOOP 0x01000000
1080#define FLD_A1_DS1_SEL 0x000c0000
1081#define FLD_A1_DS2_SEL 0x00030000
1082#define FLD_A1_KI 0x0000ff00
1083#define FLD_A1_KD 0x000000ff
1084
1085/*****************************************************************************/
1086/* Cx231xx redefine */
1087#define DPLL_CTRL4 0x870
1088#define DIG_PLL_CTL4 0x870
1089#define FLD_A2_DS1_SEL 0x000c0000
1090#define FLD_A2_DS2_SEL 0x00030000
1091#define FLD_A2_KI 0x0000ff00
1092#define FLD_A2_KD 0x000000ff
1093
1094/*****************************************************************************/
1095/* Cx231xx redefine */
1096#define DPLL_CTRL5 0x874
1097#define DIG_PLL_CTL5 0x874
1098#define FLD_TRK_DS1_SEL 0x000c0000
1099#define FLD_TRK_DS2_SEL 0x00030000
1100#define FLD_TRK_KI 0x0000ff00
1101#define FLD_TRK_KD 0x000000ff
1102
1103/*****************************************************************************/
1104#define DEEMPH_GAIN_CTL 0x878
1105#define FLD_DEEMPH2_GAIN 0xFFFF0000
1106#define FLD_DEEMPH1_GAIN 0x0000FFFF
1107
1108/*****************************************************************************/
1109/* Cx231xx redefine */
1110#define DEEMPH_COEFF1 0x87c
1111#define DEEMPH_COEF1 0x87c
1112#define FLD_DEEMPH_B0 0xffff0000
1113#define FLD_DEEMPH_A0 0x0000ffff
1114
1115/*****************************************************************************/
1116/* Cx231xx redefine */
1117#define DEEMPH_COEFF2 0x880
1118#define DEEMPH_COEF2 0x880
1119#define FLD_DEEMPH_B1 0xFFFF0000
1120#define FLD_DEEMPH_A1 0x0000FFFF
1121
1122/*****************************************************************************/
1123#define DBX1_CTL1 0x884
1124#define FLD_DBX1_WBE_GAIN 0xffff0000
1125#define FLD_DBX1_IN_GAIN 0x0000ffff
1126
1127/*****************************************************************************/
1128#define DBX1_CTL2 0x888
1129#define FLD_DBX1_SE_BYPASS 0xffff0000
1130#define FLD_DBX1_SE_GAIN 0x0000ffff
1131
1132/*****************************************************************************/
1133#define DBX1_RMS_SE 0x88C
1134#define FLD_DBX1_RMS_WBE 0xffff0000
1135…Large files files are truncated, but you can click here to view the full file