/contrib/groff/doc/grnexmpl.me
https://bitbucket.org/freebsd/freebsd-head/ · Unknown · 84 lines · 84 code · 0 blank · 0 comment · 0 complexity · 5bb549755d2a9773d25a1b9da58ccbb7 MD5 · raw file
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- delim $$
- define // 'over down 10'
- define sw 'phi sub'
- define aa 'A sub'
- define vv 'V sub'
- define mm 'M sub'
- define nn 'N sub'
- define cc 'C sub'
- define ll 'L sub'
- define rr 'R sub'
- define ss 'S sub'
- define gg 'g sub'
- define ff 'F sub'
- define qq 'Q sub'
- define qqq '{C prime} sub'
- define pp 'P sub'
- define tt 'T sub'
- define zz 'Z sub'
- define kk 'K sub'
- define ii 'I sub'
- define iis 'IC sub'
- define e2 '2 sup'
- define sunc '{ sin x } / x'
- define vddm1V 'vv DD - 1 ^ roman V'
- define vssp1V 'vv SS + 1 ^ roman V'
- .EN
- .pp
- The following slide shows the complete schematics of the
- fully-differential RIC. The operation includes a
- correlated-double-sampling phase that occurs once every 256
- clock periods, also called the
- .i "spreading ratio" .
- This reset phase is controlled by clocks $ DP sub 1 $ and $ DP
- sub 2 $ in which the integrator is initialized by totally
- removing the charge from $ cc F $ and storing the low-frequency
- noise of the op amp in $ cc C $. At the same time the comparison
- thresholds are set.
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- roman 1
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- file grnexmpl.g
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- The faster clocks are $ PN $, $ ITS $ and $ SP $. The sampling
- capacitor $ cc S $ performs the delayed subtraction of a sample
- of the input signal $ +- ^ vv SIG $ and a choice of $ - ^ vv REF
- $, $ AGND $ or $ + ^ vv REF $ according to the operations
- performed by the logic partially depicted operating on past
- results of the comparisons. The synchronous comparators are
- reset at this fast rates, thus performing one comparison for
- every fast clock cycle. The dynamic common-mode feedback
- arrangement operates synchronously with the reset time slot and
- its configuration is equivalent to that in the differential
- feedback path.