/contrib/groff/doc/grnexmpl.me

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  8. .EQ
  9. gsize 12
  10. delim $$
  11. define // 'over down 10'
  12. define sw 'phi sub'
  13. define aa 'A sub'
  14. define vv 'V sub'
  15. define mm 'M sub'
  16. define nn 'N sub'
  17. define cc 'C sub'
  18. define ll 'L sub'
  19. define rr 'R sub'
  20. define ss 'S sub'
  21. define gg 'g sub'
  22. define ff 'F sub'
  23. define qq 'Q sub'
  24. define qqq '{C prime} sub'
  25. define pp 'P sub'
  26. define tt 'T sub'
  27. define zz 'Z sub'
  28. define kk 'K sub'
  29. define ii 'I sub'
  30. define iis 'IC sub'
  31. define e2 '2 sup'
  32. define sunc '{ sin x } / x'
  33. define vddm1V 'vv DD - 1 ^ roman V'
  34. define vssp1V 'vv SS + 1 ^ roman V'
  35. .EN
  36. .pp
  37. The following slide shows the complete schematics of the
  38. fully-differential RIC. The operation includes a
  39. correlated-double-sampling phase that occurs once every 256
  40. clock periods, also called the
  41. .i "spreading ratio" .
  42. This reset phase is controlled by clocks $ DP sub 1 $ and $ DP
  43. sub 2 $ in which the integrator is initialized by totally
  44. removing the charge from $ cc F $ and storing the low-frequency
  45. noise of the op amp in $ cc C $. At the same time the comparison
  46. thresholds are set.
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  55. .GS
  56. roman 1
  57. italics 2
  58. bold 3
  59. special 4
  60. narrow 1
  61. medium 3
  62. thick 5
  63. width 5.5
  64. l mg
  65. file grnexmpl.g
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  69. .EN
  70. .)b
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  73. .pp
  74. The faster clocks are $ PN $, $ ITS $ and $ SP $. The sampling
  75. capacitor $ cc S $ performs the delayed subtraction of a sample
  76. of the input signal $ +- ^ vv SIG $ and a choice of $ - ^ vv REF
  77. $, $ AGND $ or $ + ^ vv REF $ according to the operations
  78. performed by the logic partially depicted operating on past
  79. results of the comparisons. The synchronous comparators are
  80. reset at this fast rates, thus performing one comparison for
  81. every fast clock cycle. The dynamic common-mode feedback
  82. arrangement operates synchronously with the reset time slot and
  83. its configuration is equivalent to that in the differential
  84. feedback path.