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Unknown | 84 lines | 84 code | 0 blank | 0 comment | 0 complexity | 5bb549755d2a9773d25a1b9da58ccbb7 MD5 | raw file pp 12 tp 12 sp 12 fi 0 1
 6.po 1i 11i
 9gsize 12
10delim $$
11define // 'over down 10'
12define sw 'phi sub'
13define aa 'A sub'
14define vv 'V sub'
15define mm 'M sub'
16define nn 'N sub'
17define cc 'C sub'
18define ll 'L sub'
19define rr 'R sub'
20define ss 'S sub'
21define gg 'g sub'
22define ff 'F sub'
23define qq 'Q sub'
24define qqq '{C prime} sub'
25define pp 'P sub'
26define tt 'T sub'
27define zz 'Z sub'
28define kk 'K sub'
29define ii 'I sub'
30define iis 'IC sub'
31define e2 '2 sup'
32define sunc '{ sin x } / x'
33define vddm1V 'vv DD - 1 ^ roman V'
34define vssp1V 'vv SS + 1 ^ roman V'
37The following slide shows the complete schematics of the
38fully-differential RIC. The operation includes a
39correlated-double-sampling phase that occurs once every 256
40clock periods, also called the
41.i "spreading ratio" .
42This reset phase is controlled by clocks $ DP sub 1 $ and $ DP
43sub 2 $ in which the integrator is initialized by totally
44removing the charge from $ cc F $ and storing the low-frequency
45noise of the op amp in $ cc C $. At the same time the comparison
46thresholds are set.
48.po -0.2i
49.sp 2
53gsize -4
56roman 1
57italics 2
58bold 3
59special 4
60narrow 1
61medium 3
62thick 5
63width 5.5
64l mg
65file grnexmpl.g
68gsize +4
72.po +0.2i
74The faster clocks are $ PN $, $ ITS $ and $ SP $. The sampling
75capacitor $ cc S $ performs the delayed subtraction of a sample
76of the input signal $ +- ^ vv SIG $ and a choice of $ - ^ vv REF
77$, $ AGND $ or $ + ^ vv REF $ according to the operations
78performed by the logic partially depicted operating on past
79results of the comparisons. The synchronous comparators are
80reset at this fast rates, thus performing one comparison for
81every fast clock cycle. The dynamic common-mode feedback
82arrangement operates synchronously with the reset time slot and
83its configuration is equivalent to that in the differential
84feedback path.