/drivers/net/sun4i/sun4i_wemac.h
C Header | 251 lines | 176 code | 37 blank | 38 comment | 0 complexity | dff20ddf47683c56852595abf5de84cd MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/* 2 * drivers/net/sun4i/sun4i_wemac.h 3 * 4 * (C) Copyright 2007-2012 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23/* 24 * wemac Ethernet 25 */ 26 27#ifndef _WEMACX_H_ 28#define _WEMACX_H_ 29 30/* registers define */ 31/* EMAC register */ 32#define EMAC_BASE 0x01C0B000 33 34#define EMAC_CTL_REG (0x00) 35#define EMAC_TX_MODE_REG (0x04) 36#define EMAC_TX_FLOW_REG (0x08) 37#define EMAC_TX_CTL0_REG (0x0C) 38#define EMAC_TX_CTL1_REG (0x10) 39#define EMAC_TX_INS_REG (0x14) 40#define EMAC_TX_PL0_REG (0x18) 41#define EMAC_TX_PL1_REG (0x1C) 42#define EMAC_TX_STA_REG (0x20) 43#define EMAC_TX_IO_DATA_REG (0x24) 44#define EMAC_TX_IO_DATA1_REG (0x28) 45#define EMAC_TX_TSVL0_REG (0x2C) 46#define EMAC_TX_TSVH0_REG (0x30) 47#define EMAC_TX_TSVL1_REG (0x34) 48#define EMAC_TX_TSVH1_REG (0x38) 49#define EMAC_RX_CTL_REG (0x3C) 50#define EMAC_RX_HASH0_REG (0x40) 51#define EMAC_RX_HASH1_REG (0x44) 52#define EMAC_RX_STA_REG (0x48) 53#define EMAC_RX_IO_DATA_REG (0x4C) 54#define EMAC_RX_FBC_REG (0x50) 55#define EMAC_INT_CTL_REG (0x54) 56#define EMAC_INT_STA_REG (0x58) 57#define EMAC_MAC_CTL0_REG (0x5C) 58#define EMAC_MAC_CTL1_REG (0x60) 59#define EMAC_MAC_IPGT_REG (0x64) 60#define EMAC_MAC_IPGR_REG (0x68) 61#define EMAC_MAC_CLRT_REG (0x6C) 62#define EMAC_MAC_MAXF_REG (0x70) 63#define EMAC_MAC_SUPP_REG (0x74) 64#define EMAC_MAC_TEST_REG (0x78) 65#define EMAC_MAC_MCFG_REG (0x7C) 66#define EMAC_MAC_MCMD_REG (0x80) 67#define EMAC_MAC_MADR_REG (0x84) 68#define EMAC_MAC_MWTD_REG (0x88) 69#define EMAC_MAC_MRDD_REG (0x8C) 70#define EMAC_MAC_MIND_REG (0x90) 71#define EMAC_MAC_SSRR_REG (0x94) 72#define EMAC_MAC_A0_REG (0x98) 73#define EMAC_MAC_A1_REG (0x9C) 74#define EMAC_MAC_A2_REG (0xA0) 75#define EMAC_SAFX_L_REG0 (0xA4) 76#define EMAC_SAFX_H_REG0 (0xA8) 77#define EMAC_SAFX_L_REG1 (0xAC) 78#define EMAC_SAFX_H_REG1 (0xB0) 79#define EMAC_SAFX_L_REG2 (0xB4) 80#define EMAC_SAFX_H_REG2 (0xB8) 81#define EMAC_SAFX_L_REG3 (0xBC) 82#define EMAC_SAFX_H_REG3 (0xC0) 83 84/* PIO register */ 85//#define PIO_BASE 0x01c20800 86 87#define PA_CFG0_REG (0x00) 88#define PA_CFG1_REG (0x04) 89#define PA_CFG2_REG (0x08) 90#define PA_DAT_REG (0x0c) 91#define PA_DRV0_REG (0x10) 92#define PA_DRV1_REG (0x14) 93#define PA_PULLUP0_REG (0x18) 94#define PA_PULLUP1_REG (0x1c) 95#define PB_CFG0_REG (0x20) 96#define PB_CFG1_REG (0x24) 97#define PB_CFG2_REG (0x28) 98#define PB_DAT_REG (0x2c) 99#define PB_DRV0_REG (0x30) 100#define PB_DRV1_REG (0x34) 101#define PB_PULLUP0_REG (0x38) 102#define PB_PULLUP1_REG (0x3c) 103#define PC_CFG0_REG (0x40) 104#define PC_CFG1_REG (0x44) 105#define PC_CFG2_REG (0x48) 106#define PC_DAT_REG (0x4c) 107#define PC_DRV0_REG (0x50) 108#define PC_DRV1_REG (0x54) 109#define PC_PULLUP0_REG (0x58) 110#define PC_PULLUP1_REG (0x5c) 111#define PD_CFG0_REG (0x60) 112#define PD_CFG1_REG (0x64) 113#define PD_CFG2_REG (0x68) 114#define PD_CFG3_REG (0x6c) 115#define PD_DAT_REG (0x70) 116#define PD_DRV0_REG (0x74) 117#define PD_DRV1_REG (0x78) 118#define PD_PULLUP0_REG (0x7c) 119#define PD_PULLUP1_REG (0x80) 120#define PE_CFG0_REG (0x84) 121#define PE_CFG1_REG (0x88) 122#define PE_DAT_REG (0x8c) 123#define PE_DRV_REG (0x90) 124#define PE_PULLUP_REG (0x94) 125#define PF_DRV_REG (0x98) 126#define PF_PULLUP_REG (0x9c) 127#define PD_INT_REG (0xa0) 128 129 130//CCM register 131#define CCM_BASE 0x01c20000 132 133#define CCM_AC320_MACC_REG (0x00) 134#define CCM_AUDIO_HOSC_REG (0x04) 135#define CCM_AHB_APB_REG (0x08) 136#define CCM_AHB_GATING_REG (0x0c) 137#define CCM_APB_GATING_REG (0x10) 138#define CCM_NFC_MS_REG (0x14) 139#define CCM_SD01_REG (0x18) 140#define CCM_SD23_REG (0x1c) 141#define CCM_DRAM_PLL_REG (0x20) 142#define CCM_DE_REG (0x24) 143#define CCM_LCD_MACC_REG (0x28) 144#define CCM_TV_CSI_REG (0x2c) 145#define CCM_VIDEO_PLL_REG (0x30) 146#define CCM_IR_CLK_REG (0x34) 147#define CCM_AUDIO_CLK_REG (0x38) 148#define CCM_TS_CLK_REG (0x3c) 149#define CCM_AVS_USB_CLK_REG (0x40) 150#define CCM_PID_CLK_REG (0xd0) 151#define CCM_WAKEUP_PENDING_REG (0xd4) 152 153 154//SRAMC register 155#define SRAMC_BASE 0x01c00000 156#define SRAMC_CFG_REG (0x04) 157 158 159//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~registers define~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 160 161 162//set up PHY 163#define PHY_AUTO_NEGOTIOATION 1 // 0: Normal 1: Auto(default) 164#define PHY_SPEED 1 // 0: 10M 1: 100M(default) 165#define EMAC_MAC_FULL 1 //0: Half duplex 1: Full duplex(default) 166 167//set up EMAC TX 168#define EMAC_TX_TM 0 //0: CPU 1: DMA(default) 169#define EMAC_TX_AB_M 1 //0: Disable 1: Aborted frame enable(default) 170 171//set up EMAC RX 172#define EMAC_RX_TM 0 //0: CPU 1: DMA(default) 173#define EMAC_RX_DRQ_MODE 0 //0: DRQ asserted 1: DRQ automatically(default) 174 175#define EMAC_RX_PA 0 //0: Normal(default) 1: Pass all Frames 176#define EMAC_RX_PCF 0 //0: Normal(default) 1: Pass Control Frames 177#define EMAC_RX_PCRCE 0 //0: Normal(default) 1: Pass Frames with CRC Error 178#define EMAC_RX_POR 1 //0: Normal 1: Pass Frames length out of range(default) 179#define EMAC_RX_PLE 0 //0: Normal(default) 1: Pass Frames with Length Error 180#define EMAC_RX_UCAD 1 //0: Not accept 1: Accept unicast Packets(default) 181#define EMAC_RX_DAF 1 //0: Normal(default) 1: DA Filtering 182#define EMAC_RX_MCO 1 //0: Not accept 1: Accept multicast Packets(default) 183#define EMAC_RX_MHF 0 //0: Disable(default) 1: Enable Hash filter 184#define EMAC_RX_BCO 1 //0: Not accept 1: Accept Broadcast Packets(default) 185#define EMAC_RX_SAF 0 //0: Disable(default) 1: Enable SA Filtering 186#define EMAC_RX_SAIF 0 //0: Normal(default) 1: Inverse Filtering 187 188//set up MAC 189#define EMAC_MAC_TFC 1 //0: Disable 1: Enable Transmit Flow Control(default) 190#define EMAC_MAC_RFC 1 //0: Disable 1: Enable Receive Flow Control(default) 191 192 193 194#define EMAC_MAC_FLC 1 //0: Disable 1: Enable MAC Frame Length Checking(default) 195#define EMAC_MAC_HF 0 //0: Disable(default) 1: Enable Huge Frame 196#define EMAC_MAC_DCRC 0 //0: Disable(default) 1: Enable MAC Delayed CRC 197#define EMAC_MAC_CRC 1 //0: Disable 1: Enable MAC CRC(default) 198#define EMAC_MAC_PC 1 //0: Disable 1: Enable MAC PAD Short frames(default) 199#define EMAC_MAC_VC 0 //0: Disable(default) 1: Enable MAC PAD Short frames and append CRC 200#define EMAC_MAC_ADP 0 //0: Disable(default) 1: Enable MAC auto detect Short frames 201#define EMAC_MAC_PRE 0 //0: Disable(default) 1: Enable 202#define EMAC_MAC_LPE 0 //0: Disable(default) 1: Enable 203#define EMAC_MAC_NB 0 //0: Disable(default) 1: Enable no back off 204#define EMAC_MAC_BNB 0 //0: Disable(default) 1: Enable 205#define EMAC_MAC_ED 0 //0: Disable(default) 1: Enable 206 207#if EMAC_MAC_FULL 208 #define EMAC_MAC_IPGT 0x15 209#else 210 #define EMAC_MAC_IPGT 0x12 211#endif 212 213#define EMAC_MAC_NBTB_IPG1 0xC 214#define EMAC_MAC_NBTB_IPG2 0x12 215 216#define EMAC_MAC_CW 0x37 217#define EMAC_MAC_RM 0xF 218 219#define EMAC_MAC_MFL 0x0600 220 221#define EMAC_MAP1 222 223//define receive status 224#define EMAC_CRCERR (1<<4) 225#define EMAC_LENERR (3<<5) 226 227#define WEMAC_PLATF_8BITONLY (0x0001) 228#define WEMAC_PLATF_16BITONLY (0x0002) 229#define WEMAC_PLATF_32BITONLY (0x0004) 230#define WEMAC_PLATF_EXT_PHY (0x0008) 231#define WEMAC_PLATF_NO_EEPROM (0x0010) 232#define WEMAC_PLATF_SIMPLE_PHY (0x0020) /* Use NSR to find LinkStatus */ 233 234#define EMAC_EEPROM_MAGIC (0x444D394B) 235 236/* platfrom data for platfrom device structure's platfrom_data field */ 237 238struct wemac_plat_data { 239 unsigned int flags; 240 unsigned char dev_addr[6]; 241 242 /* allow replacement IO routines */ 243 244 void (*inblk)(void __iomem *reg, void *data, int len); 245 void (*outblk)(void __iomem *reg, void *data, int len); 246 void (*dumpblk)(void __iomem *reg, int len); 247}; 248 249 250#endif /* _WEMACX_H_ */ 251