/drivers/net/qlcnic/qlcnic_hw.c

https://bitbucket.org/ndreys/linux-sunxi · C · 1723 lines · 1405 code · 256 blank · 62 comment · 170 complexity · d1314bef6475bd30924a129932ab4567 MD5 · raw file

  1. /*
  2. * QLogic qlcnic NIC Driver
  3. * Copyright (c) 2009-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qlcnic for copyright and licensing details.
  6. */
  7. #include "qlcnic.h"
  8. #include <linux/slab.h>
  9. #include <net/ip.h>
  10. #include <linux/bitops.h>
  11. #define MASK(n) ((1ULL<<(n))-1)
  12. #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  13. #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  14. #define CRB_BLK(off) ((off >> 20) & 0x3f)
  15. #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  16. #define CRB_WINDOW_2M (0x130060)
  17. #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  18. #define CRB_INDIRECT_2M (0x1e0000UL)
  19. #ifndef readq
  20. static inline u64 readq(void __iomem *addr)
  21. {
  22. return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  23. }
  24. #endif
  25. #ifndef writeq
  26. static inline void writeq(u64 val, void __iomem *addr)
  27. {
  28. writel(((u32) (val)), (addr));
  29. writel(((u32) (val >> 32)), (addr + 4));
  30. }
  31. #endif
  32. static const struct crb_128M_2M_block_map
  33. crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  34. {{{0, 0, 0, 0} } }, /* 0: PCI */
  35. {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
  36. {1, 0x0110000, 0x0120000, 0x130000},
  37. {1, 0x0120000, 0x0122000, 0x124000},
  38. {1, 0x0130000, 0x0132000, 0x126000},
  39. {1, 0x0140000, 0x0142000, 0x128000},
  40. {1, 0x0150000, 0x0152000, 0x12a000},
  41. {1, 0x0160000, 0x0170000, 0x110000},
  42. {1, 0x0170000, 0x0172000, 0x12e000},
  43. {0, 0x0000000, 0x0000000, 0x000000},
  44. {0, 0x0000000, 0x0000000, 0x000000},
  45. {0, 0x0000000, 0x0000000, 0x000000},
  46. {0, 0x0000000, 0x0000000, 0x000000},
  47. {0, 0x0000000, 0x0000000, 0x000000},
  48. {0, 0x0000000, 0x0000000, 0x000000},
  49. {1, 0x01e0000, 0x01e0800, 0x122000},
  50. {0, 0x0000000, 0x0000000, 0x000000} } },
  51. {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  52. {{{0, 0, 0, 0} } }, /* 3: */
  53. {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  54. {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
  55. {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
  56. {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
  57. {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
  58. {0, 0x0000000, 0x0000000, 0x000000},
  59. {0, 0x0000000, 0x0000000, 0x000000},
  60. {0, 0x0000000, 0x0000000, 0x000000},
  61. {0, 0x0000000, 0x0000000, 0x000000},
  62. {0, 0x0000000, 0x0000000, 0x000000},
  63. {0, 0x0000000, 0x0000000, 0x000000},
  64. {0, 0x0000000, 0x0000000, 0x000000},
  65. {0, 0x0000000, 0x0000000, 0x000000},
  66. {0, 0x0000000, 0x0000000, 0x000000},
  67. {0, 0x0000000, 0x0000000, 0x000000},
  68. {0, 0x0000000, 0x0000000, 0x000000},
  69. {0, 0x0000000, 0x0000000, 0x000000},
  70. {0, 0x0000000, 0x0000000, 0x000000},
  71. {0, 0x0000000, 0x0000000, 0x000000},
  72. {1, 0x08f0000, 0x08f2000, 0x172000} } },
  73. {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
  74. {0, 0x0000000, 0x0000000, 0x000000},
  75. {0, 0x0000000, 0x0000000, 0x000000},
  76. {0, 0x0000000, 0x0000000, 0x000000},
  77. {0, 0x0000000, 0x0000000, 0x000000},
  78. {0, 0x0000000, 0x0000000, 0x000000},
  79. {0, 0x0000000, 0x0000000, 0x000000},
  80. {0, 0x0000000, 0x0000000, 0x000000},
  81. {0, 0x0000000, 0x0000000, 0x000000},
  82. {0, 0x0000000, 0x0000000, 0x000000},
  83. {0, 0x0000000, 0x0000000, 0x000000},
  84. {0, 0x0000000, 0x0000000, 0x000000},
  85. {0, 0x0000000, 0x0000000, 0x000000},
  86. {0, 0x0000000, 0x0000000, 0x000000},
  87. {0, 0x0000000, 0x0000000, 0x000000},
  88. {1, 0x09f0000, 0x09f2000, 0x176000} } },
  89. {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
  90. {0, 0x0000000, 0x0000000, 0x000000},
  91. {0, 0x0000000, 0x0000000, 0x000000},
  92. {0, 0x0000000, 0x0000000, 0x000000},
  93. {0, 0x0000000, 0x0000000, 0x000000},
  94. {0, 0x0000000, 0x0000000, 0x000000},
  95. {0, 0x0000000, 0x0000000, 0x000000},
  96. {0, 0x0000000, 0x0000000, 0x000000},
  97. {0, 0x0000000, 0x0000000, 0x000000},
  98. {0, 0x0000000, 0x0000000, 0x000000},
  99. {0, 0x0000000, 0x0000000, 0x000000},
  100. {0, 0x0000000, 0x0000000, 0x000000},
  101. {0, 0x0000000, 0x0000000, 0x000000},
  102. {0, 0x0000000, 0x0000000, 0x000000},
  103. {0, 0x0000000, 0x0000000, 0x000000},
  104. {1, 0x0af0000, 0x0af2000, 0x17a000} } },
  105. {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
  106. {0, 0x0000000, 0x0000000, 0x000000},
  107. {0, 0x0000000, 0x0000000, 0x000000},
  108. {0, 0x0000000, 0x0000000, 0x000000},
  109. {0, 0x0000000, 0x0000000, 0x000000},
  110. {0, 0x0000000, 0x0000000, 0x000000},
  111. {0, 0x0000000, 0x0000000, 0x000000},
  112. {0, 0x0000000, 0x0000000, 0x000000},
  113. {0, 0x0000000, 0x0000000, 0x000000},
  114. {0, 0x0000000, 0x0000000, 0x000000},
  115. {0, 0x0000000, 0x0000000, 0x000000},
  116. {0, 0x0000000, 0x0000000, 0x000000},
  117. {0, 0x0000000, 0x0000000, 0x000000},
  118. {0, 0x0000000, 0x0000000, 0x000000},
  119. {0, 0x0000000, 0x0000000, 0x000000},
  120. {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
  121. {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
  122. {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
  123. {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
  124. {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
  125. {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
  126. {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
  127. {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
  128. {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
  129. {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
  130. {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
  131. {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
  132. {{{0, 0, 0, 0} } }, /* 23: */
  133. {{{0, 0, 0, 0} } }, /* 24: */
  134. {{{0, 0, 0, 0} } }, /* 25: */
  135. {{{0, 0, 0, 0} } }, /* 26: */
  136. {{{0, 0, 0, 0} } }, /* 27: */
  137. {{{0, 0, 0, 0} } }, /* 28: */
  138. {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
  139. {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
  140. {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
  141. {{{0} } }, /* 32: PCI */
  142. {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
  143. {1, 0x2110000, 0x2120000, 0x130000},
  144. {1, 0x2120000, 0x2122000, 0x124000},
  145. {1, 0x2130000, 0x2132000, 0x126000},
  146. {1, 0x2140000, 0x2142000, 0x128000},
  147. {1, 0x2150000, 0x2152000, 0x12a000},
  148. {1, 0x2160000, 0x2170000, 0x110000},
  149. {1, 0x2170000, 0x2172000, 0x12e000},
  150. {0, 0x0000000, 0x0000000, 0x000000},
  151. {0, 0x0000000, 0x0000000, 0x000000},
  152. {0, 0x0000000, 0x0000000, 0x000000},
  153. {0, 0x0000000, 0x0000000, 0x000000},
  154. {0, 0x0000000, 0x0000000, 0x000000},
  155. {0, 0x0000000, 0x0000000, 0x000000},
  156. {0, 0x0000000, 0x0000000, 0x000000},
  157. {0, 0x0000000, 0x0000000, 0x000000} } },
  158. {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
  159. {{{0} } }, /* 35: */
  160. {{{0} } }, /* 36: */
  161. {{{0} } }, /* 37: */
  162. {{{0} } }, /* 38: */
  163. {{{0} } }, /* 39: */
  164. {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
  165. {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
  166. {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
  167. {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
  168. {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
  169. {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
  170. {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
  171. {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
  172. {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
  173. {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
  174. {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
  175. {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
  176. {{{0} } }, /* 52: */
  177. {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
  178. {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
  179. {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
  180. {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
  181. {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
  182. {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
  183. {{{0} } }, /* 59: I2C0 */
  184. {{{0} } }, /* 60: I2C1 */
  185. {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
  186. {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
  187. {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
  188. };
  189. /*
  190. * top 12 bits of crb internal address (hub, agent)
  191. */
  192. static const unsigned crb_hub_agt[64] = {
  193. 0,
  194. QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
  195. QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
  196. QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
  197. 0,
  198. QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
  199. QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
  200. QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
  201. QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
  202. QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
  203. QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
  204. QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
  205. QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
  206. QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
  207. QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
  208. QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
  209. QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
  210. QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
  211. QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
  212. QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
  213. QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
  214. QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
  215. QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
  216. QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
  217. QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
  218. QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
  219. QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
  220. 0,
  221. QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
  222. QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
  223. 0,
  224. QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
  225. 0,
  226. QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
  227. QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
  228. 0,
  229. 0,
  230. 0,
  231. 0,
  232. 0,
  233. QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
  234. 0,
  235. QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
  236. QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
  237. QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
  238. QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
  239. QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
  240. QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
  241. QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
  242. QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
  243. QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
  244. QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
  245. 0,
  246. QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
  247. QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
  248. QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
  249. QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
  250. 0,
  251. QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
  252. QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
  253. QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
  254. 0,
  255. QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
  256. 0,
  257. };
  258. /* PCI Windowing for DDR regions. */
  259. #define QLCNIC_PCIE_SEM_TIMEOUT 10000
  260. int
  261. qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
  262. {
  263. int done = 0, timeout = 0;
  264. while (!done) {
  265. done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
  266. if (done == 1)
  267. break;
  268. if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
  269. dev_err(&adapter->pdev->dev,
  270. "Failed to acquire sem=%d lock; holdby=%d\n",
  271. sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
  272. return -EIO;
  273. }
  274. msleep(1);
  275. }
  276. if (id_reg)
  277. QLCWR32(adapter, id_reg, adapter->portnum);
  278. return 0;
  279. }
  280. void
  281. qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
  282. {
  283. QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
  284. }
  285. static int
  286. qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
  287. struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
  288. {
  289. u32 i, producer, consumer;
  290. struct qlcnic_cmd_buffer *pbuf;
  291. struct cmd_desc_type0 *cmd_desc;
  292. struct qlcnic_host_tx_ring *tx_ring;
  293. i = 0;
  294. if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
  295. return -EIO;
  296. tx_ring = adapter->tx_ring;
  297. __netif_tx_lock_bh(tx_ring->txq);
  298. producer = tx_ring->producer;
  299. consumer = tx_ring->sw_consumer;
  300. if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
  301. netif_tx_stop_queue(tx_ring->txq);
  302. smp_mb();
  303. if (qlcnic_tx_avail(tx_ring) > nr_desc) {
  304. if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
  305. netif_tx_wake_queue(tx_ring->txq);
  306. } else {
  307. adapter->stats.xmit_off++;
  308. __netif_tx_unlock_bh(tx_ring->txq);
  309. return -EBUSY;
  310. }
  311. }
  312. do {
  313. cmd_desc = &cmd_desc_arr[i];
  314. pbuf = &tx_ring->cmd_buf_arr[producer];
  315. pbuf->skb = NULL;
  316. pbuf->frag_count = 0;
  317. memcpy(&tx_ring->desc_head[producer],
  318. &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
  319. producer = get_next_index(producer, tx_ring->num_desc);
  320. i++;
  321. } while (i != nr_desc);
  322. tx_ring->producer = producer;
  323. qlcnic_update_cmd_producer(adapter, tx_ring);
  324. __netif_tx_unlock_bh(tx_ring->txq);
  325. return 0;
  326. }
  327. static int
  328. qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
  329. __le16 vlan_id, unsigned op)
  330. {
  331. struct qlcnic_nic_req req;
  332. struct qlcnic_mac_req *mac_req;
  333. struct qlcnic_vlan_req *vlan_req;
  334. u64 word;
  335. memset(&req, 0, sizeof(struct qlcnic_nic_req));
  336. req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
  337. word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
  338. req.req_hdr = cpu_to_le64(word);
  339. mac_req = (struct qlcnic_mac_req *)&req.words[0];
  340. mac_req->op = op;
  341. memcpy(mac_req->mac_addr, addr, 6);
  342. vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
  343. vlan_req->vlan_id = vlan_id;
  344. return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
  345. }
  346. static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr)
  347. {
  348. struct list_head *head;
  349. struct qlcnic_mac_list_s *cur;
  350. /* look up if already exists */
  351. list_for_each(head, &adapter->mac_list) {
  352. cur = list_entry(head, struct qlcnic_mac_list_s, list);
  353. if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
  354. return 0;
  355. }
  356. cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
  357. if (cur == NULL) {
  358. dev_err(&adapter->netdev->dev,
  359. "failed to add mac address filter\n");
  360. return -ENOMEM;
  361. }
  362. memcpy(cur->mac_addr, addr, ETH_ALEN);
  363. if (qlcnic_sre_macaddr_change(adapter,
  364. cur->mac_addr, 0, QLCNIC_MAC_ADD)) {
  365. kfree(cur);
  366. return -EIO;
  367. }
  368. list_add_tail(&cur->list, &adapter->mac_list);
  369. return 0;
  370. }
  371. void qlcnic_set_multi(struct net_device *netdev)
  372. {
  373. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  374. struct netdev_hw_addr *ha;
  375. static const u8 bcast_addr[ETH_ALEN] = {
  376. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
  377. };
  378. u32 mode = VPORT_MISS_MODE_DROP;
  379. if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
  380. return;
  381. qlcnic_nic_add_mac(adapter, adapter->mac_addr);
  382. qlcnic_nic_add_mac(adapter, bcast_addr);
  383. if (netdev->flags & IFF_PROMISC) {
  384. if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
  385. mode = VPORT_MISS_MODE_ACCEPT_ALL;
  386. goto send_fw_cmd;
  387. }
  388. if ((netdev->flags & IFF_ALLMULTI) ||
  389. (netdev_mc_count(netdev) > adapter->max_mc_count)) {
  390. mode = VPORT_MISS_MODE_ACCEPT_MULTI;
  391. goto send_fw_cmd;
  392. }
  393. if (!netdev_mc_empty(netdev)) {
  394. netdev_for_each_mc_addr(ha, netdev) {
  395. qlcnic_nic_add_mac(adapter, ha->addr);
  396. }
  397. }
  398. send_fw_cmd:
  399. qlcnic_nic_set_promisc(adapter, mode);
  400. }
  401. int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
  402. {
  403. struct qlcnic_nic_req req;
  404. u64 word;
  405. memset(&req, 0, sizeof(struct qlcnic_nic_req));
  406. req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
  407. word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
  408. ((u64)adapter->portnum << 16);
  409. req.req_hdr = cpu_to_le64(word);
  410. req.words[0] = cpu_to_le64(mode);
  411. return qlcnic_send_cmd_descs(adapter,
  412. (struct cmd_desc_type0 *)&req, 1);
  413. }
  414. void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
  415. {
  416. struct qlcnic_mac_list_s *cur;
  417. struct list_head *head = &adapter->mac_list;
  418. while (!list_empty(head)) {
  419. cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
  420. qlcnic_sre_macaddr_change(adapter,
  421. cur->mac_addr, 0, QLCNIC_MAC_DEL);
  422. list_del(&cur->list);
  423. kfree(cur);
  424. }
  425. }
  426. void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
  427. {
  428. struct qlcnic_filter *tmp_fil;
  429. struct hlist_node *tmp_hnode, *n;
  430. struct hlist_head *head;
  431. int i;
  432. for (i = 0; i < adapter->fhash.fmax; i++) {
  433. head = &(adapter->fhash.fhead[i]);
  434. hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode)
  435. {
  436. if (jiffies >
  437. (QLCNIC_FILTER_AGE * HZ + tmp_fil->ftime)) {
  438. qlcnic_sre_macaddr_change(adapter,
  439. tmp_fil->faddr, tmp_fil->vlan_id,
  440. tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
  441. QLCNIC_MAC_DEL);
  442. spin_lock_bh(&adapter->mac_learn_lock);
  443. adapter->fhash.fnum--;
  444. hlist_del(&tmp_fil->fnode);
  445. spin_unlock_bh(&adapter->mac_learn_lock);
  446. kfree(tmp_fil);
  447. }
  448. }
  449. }
  450. }
  451. void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
  452. {
  453. struct qlcnic_filter *tmp_fil;
  454. struct hlist_node *tmp_hnode, *n;
  455. struct hlist_head *head;
  456. int i;
  457. for (i = 0; i < adapter->fhash.fmax; i++) {
  458. head = &(adapter->fhash.fhead[i]);
  459. hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
  460. qlcnic_sre_macaddr_change(adapter, tmp_fil->faddr,
  461. tmp_fil->vlan_id, tmp_fil->vlan_id ?
  462. QLCNIC_MAC_VLAN_DEL : QLCNIC_MAC_DEL);
  463. spin_lock_bh(&adapter->mac_learn_lock);
  464. adapter->fhash.fnum--;
  465. hlist_del(&tmp_fil->fnode);
  466. spin_unlock_bh(&adapter->mac_learn_lock);
  467. kfree(tmp_fil);
  468. }
  469. }
  470. }
  471. /*
  472. * Send the interrupt coalescing parameter set by ethtool to the card.
  473. */
  474. int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
  475. {
  476. struct qlcnic_nic_req req;
  477. int rv;
  478. memset(&req, 0, sizeof(struct qlcnic_nic_req));
  479. req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
  480. req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
  481. ((u64) adapter->portnum << 16));
  482. req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
  483. req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
  484. ((u64) adapter->ahw->coal.rx_time_us) << 16);
  485. req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
  486. ((u64) adapter->ahw->coal.type) << 32 |
  487. ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
  488. rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
  489. if (rv != 0)
  490. dev_err(&adapter->netdev->dev,
  491. "Could not send interrupt coalescing parameters\n");
  492. return rv;
  493. }
  494. int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
  495. {
  496. struct qlcnic_nic_req req;
  497. u64 word;
  498. int rv;
  499. if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
  500. return 0;
  501. memset(&req, 0, sizeof(struct qlcnic_nic_req));
  502. req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
  503. word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
  504. req.req_hdr = cpu_to_le64(word);
  505. req.words[0] = cpu_to_le64(enable);
  506. rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
  507. if (rv != 0)
  508. dev_err(&adapter->netdev->dev,
  509. "Could not send configure hw lro request\n");
  510. return rv;
  511. }
  512. int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
  513. {
  514. struct qlcnic_nic_req req;
  515. u64 word;
  516. int rv;
  517. if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
  518. return 0;
  519. memset(&req, 0, sizeof(struct qlcnic_nic_req));
  520. req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
  521. word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
  522. ((u64)adapter->portnum << 16);
  523. req.req_hdr = cpu_to_le64(word);
  524. req.words[0] = cpu_to_le64(enable);
  525. rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
  526. if (rv != 0)
  527. dev_err(&adapter->netdev->dev,
  528. "Could not send configure bridge mode request\n");
  529. adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
  530. return rv;
  531. }
  532. #define RSS_HASHTYPE_IP_TCP 0x3
  533. int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
  534. {
  535. struct qlcnic_nic_req req;
  536. u64 word;
  537. int i, rv;
  538. static const u64 key[] = {
  539. 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
  540. 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
  541. 0x255b0ec26d5a56daULL
  542. };
  543. memset(&req, 0, sizeof(struct qlcnic_nic_req));
  544. req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
  545. word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
  546. req.req_hdr = cpu_to_le64(word);
  547. /*
  548. * RSS request:
  549. * bits 3-0: hash_method
  550. * 5-4: hash_type_ipv4
  551. * 7-6: hash_type_ipv6
  552. * 8: enable
  553. * 9: use indirection table
  554. * 47-10: reserved
  555. * 63-48: indirection table mask
  556. */
  557. word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
  558. ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
  559. ((u64)(enable & 0x1) << 8) |
  560. ((0x7ULL) << 48);
  561. req.words[0] = cpu_to_le64(word);
  562. for (i = 0; i < 5; i++)
  563. req.words[i+1] = cpu_to_le64(key[i]);
  564. rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
  565. if (rv != 0)
  566. dev_err(&adapter->netdev->dev, "could not configure RSS\n");
  567. return rv;
  568. }
  569. int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd)
  570. {
  571. struct qlcnic_nic_req req;
  572. struct qlcnic_ipaddr *ipa;
  573. u64 word;
  574. int rv;
  575. memset(&req, 0, sizeof(struct qlcnic_nic_req));
  576. req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
  577. word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
  578. req.req_hdr = cpu_to_le64(word);
  579. req.words[0] = cpu_to_le64(cmd);
  580. ipa = (struct qlcnic_ipaddr *)&req.words[1];
  581. ipa->ipv4 = ip;
  582. rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
  583. if (rv != 0)
  584. dev_err(&adapter->netdev->dev,
  585. "could not notify %s IP 0x%x reuqest\n",
  586. (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
  587. return rv;
  588. }
  589. int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
  590. {
  591. struct qlcnic_nic_req req;
  592. u64 word;
  593. int rv;
  594. memset(&req, 0, sizeof(struct qlcnic_nic_req));
  595. req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
  596. word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
  597. req.req_hdr = cpu_to_le64(word);
  598. req.words[0] = cpu_to_le64(enable | (enable << 8));
  599. rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
  600. if (rv != 0)
  601. dev_err(&adapter->netdev->dev,
  602. "could not configure link notification\n");
  603. return rv;
  604. }
  605. int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
  606. {
  607. struct qlcnic_nic_req req;
  608. u64 word;
  609. int rv;
  610. if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
  611. return 0;
  612. memset(&req, 0, sizeof(struct qlcnic_nic_req));
  613. req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
  614. word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
  615. ((u64)adapter->portnum << 16) |
  616. ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
  617. req.req_hdr = cpu_to_le64(word);
  618. rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
  619. if (rv != 0)
  620. dev_err(&adapter->netdev->dev,
  621. "could not cleanup lro flows\n");
  622. return rv;
  623. }
  624. /*
  625. * qlcnic_change_mtu - Change the Maximum Transfer Unit
  626. * @returns 0 on success, negative on failure
  627. */
  628. int qlcnic_change_mtu(struct net_device *netdev, int mtu)
  629. {
  630. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  631. int rc = 0;
  632. if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
  633. dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
  634. " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
  635. return -EINVAL;
  636. }
  637. rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
  638. if (!rc)
  639. netdev->mtu = mtu;
  640. return rc;
  641. }
  642. u32 qlcnic_fix_features(struct net_device *netdev, u32 features)
  643. {
  644. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  645. if ((adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
  646. u32 changed = features ^ netdev->features;
  647. features ^= changed & (NETIF_F_ALL_CSUM | NETIF_F_RXCSUM);
  648. }
  649. if (!(features & NETIF_F_RXCSUM))
  650. features &= ~NETIF_F_LRO;
  651. return features;
  652. }
  653. int qlcnic_set_features(struct net_device *netdev, u32 features)
  654. {
  655. struct qlcnic_adapter *adapter = netdev_priv(netdev);
  656. u32 changed = netdev->features ^ features;
  657. int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
  658. if (!(changed & NETIF_F_LRO))
  659. return 0;
  660. netdev->features = features ^ NETIF_F_LRO;
  661. if (qlcnic_config_hw_lro(adapter, hw_lro))
  662. return -EIO;
  663. if ((hw_lro == 0) && qlcnic_send_lro_cleanup(adapter))
  664. return -EIO;
  665. return 0;
  666. }
  667. /*
  668. * Changes the CRB window to the specified window.
  669. */
  670. /* Returns < 0 if off is not valid,
  671. * 1 if window access is needed. 'off' is set to offset from
  672. * CRB space in 128M pci map
  673. * 0 if no window access is needed. 'off' is set to 2M addr
  674. * In: 'off' is offset from base in 128M pci map
  675. */
  676. static int
  677. qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
  678. ulong off, void __iomem **addr)
  679. {
  680. const struct crb_128M_2M_sub_block_map *m;
  681. if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
  682. return -EINVAL;
  683. off -= QLCNIC_PCI_CRBSPACE;
  684. /*
  685. * Try direct map
  686. */
  687. m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
  688. if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
  689. *addr = adapter->ahw->pci_base0 + m->start_2M +
  690. (off - m->start_128M);
  691. return 0;
  692. }
  693. /*
  694. * Not in direct map, use crb window
  695. */
  696. *addr = adapter->ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
  697. return 1;
  698. }
  699. /*
  700. * In: 'off' is offset from CRB space in 128M pci map
  701. * Out: 'off' is 2M pci map addr
  702. * side effect: lock crb window
  703. */
  704. static int
  705. qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
  706. {
  707. u32 window;
  708. void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
  709. off -= QLCNIC_PCI_CRBSPACE;
  710. window = CRB_HI(off);
  711. if (window == 0) {
  712. dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
  713. return -EIO;
  714. }
  715. writel(window, addr);
  716. if (readl(addr) != window) {
  717. if (printk_ratelimit())
  718. dev_warn(&adapter->pdev->dev,
  719. "failed to set CRB window to %d off 0x%lx\n",
  720. window, off);
  721. return -EIO;
  722. }
  723. return 0;
  724. }
  725. int
  726. qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
  727. {
  728. unsigned long flags;
  729. int rv;
  730. void __iomem *addr = NULL;
  731. rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
  732. if (rv == 0) {
  733. writel(data, addr);
  734. return 0;
  735. }
  736. if (rv > 0) {
  737. /* indirect access */
  738. write_lock_irqsave(&adapter->ahw->crb_lock, flags);
  739. crb_win_lock(adapter);
  740. rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
  741. if (!rv)
  742. writel(data, addr);
  743. crb_win_unlock(adapter);
  744. write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
  745. return rv;
  746. }
  747. dev_err(&adapter->pdev->dev,
  748. "%s: invalid offset: 0x%016lx\n", __func__, off);
  749. dump_stack();
  750. return -EIO;
  751. }
  752. u32
  753. qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
  754. {
  755. unsigned long flags;
  756. int rv;
  757. u32 data = -1;
  758. void __iomem *addr = NULL;
  759. rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
  760. if (rv == 0)
  761. return readl(addr);
  762. if (rv > 0) {
  763. /* indirect access */
  764. write_lock_irqsave(&adapter->ahw->crb_lock, flags);
  765. crb_win_lock(adapter);
  766. if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
  767. data = readl(addr);
  768. crb_win_unlock(adapter);
  769. write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
  770. return data;
  771. }
  772. dev_err(&adapter->pdev->dev,
  773. "%s: invalid offset: 0x%016lx\n", __func__, off);
  774. dump_stack();
  775. return -1;
  776. }
  777. void __iomem *
  778. qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
  779. {
  780. void __iomem *addr = NULL;
  781. WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
  782. return addr;
  783. }
  784. static int
  785. qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
  786. u64 addr, u32 *start)
  787. {
  788. u32 window;
  789. window = OCM_WIN_P3P(addr);
  790. writel(window, adapter->ahw->ocm_win_crb);
  791. /* read back to flush */
  792. readl(adapter->ahw->ocm_win_crb);
  793. *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
  794. return 0;
  795. }
  796. static int
  797. qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
  798. u64 *data, int op)
  799. {
  800. void __iomem *addr;
  801. int ret;
  802. u32 start;
  803. mutex_lock(&adapter->ahw->mem_lock);
  804. ret = qlcnic_pci_set_window_2M(adapter, off, &start);
  805. if (ret != 0)
  806. goto unlock;
  807. addr = adapter->ahw->pci_base0 + start;
  808. if (op == 0) /* read */
  809. *data = readq(addr);
  810. else /* write */
  811. writeq(*data, addr);
  812. unlock:
  813. mutex_unlock(&adapter->ahw->mem_lock);
  814. return ret;
  815. }
  816. void
  817. qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
  818. {
  819. void __iomem *addr = adapter->ahw->pci_base0 +
  820. QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
  821. mutex_lock(&adapter->ahw->mem_lock);
  822. *data = readq(addr);
  823. mutex_unlock(&adapter->ahw->mem_lock);
  824. }
  825. void
  826. qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
  827. {
  828. void __iomem *addr = adapter->ahw->pci_base0 +
  829. QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
  830. mutex_lock(&adapter->ahw->mem_lock);
  831. writeq(data, addr);
  832. mutex_unlock(&adapter->ahw->mem_lock);
  833. }
  834. #define MAX_CTL_CHECK 1000
  835. int
  836. qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
  837. u64 off, u64 data)
  838. {
  839. int i, j, ret;
  840. u32 temp, off8;
  841. void __iomem *mem_crb;
  842. /* Only 64-bit aligned access */
  843. if (off & 7)
  844. return -EIO;
  845. /* P3 onward, test agent base for MIU and SIU is same */
  846. if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
  847. QLCNIC_ADDR_QDR_NET_MAX)) {
  848. mem_crb = qlcnic_get_ioaddr(adapter,
  849. QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
  850. goto correct;
  851. }
  852. if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
  853. mem_crb = qlcnic_get_ioaddr(adapter,
  854. QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
  855. goto correct;
  856. }
  857. if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
  858. return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
  859. return -EIO;
  860. correct:
  861. off8 = off & ~0xf;
  862. mutex_lock(&adapter->ahw->mem_lock);
  863. writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
  864. writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
  865. i = 0;
  866. writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
  867. writel((TA_CTL_START | TA_CTL_ENABLE),
  868. (mem_crb + TEST_AGT_CTRL));
  869. for (j = 0; j < MAX_CTL_CHECK; j++) {
  870. temp = readl(mem_crb + TEST_AGT_CTRL);
  871. if ((temp & TA_CTL_BUSY) == 0)
  872. break;
  873. }
  874. if (j >= MAX_CTL_CHECK) {
  875. ret = -EIO;
  876. goto done;
  877. }
  878. i = (off & 0xf) ? 0 : 2;
  879. writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
  880. mem_crb + MIU_TEST_AGT_WRDATA(i));
  881. writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
  882. mem_crb + MIU_TEST_AGT_WRDATA(i+1));
  883. i = (off & 0xf) ? 2 : 0;
  884. writel(data & 0xffffffff,
  885. mem_crb + MIU_TEST_AGT_WRDATA(i));
  886. writel((data >> 32) & 0xffffffff,
  887. mem_crb + MIU_TEST_AGT_WRDATA(i+1));
  888. writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
  889. writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
  890. (mem_crb + TEST_AGT_CTRL));
  891. for (j = 0; j < MAX_CTL_CHECK; j++) {
  892. temp = readl(mem_crb + TEST_AGT_CTRL);
  893. if ((temp & TA_CTL_BUSY) == 0)
  894. break;
  895. }
  896. if (j >= MAX_CTL_CHECK) {
  897. if (printk_ratelimit())
  898. dev_err(&adapter->pdev->dev,
  899. "failed to write through agent\n");
  900. ret = -EIO;
  901. } else
  902. ret = 0;
  903. done:
  904. mutex_unlock(&adapter->ahw->mem_lock);
  905. return ret;
  906. }
  907. int
  908. qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
  909. u64 off, u64 *data)
  910. {
  911. int j, ret;
  912. u32 temp, off8;
  913. u64 val;
  914. void __iomem *mem_crb;
  915. /* Only 64-bit aligned access */
  916. if (off & 7)
  917. return -EIO;
  918. /* P3 onward, test agent base for MIU and SIU is same */
  919. if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
  920. QLCNIC_ADDR_QDR_NET_MAX)) {
  921. mem_crb = qlcnic_get_ioaddr(adapter,
  922. QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
  923. goto correct;
  924. }
  925. if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
  926. mem_crb = qlcnic_get_ioaddr(adapter,
  927. QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
  928. goto correct;
  929. }
  930. if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
  931. return qlcnic_pci_mem_access_direct(adapter,
  932. off, data, 0);
  933. }
  934. return -EIO;
  935. correct:
  936. off8 = off & ~0xf;
  937. mutex_lock(&adapter->ahw->mem_lock);
  938. writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
  939. writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
  940. writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
  941. writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
  942. for (j = 0; j < MAX_CTL_CHECK; j++) {
  943. temp = readl(mem_crb + TEST_AGT_CTRL);
  944. if ((temp & TA_CTL_BUSY) == 0)
  945. break;
  946. }
  947. if (j >= MAX_CTL_CHECK) {
  948. if (printk_ratelimit())
  949. dev_err(&adapter->pdev->dev,
  950. "failed to read through agent\n");
  951. ret = -EIO;
  952. } else {
  953. off8 = MIU_TEST_AGT_RDDATA_LO;
  954. if (off & 0xf)
  955. off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
  956. temp = readl(mem_crb + off8 + 4);
  957. val = (u64)temp << 32;
  958. val |= readl(mem_crb + off8);
  959. *data = val;
  960. ret = 0;
  961. }
  962. mutex_unlock(&adapter->ahw->mem_lock);
  963. return ret;
  964. }
  965. int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
  966. {
  967. int offset, board_type, magic;
  968. struct pci_dev *pdev = adapter->pdev;
  969. offset = QLCNIC_FW_MAGIC_OFFSET;
  970. if (qlcnic_rom_fast_read(adapter, offset, &magic))
  971. return -EIO;
  972. if (magic != QLCNIC_BDINFO_MAGIC) {
  973. dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
  974. magic);
  975. return -EIO;
  976. }
  977. offset = QLCNIC_BRDTYPE_OFFSET;
  978. if (qlcnic_rom_fast_read(adapter, offset, &board_type))
  979. return -EIO;
  980. adapter->ahw->board_type = board_type;
  981. if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
  982. u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
  983. if ((gpio & 0x8000) == 0)
  984. board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
  985. }
  986. switch (board_type) {
  987. case QLCNIC_BRDTYPE_P3P_HMEZ:
  988. case QLCNIC_BRDTYPE_P3P_XG_LOM:
  989. case QLCNIC_BRDTYPE_P3P_10G_CX4:
  990. case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
  991. case QLCNIC_BRDTYPE_P3P_IMEZ:
  992. case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
  993. case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
  994. case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
  995. case QLCNIC_BRDTYPE_P3P_10G_XFP:
  996. case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
  997. adapter->ahw->port_type = QLCNIC_XGBE;
  998. break;
  999. case QLCNIC_BRDTYPE_P3P_REF_QG:
  1000. case QLCNIC_BRDTYPE_P3P_4_GB:
  1001. case QLCNIC_BRDTYPE_P3P_4_GB_MM:
  1002. adapter->ahw->port_type = QLCNIC_GBE;
  1003. break;
  1004. case QLCNIC_BRDTYPE_P3P_10G_TP:
  1005. adapter->ahw->port_type = (adapter->portnum < 2) ?
  1006. QLCNIC_XGBE : QLCNIC_GBE;
  1007. break;
  1008. default:
  1009. dev_err(&pdev->dev, "unknown board type %x\n", board_type);
  1010. adapter->ahw->port_type = QLCNIC_XGBE;
  1011. break;
  1012. }
  1013. return 0;
  1014. }
  1015. int
  1016. qlcnic_wol_supported(struct qlcnic_adapter *adapter)
  1017. {
  1018. u32 wol_cfg;
  1019. wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
  1020. if (wol_cfg & (1UL << adapter->portnum)) {
  1021. wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
  1022. if (wol_cfg & (1 << adapter->portnum))
  1023. return 1;
  1024. }
  1025. return 0;
  1026. }
  1027. int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
  1028. {
  1029. struct qlcnic_nic_req req;
  1030. int rv;
  1031. u64 word;
  1032. memset(&req, 0, sizeof(struct qlcnic_nic_req));
  1033. req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
  1034. word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
  1035. req.req_hdr = cpu_to_le64(word);
  1036. req.words[0] = cpu_to_le64((u64)rate << 32);
  1037. req.words[1] = cpu_to_le64(state);
  1038. rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
  1039. if (rv)
  1040. dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
  1041. return rv;
  1042. }
  1043. /* FW dump related functions */
  1044. static u32
  1045. qlcnic_dump_crb(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
  1046. u32 *buffer)
  1047. {
  1048. int i;
  1049. u32 addr, data;
  1050. struct __crb *crb = &entry->region.crb;
  1051. void __iomem *base = adapter->ahw->pci_base0;
  1052. addr = crb->addr;
  1053. for (i = 0; i < crb->no_ops; i++) {
  1054. QLCNIC_RD_DUMP_REG(addr, base, &data);
  1055. *buffer++ = cpu_to_le32(addr);
  1056. *buffer++ = cpu_to_le32(data);
  1057. addr += crb->stride;
  1058. }
  1059. return crb->no_ops * 2 * sizeof(u32);
  1060. }
  1061. static u32
  1062. qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
  1063. struct qlcnic_dump_entry *entry, u32 *buffer)
  1064. {
  1065. int i, k, timeout = 0;
  1066. void __iomem *base = adapter->ahw->pci_base0;
  1067. u32 addr, data;
  1068. u8 opcode, no_ops;
  1069. struct __ctrl *ctr = &entry->region.ctrl;
  1070. struct qlcnic_dump_template_hdr *t_hdr = adapter->ahw->fw_dump.tmpl_hdr;
  1071. addr = ctr->addr;
  1072. no_ops = ctr->no_ops;
  1073. for (i = 0; i < no_ops; i++) {
  1074. k = 0;
  1075. opcode = 0;
  1076. for (k = 0; k < 8; k++) {
  1077. if (!(ctr->opcode & (1 << k)))
  1078. continue;
  1079. switch (1 << k) {
  1080. case QLCNIC_DUMP_WCRB:
  1081. QLCNIC_WR_DUMP_REG(addr, base, ctr->val1);
  1082. break;
  1083. case QLCNIC_DUMP_RWCRB:
  1084. QLCNIC_RD_DUMP_REG(addr, base, &data);
  1085. QLCNIC_WR_DUMP_REG(addr, base, data);
  1086. break;
  1087. case QLCNIC_DUMP_ANDCRB:
  1088. QLCNIC_RD_DUMP_REG(addr, base, &data);
  1089. QLCNIC_WR_DUMP_REG(addr, base,
  1090. (data & ctr->val2));
  1091. break;
  1092. case QLCNIC_DUMP_ORCRB:
  1093. QLCNIC_RD_DUMP_REG(addr, base, &data);
  1094. QLCNIC_WR_DUMP_REG(addr, base,
  1095. (data | ctr->val3));
  1096. break;
  1097. case QLCNIC_DUMP_POLLCRB:
  1098. while (timeout <= ctr->timeout) {
  1099. QLCNIC_RD_DUMP_REG(addr, base, &data);
  1100. if ((data & ctr->val2) == ctr->val1)
  1101. break;
  1102. msleep(1);
  1103. timeout++;
  1104. }
  1105. if (timeout > ctr->timeout) {
  1106. dev_info(&adapter->pdev->dev,
  1107. "Timed out, aborting poll CRB\n");
  1108. return -EINVAL;
  1109. }
  1110. break;
  1111. case QLCNIC_DUMP_RD_SAVE:
  1112. if (ctr->index_a)
  1113. addr = t_hdr->saved_state[ctr->index_a];
  1114. QLCNIC_RD_DUMP_REG(addr, base, &data);
  1115. t_hdr->saved_state[ctr->index_v] = data;
  1116. break;
  1117. case QLCNIC_DUMP_WRT_SAVED:
  1118. if (ctr->index_v)
  1119. data = t_hdr->saved_state[ctr->index_v];
  1120. else
  1121. data = ctr->val1;
  1122. if (ctr->index_a)
  1123. addr = t_hdr->saved_state[ctr->index_a];
  1124. QLCNIC_WR_DUMP_REG(addr, base, data);
  1125. break;
  1126. case QLCNIC_DUMP_MOD_SAVE_ST:
  1127. data = t_hdr->saved_state[ctr->index_v];
  1128. data <<= ctr->shl_val;
  1129. data >>= ctr->shr_val;
  1130. if (ctr->val2)
  1131. data &= ctr->val2;
  1132. data |= ctr->val3;
  1133. data += ctr->val1;
  1134. t_hdr->saved_state[ctr->index_v] = data;
  1135. break;
  1136. default:
  1137. dev_info(&adapter->pdev->dev,
  1138. "Unknown opcode\n");
  1139. break;
  1140. }
  1141. }
  1142. addr += ctr->stride;
  1143. }
  1144. return 0;
  1145. }
  1146. static u32
  1147. qlcnic_dump_mux(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
  1148. u32 *buffer)
  1149. {
  1150. int loop;
  1151. u32 val, data = 0;
  1152. struct __mux *mux = &entry->region.mux;
  1153. void __iomem *base = adapter->ahw->pci_base0;
  1154. val = mux->val;
  1155. for (loop = 0; loop < mux->no_ops; loop++) {
  1156. QLCNIC_WR_DUMP_REG(mux->addr, base, val);
  1157. QLCNIC_RD_DUMP_REG(mux->read_addr, base, &data);
  1158. *buffer++ = cpu_to_le32(val);
  1159. *buffer++ = cpu_to_le32(data);
  1160. val += mux->val_stride;
  1161. }
  1162. return 2 * mux->no_ops * sizeof(u32);
  1163. }
  1164. static u32
  1165. qlcnic_dump_que(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
  1166. u32 *buffer)
  1167. {
  1168. int i, loop;
  1169. u32 cnt, addr, data, que_id = 0;
  1170. void __iomem *base = adapter->ahw->pci_base0;
  1171. struct __queue *que = &entry->region.que;
  1172. addr = que->read_addr;
  1173. cnt = que->read_addr_cnt;
  1174. for (loop = 0; loop < que->no_ops; loop++) {
  1175. QLCNIC_WR_DUMP_REG(que->sel_addr, base, que_id);
  1176. addr = que->read_addr;
  1177. for (i = 0; i < cnt; i++) {
  1178. QLCNIC_RD_DUMP_REG(addr, base, &data);
  1179. *buffer++ = cpu_to_le32(data);
  1180. addr += que->read_addr_stride;
  1181. }
  1182. que_id += que->stride;
  1183. }
  1184. return que->no_ops * cnt * sizeof(u32);
  1185. }
  1186. static u32
  1187. qlcnic_dump_ocm(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
  1188. u32 *buffer)
  1189. {
  1190. int i;
  1191. u32 data;
  1192. void __iomem *addr;
  1193. struct __ocm *ocm = &entry->region.ocm;
  1194. addr = adapter->ahw->pci_base0 + ocm->read_addr;
  1195. for (i = 0; i < ocm->no_ops; i++) {
  1196. data = readl(addr);
  1197. *buffer++ = cpu_to_le32(data);
  1198. addr += ocm->read_addr_stride;
  1199. }
  1200. return ocm->no_ops * sizeof(u32);
  1201. }
  1202. static u32
  1203. qlcnic_read_rom(struct qlcnic_adapter *adapter, struct qlcnic_dump_entry *entry,
  1204. u32 *buffer)
  1205. {
  1206. int i, count = 0;
  1207. u32 fl_addr, size, val, lck_val, addr;
  1208. struct __mem *rom = &entry->region.mem;
  1209. void __iomem *base = adapter->ahw->pci_base0;
  1210. fl_addr = rom->addr;
  1211. size = rom->size/4;
  1212. lock_try:
  1213. lck_val = readl(base + QLCNIC_FLASH_SEM2_LK);
  1214. if (!lck_val && count < MAX_CTL_CHECK) {
  1215. msleep(10);
  1216. count++;
  1217. goto lock_try;
  1218. }
  1219. writel(adapter->ahw->pci_func, (base + QLCNIC_FLASH_LOCK_ID));
  1220. for (i = 0; i < size; i++) {
  1221. addr = fl_addr & 0xFFFF0000;
  1222. QLCNIC_WR_DUMP_REG(FLASH_ROM_WINDOW, base, addr);
  1223. addr = LSW(fl_addr) + FLASH_ROM_DATA;
  1224. QLCNIC_RD_DUMP_REG(addr, base, &val);
  1225. fl_addr += 4;
  1226. *buffer++ = cpu_to_le32(val);
  1227. }
  1228. readl(base + QLCNIC_FLASH_SEM2_ULK);
  1229. return rom->size;
  1230. }
  1231. static u32
  1232. qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter,
  1233. struct qlcnic_dump_entry *entry, u32 *buffer)
  1234. {
  1235. int i;
  1236. u32 cnt, val, data, addr;
  1237. void __iomem *base = adapter->ahw->pci_base0;
  1238. struct __cache *l1 = &entry->region.cache;
  1239. val = l1->init_tag_val;
  1240. for (i = 0; i < l1->no_ops; i++) {
  1241. QLCNIC_WR_DUMP_REG(l1->addr, base, val);
  1242. QLCNIC_WR_DUMP_REG(l1->ctrl_addr, base, LSW(l1->ctrl_val));
  1243. addr = l1->read_addr;
  1244. cnt = l1->read_addr_num;
  1245. while (cnt) {
  1246. QLCNIC_RD_DUMP_REG(addr, base, &data);
  1247. *buffer++ = cpu_to_le32(data);
  1248. addr += l1->read_addr_stride;
  1249. cnt--;
  1250. }
  1251. val += l1->stride;
  1252. }
  1253. return l1->no_ops * l1->read_addr_num * sizeof(u32);
  1254. }
  1255. static u32
  1256. qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter,
  1257. struct qlcnic_dump_entry *entry, u32 *buffer)
  1258. {
  1259. int i;
  1260. u32 cnt, val, data, addr;
  1261. u8 poll_mask, poll_to, time_out = 0;
  1262. void __iomem *base = adapter->ahw->pci_base0;
  1263. struct __cache *l2 = &entry->region.cache;
  1264. val = l2->init_tag_val;
  1265. poll_mask = LSB(MSW(l2->ctrl_val));
  1266. poll_to = MSB(MSW(l2->ctrl_val));
  1267. for (i = 0; i < l2->no_ops; i++) {
  1268. QLCNIC_WR_DUMP_REG(l2->addr, base, val);
  1269. do {
  1270. QLCNIC_WR_DUMP_REG(l2->ctrl_addr, base,
  1271. LSW(l2->ctrl_val));
  1272. QLCNIC_RD_DUMP_REG(l2->ctrl_addr, base, &data);
  1273. if (!(data & poll_mask))
  1274. break;
  1275. msleep(1);
  1276. time_out++;
  1277. } while (time_out <= poll_to);
  1278. if (time_out > poll_to)
  1279. return -EINVAL;
  1280. addr = l2->read_addr;
  1281. cnt = l2->read_addr_num;
  1282. while (cnt) {
  1283. QLCNIC_RD_DUMP_REG(addr, base, &data);
  1284. *buffer++ = cpu_to_le32(data);
  1285. addr += l2->read_addr_stride;
  1286. cnt--;
  1287. }
  1288. val += l2->stride;
  1289. }
  1290. return l2->no_ops * l2->read_addr_num * sizeof(u32);
  1291. }
  1292. static u32
  1293. qlcnic_read_memory(struct qlcnic_adapter *adapter,
  1294. struct qlcnic_dump_entry *entry, u32 *buffer)
  1295. {
  1296. u32 addr, data, test, ret = 0;
  1297. int i, reg_read;
  1298. struct __mem *mem = &entry->region.mem;
  1299. void __iomem *base = adapter->ahw->pci_base0;
  1300. reg_read = mem->size;
  1301. addr = mem->addr;
  1302. /* check for data size of multiple of 16 and 16 byte alignment */
  1303. if ((addr & 0xf) || (reg_read%16)) {
  1304. dev_info(&adapter->pdev->dev,
  1305. "Unaligned memory addr:0x%x size:0x%x\n",
  1306. addr, reg_read);
  1307. return -EINVAL;
  1308. }
  1309. mutex_lock(&adapter->ahw->mem_lock);
  1310. while (reg_read != 0) {
  1311. QLCNIC_WR_DUMP_REG(MIU_TEST_ADDR_LO, base, addr);
  1312. QLCNIC_WR_DUMP_REG(MIU_TEST_ADDR_HI, base, 0);
  1313. QLCNIC_WR_DUMP_REG(MIU_TEST_CTR, base,
  1314. TA_CTL_ENABLE | TA_CTL_START);
  1315. for (i = 0; i < MAX_CTL_CHECK; i++) {
  1316. QLCNIC_RD_DUMP_REG(MIU_TEST_CTR, base, &test);
  1317. if (!(test & TA_CTL_BUSY))
  1318. break;
  1319. }
  1320. if (i == MAX_CTL_CHECK) {
  1321. if (printk_ratelimit()) {
  1322. dev_err(&adapter->pdev->dev,
  1323. "failed to read through agent\n");
  1324. ret = -EINVAL;
  1325. goto out;
  1326. }
  1327. }
  1328. for (i = 0; i < 4; i++) {
  1329. QLCNIC_RD_DUMP_REG(MIU_TEST_READ_DATA[i], base, &data);
  1330. *buffer++ = cpu_to_le32(data);
  1331. }
  1332. addr += 16;
  1333. reg_read -= 16;
  1334. ret += 16;
  1335. }
  1336. out:
  1337. mutex_unlock(&adapter->ahw->mem_lock);
  1338. return mem->size;
  1339. }
  1340. static u32
  1341. qlcnic_dump_nop(struct qlcnic_adapter *adapter,
  1342. struct qlcnic_dump_entry *entry, u32 *buffer)
  1343. {
  1344. entry->hdr.flags |= QLCNIC_DUMP_SKIP;
  1345. return 0;
  1346. }
  1347. struct qlcnic_dump_operations fw_dump_ops[] = {
  1348. { QLCNIC_DUMP_NOP, qlcnic_dump_nop },
  1349. { QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb },
  1350. { QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux },
  1351. { QLCNIC_DUMP_QUEUE, qlcnic_dump_que },
  1352. { QLCNIC_DUMP_BRD_CONFIG, qlcnic_read_rom },
  1353. { QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm },
  1354. { QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl },
  1355. { QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache },
  1356. { QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache },
  1357. { QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache },
  1358. { QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache },
  1359. { QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache },
  1360. { QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache },
  1361. { QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache },
  1362. { QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache },
  1363. { QLCNIC_DUMP_READ_ROM, qlcnic_read_rom },
  1364. { QLCNIC_DUMP_READ_MEM, qlcnic_read_memory },
  1365. { QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl },
  1366. { QLCNIC_DUMP_TLHDR, qlcnic_dump_nop },
  1367. { QLCNIC_DUMP_RDEND, qlcnic_dump_nop },
  1368. };
  1369. /* Walk the template and collect dump for each entry in the dump template */
  1370. static int
  1371. qlcnic_valid_dump_entry(struct device *dev, struct qlcnic_dump_entry *entry,
  1372. u32 size)
  1373. {
  1374. int ret = 1;
  1375. if (size != entry->hdr.cap_size) {
  1376. dev_info(dev,
  1377. "Invalidate dump, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
  1378. entry->hdr.type, entry->hdr.mask, size, entry->hdr.cap_size);
  1379. dev_info(dev, "Aborting further dump capture\n");
  1380. ret = 0;
  1381. }
  1382. return ret;
  1383. }
  1384. int qlcnic_dump_fw(struct qlcnic_adapter *adapter)
  1385. {
  1386. u32 *buffer;
  1387. char mesg[64];
  1388. char *msg[] = {mesg, NULL};
  1389. int i, k, ops_cnt, ops_index, dump_size = 0;
  1390. u32 entry_offset, dump, no_entries, buf_offset = 0;
  1391. struct qlcnic_dump_entry *entry;
  1392. struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
  1393. struct qlcnic_dump_template_hdr *tmpl_hdr = fw_dump->tmpl_hdr;
  1394. if (fw_dump->clr) {
  1395. dev_info(&adapter->pdev->dev,
  1396. "Previous dump not cleared, not capturing dump\n");
  1397. return -EIO;
  1398. }
  1399. /* Calculate the size for dump data area only */
  1400. for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++)
  1401. if (i & tmpl_hdr->drv_cap_mask)
  1402. dump_size += tmpl_hdr->cap_sizes[k];
  1403. if (!dump_size)
  1404. return -EIO;
  1405. fw_dump->data = vzalloc(dump_size);
  1406. if (!fw_dump->data) {
  1407. dev_info(&adapter->pdev->dev,
  1408. "Unable to allocate (%d KB) for fw dump\n",
  1409. dump_size/1024);
  1410. return -ENOMEM;
  1411. }
  1412. buffer = fw_dump->data;
  1413. fw_dump->size = dump_size;
  1414. no_entries = tmpl_hdr->num_entries;
  1415. ops_cnt = ARRAY_SIZE(fw_dump_ops);
  1416. entry_offset = tmpl_hdr->offset;
  1417. tmpl_hdr->sys_info[0] = QLCNIC_DRIVER_VERSION;
  1418. tmpl_hdr->sys_info[1] = adapter->fw_version;
  1419. for (i = 0; i < no_entries; i++) {
  1420. entry = (struct qlcnic_dump_entry *) ((void *) tmpl_hdr +
  1421. entry_offset);
  1422. if (!(entry->hdr.mask & tmpl_hdr->drv_cap_mask)) {
  1423. entry->hdr.flags |= QLCNIC_DUMP_SKIP;
  1424. entry_offset += entry->hdr.offset;
  1425. continue;
  1426. }
  1427. /* Find the handler for this entry */
  1428. ops_index = 0;
  1429. while (ops_index < ops_cnt) {
  1430. if (entry->hdr.type == fw_dump_ops[ops_index].opcode)
  1431. break;
  1432. ops_index++;
  1433. }
  1434. if (ops_index == ops_cnt) {
  1435. dev_info(&adapter->pdev->dev,
  1436. "Invalid entry type %d, exiting dump\n",
  1437. entry->hdr.type);
  1438. goto error;
  1439. }
  1440. /* Collect dump for this entry */
  1441. dump = fw_dump_ops[ops_index].handler(adapter, entry, buffer);
  1442. if (dump && !qlcnic_valid_dump_entry(&adapter->pdev->dev, entry,
  1443. dump))
  1444. entry->hdr.flags |= QLCNIC_DUMP_SKIP;
  1445. buf_offset += entry->hdr.cap_size;
  1446. entry_offset += entry->hdr.offset;
  1447. buffer = fw_dump->data + buf_offset;
  1448. }
  1449. if (dump_size != buf_offset) {
  1450. dev_info(&adapter->pdev->dev,
  1451. "Captured(%d) and expected size(%d) do not match\n",
  1452. buf_offset, dump_size);
  1453. goto error;
  1454. } else {
  1455. fw_dump->clr = 1;
  1456. snprintf(mesg, sizeof(mesg), "FW dump for device: %d\n",
  1457. adapter->pdev->devfn);
  1458. dev_info(&adapter->pdev->dev, "Dump data, %d bytes captured\n",
  1459. fw_dump->size);
  1460. /* Send a udev event to notify availability of FW dump */
  1461. kobject_uevent_env(&adapter->pdev->dev.kobj, KOBJ_CHANGE, msg);
  1462. return 0;
  1463. }
  1464. error:
  1465. vfree(fw_dump->data);
  1466. return -EINVAL;
  1467. }